TW200717716A - Semiconductor structure and method for forming the semiconductor structure - Google Patents
Semiconductor structure and method for forming the semiconductor structureInfo
- Publication number
- TW200717716A TW200717716A TW095109587A TW95109587A TW200717716A TW 200717716 A TW200717716 A TW 200717716A TW 095109587 A TW095109587 A TW 095109587A TW 95109587 A TW95109587 A TW 95109587A TW 200717716 A TW200717716 A TW 200717716A
- Authority
- TW
- Taiwan
- Prior art keywords
- device area
- gate layer
- semiconductor structure
- forming
- layer
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/903—FET configuration adapted for use as static memory cell
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/257,572 US7485934B2 (en) | 2005-10-25 | 2005-10-25 | Integrated semiconductor structure for SRAM cells |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200717716A true TW200717716A (en) | 2007-05-01 |
TWI321829B TWI321829B (en) | 2010-03-11 |
Family
ID=37984536
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW095109587A TWI321829B (en) | 2005-10-25 | 2006-03-21 | Semiconductor structure and method for forming the semiconductor structure |
Country Status (3)
Country | Link |
---|---|
US (1) | US7485934B2 (zh) |
CN (1) | CN100470833C (zh) |
TW (1) | TWI321829B (zh) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8448102B2 (en) | 2006-03-09 | 2013-05-21 | Tela Innovations, Inc. | Optimizing layout of irregular structures in regular layout context |
US8653857B2 (en) | 2006-03-09 | 2014-02-18 | Tela Innovations, Inc. | Circuitry and layouts for XOR and XNOR logic |
US8658542B2 (en) | 2006-03-09 | 2014-02-25 | Tela Innovations, Inc. | Coarse grid design methods and structures |
US9035359B2 (en) | 2006-03-09 | 2015-05-19 | Tela Innovations, Inc. | Semiconductor chip including region including linear-shaped conductive structures forming gate electrodes and having electrical connection areas arranged relative to inner region between transistors of different types and associated methods |
US7763534B2 (en) | 2007-10-26 | 2010-07-27 | Tela Innovations, Inc. | Methods, structures and designs for self-aligning local interconnects used in integrated circuits |
US9230910B2 (en) | 2006-03-09 | 2016-01-05 | Tela Innovations, Inc. | Oversized contacts and vias in layout defined by linearly constrained topology |
US9563733B2 (en) | 2009-05-06 | 2017-02-07 | Tela Innovations, Inc. | Cell circuit and layout with linear finfet structures |
US7956421B2 (en) | 2008-03-13 | 2011-06-07 | Tela Innovations, Inc. | Cross-coupled transistor layouts in restricted gate level layout architecture |
US7446352B2 (en) | 2006-03-09 | 2008-11-04 | Tela Innovations, Inc. | Dynamic array architecture |
US8839175B2 (en) | 2006-03-09 | 2014-09-16 | Tela Innovations, Inc. | Scalable meta-data objects |
US8541879B2 (en) | 2007-12-13 | 2013-09-24 | Tela Innovations, Inc. | Super-self-aligned contacts and method for making the same |
US9009641B2 (en) | 2006-03-09 | 2015-04-14 | Tela Innovations, Inc. | Circuits with linear finfet structures |
KR100842472B1 (ko) * | 2006-12-27 | 2008-07-01 | 동부일렉트로닉스 주식회사 | 칩 면적 축소를 위한 반도체 소자의 구조 및 제조 방법 |
US7869262B2 (en) * | 2007-01-29 | 2011-01-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Memory device with an asymmetric layout structure |
US7888705B2 (en) | 2007-08-02 | 2011-02-15 | Tela Innovations, Inc. | Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same |
US8667443B2 (en) | 2007-03-05 | 2014-03-04 | Tela Innovations, Inc. | Integrated circuit cell library for multiple patterning |
US8188550B2 (en) * | 2007-12-27 | 2012-05-29 | Globalfoundries Singapore Pte. Ltd. | Integrated circuit structure with electrical strap and its method of forming |
US8453094B2 (en) | 2008-01-31 | 2013-05-28 | Tela Innovations, Inc. | Enforcement of semiconductor structure regularity for localized transistors and interconnect |
US7939443B2 (en) | 2008-03-27 | 2011-05-10 | Tela Innovations, Inc. | Methods for multi-wire routing and apparatus implementing same |
KR101761530B1 (ko) | 2008-07-16 | 2017-07-25 | 텔라 이노베이션스, 인코포레이티드 | 동적 어레이 아키텍쳐에서의 셀 페이징과 배치를 위한 방법 및 그 구현 |
US9122832B2 (en) | 2008-08-01 | 2015-09-01 | Tela Innovations, Inc. | Methods for controlling microloading variation in semiconductor wafer layout and fabrication |
US8661392B2 (en) | 2009-10-13 | 2014-02-25 | Tela Innovations, Inc. | Methods for cell boundary encroachment and layouts implementing the Same |
US8212295B2 (en) | 2010-06-30 | 2012-07-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | ROM cell circuit for FinFET devices |
US8675397B2 (en) | 2010-06-25 | 2014-03-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cell structure for dual-port SRAM |
US8942030B2 (en) | 2010-06-25 | 2015-01-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for SRAM cell circuit |
US8399931B2 (en) | 2010-06-30 | 2013-03-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout for multiple-fin SRAM cell |
US8315084B2 (en) * | 2010-03-10 | 2012-11-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fully balanced dual-port memory cell |
KR101914798B1 (ko) * | 2010-07-20 | 2018-11-02 | 유니버시티 오브 버지니아 페이턴트 파운데이션 | 메모리 셀 |
US9159627B2 (en) | 2010-11-12 | 2015-10-13 | Tela Innovations, Inc. | Methods for linewidth modification and apparatus implementing the same |
US8735972B2 (en) * | 2011-09-08 | 2014-05-27 | International Business Machines Corporation | SRAM cell having recessed storage node connections and method of fabricating same |
US9911727B2 (en) | 2015-03-16 | 2018-03-06 | Taiwan Semiconductor Manufacturing Company, Ltd. | Strapping structure of memory circuit |
DE102016118207A1 (de) * | 2015-12-30 | 2017-07-06 | Taiwan Semiconductor Manufacturing Co. Ltd. | Halbleitervorrichtung und verfahren zu ihrer herstellung |
US10804148B2 (en) * | 2017-08-25 | 2020-10-13 | International Business Machines Corporation | Buried contact to provide reduced VFET feature-to-feature tolerance requirements |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0758773B2 (ja) * | 1989-07-14 | 1995-06-21 | 三菱電機株式会社 | 半導体装置の製造方法及び半導体装置 |
JP2001044294A (ja) * | 1999-08-02 | 2001-02-16 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6583518B2 (en) * | 2001-08-31 | 2003-06-24 | Micron Technology, Inc. | Cross-diffusion resistant dual-polycide semiconductor structure and method |
US6700163B2 (en) * | 2001-12-07 | 2004-03-02 | International Business Machines Corporation | Selective silicide blocking |
JP3914114B2 (ja) * | 2002-08-12 | 2007-05-16 | 株式会社東芝 | 半導体装置およびその製造方法 |
-
2005
- 2005-10-25 US US11/257,572 patent/US7485934B2/en active Active
-
2006
- 2006-03-21 TW TW095109587A patent/TWI321829B/zh active
- 2006-04-12 CN CNB2006100735022A patent/CN100470833C/zh active Active
Also Published As
Publication number | Publication date |
---|---|
CN1956216A (zh) | 2007-05-02 |
CN100470833C (zh) | 2009-03-18 |
TWI321829B (en) | 2010-03-11 |
US7485934B2 (en) | 2009-02-03 |
US20070090428A1 (en) | 2007-04-26 |
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