TW200714159A - Circuit board structure and method for fabricating the same - Google Patents

Circuit board structure and method for fabricating the same

Info

Publication number
TW200714159A
TW200714159A TW094132953A TW94132953A TW200714159A TW 200714159 A TW200714159 A TW 200714159A TW 094132953 A TW094132953 A TW 094132953A TW 94132953 A TW94132953 A TW 94132953A TW 200714159 A TW200714159 A TW 200714159A
Authority
TW
Taiwan
Prior art keywords
metal layer
openings
layer
fabricating
circuit board
Prior art date
Application number
TW094132953A
Other languages
Chinese (zh)
Other versions
TWI302429B (en
Inventor
Chien-Chih Chen
I-Wen Huang
E-Tung Chou
Wei-Tien Tsai
Original Assignee
Phoenix Prec Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Phoenix Prec Technology Corp filed Critical Phoenix Prec Technology Corp
Priority to TW94132953A priority Critical patent/TWI302429B/en
Publication of TW200714159A publication Critical patent/TW200714159A/en
Application granted granted Critical
Publication of TWI302429B publication Critical patent/TWI302429B/en

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

A circuit board structure and a method for fabricating the same are proposed. A core board with a first metal layer and a second metal layer opposed to the first metal layer is provided. A plurality of first openings are formed on the first metal layer and a plurality of second openings corresponding to the first openings are formed on the second metal layer. A through hole is formed and through the first and second openings. A conductive layer is formed on the first metal layer, the second metal layer and the surface of the through hole. A thickened metal layer is formed on the conductive layer, and a conductive via is formed by sealing the second opening. The thickened metal layer is patterned to form a first and a second circuit layers on the top and bottom surfaces of the core board respectively, and the first and the second circuit layers are electrically connected by the conductive via, wherein the second circuit layer located at the bottom of conductive via has a electrically connected pad formed thereon. Therefore, the drawbacks of prior processes are avoided, the reliability is improved, and cost is reduced because specified machines are not used.
TW94132953A 2005-09-23 2005-09-23 Circuit board structure and method for fabricating the same TWI302429B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW94132953A TWI302429B (en) 2005-09-23 2005-09-23 Circuit board structure and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW94132953A TWI302429B (en) 2005-09-23 2005-09-23 Circuit board structure and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200714159A true TW200714159A (en) 2007-04-01
TWI302429B TWI302429B (en) 2008-10-21

Family

ID=45070483

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94132953A TWI302429B (en) 2005-09-23 2005-09-23 Circuit board structure and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI302429B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111163582A (en) * 2020-01-02 2020-05-15 上海航天电子通讯设备研究所 Vertical interconnection substrate based on laser nano-machining technology and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111163582A (en) * 2020-01-02 2020-05-15 上海航天电子通讯设备研究所 Vertical interconnection substrate based on laser nano-machining technology and manufacturing method thereof
CN111163582B (en) * 2020-01-02 2022-01-25 上海航天电子通讯设备研究所 Vertical interconnection substrate based on laser nano-machining technology and manufacturing method thereof

Also Published As

Publication number Publication date
TWI302429B (en) 2008-10-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees