TW200713513A - Memory structure with high coupling ratio and forming method thereof - Google Patents
Memory structure with high coupling ratio and forming method thereofInfo
- Publication number
- TW200713513A TW200713513A TW094130391A TW94130391A TW200713513A TW 200713513 A TW200713513 A TW 200713513A TW 094130391 A TW094130391 A TW 094130391A TW 94130391 A TW94130391 A TW 94130391A TW 200713513 A TW200713513 A TW 200713513A
- Authority
- TW
- Taiwan
- Prior art keywords
- trench isolation
- shallow trench
- forming method
- memory structure
- coupling ratio
- Prior art date
Links
- 230000008878 coupling Effects 0.000 title 1
- 238000010168 coupling process Methods 0.000 title 1
- 238000005859 coupling reaction Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
- 238000002955 isolation Methods 0.000 abstract 6
- 125000006850 spacer group Chemical group 0.000 abstract 3
- 239000000758 substrate Substances 0.000 abstract 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094130391A TWI288966B (en) | 2005-09-05 | 2005-09-05 | Memory structure with high coupling ratio and forming method thereof |
US11/272,683 US7535050B2 (en) | 2005-09-05 | 2005-11-15 | Memory structure with high coupling ratio |
US11/272,685 US20070052003A1 (en) | 2005-09-05 | 2005-11-15 | Method for producing a memory with high coupling ratio |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW094130391A TWI288966B (en) | 2005-09-05 | 2005-09-05 | Memory structure with high coupling ratio and forming method thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200713513A true TW200713513A (en) | 2007-04-01 |
TWI288966B TWI288966B (en) | 2007-10-21 |
Family
ID=37829254
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW094130391A TWI288966B (en) | 2005-09-05 | 2005-09-05 | Memory structure with high coupling ratio and forming method thereof |
Country Status (2)
Country | Link |
---|---|
US (2) | US20070052003A1 (zh) |
TW (1) | TWI288966B (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100723437B1 (ko) * | 2006-05-30 | 2007-05-30 | 삼성전자주식회사 | 반도체 플래시 메모리 소자 및 그 제조 방법 |
CN105097704B (zh) * | 2014-05-04 | 2018-02-16 | 中芯国际集成电路制造(上海)有限公司 | 闪存器件及其形成方法 |
US9825046B2 (en) * | 2016-01-05 | 2017-11-21 | Taiwan Semiconductor Manufacturing Co., Ltd. | Flash memory device having high coupling ratio |
US20210143275A1 (en) * | 2019-11-11 | 2021-05-13 | Integrated Silicon Solution Inc. | Finfet stack gate memory and mehod of forming thereof |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5686329A (en) * | 1995-12-29 | 1997-11-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a metal oxide semiconductor field effect transistor (MOSFET) having improved hot carrier immunity |
US5710054A (en) * | 1996-08-26 | 1998-01-20 | Advanced Micro Devices, Inc. | Method of forming a shallow junction by diffusion from a silicon-based spacer |
TW405265B (en) * | 1999-01-30 | 2000-09-11 | United Microelectronics Corp | Flash memory structure and its manufacture method |
US6376868B1 (en) * | 1999-06-15 | 2002-04-23 | Micron Technology, Inc. | Multi-layered gate for a CMOS imager |
US6232630B1 (en) * | 1999-07-07 | 2001-05-15 | Advanced Micro Devices, Inc. | Light floating gate doping to improve tunnel oxide reliability |
JP2001189439A (ja) | 2000-01-05 | 2001-07-10 | Mitsubishi Electric Corp | 不揮発性半導体記憶装置の製造方法及び不揮発性半導体記憶装置 |
KR100338783B1 (en) * | 2000-10-28 | 2002-06-01 | Samsung Electronics Co Ltd | Semiconductor device having expanded effective width of active region and fabricating method thereof |
US6563167B2 (en) * | 2001-01-05 | 2003-05-13 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with floating gates having multiple sharp edges |
US6576537B2 (en) * | 2001-08-08 | 2003-06-10 | Vanguard International Semiconductor Corp. | Flash memory cell and method for fabricating a flash memory cell |
US6532176B1 (en) * | 2001-09-25 | 2003-03-11 | Tower Semiconductor Ltd. | Non-volatile memory array with equalized bit line potentials |
TW573344B (en) * | 2002-05-24 | 2004-01-21 | Nanya Technology Corp | Separated gate flash memory and its manufacturing method |
US20040224469A1 (en) * | 2003-05-08 | 2004-11-11 | The Board Of Trustees Of The University Of Illinois | Method for forming a strained semiconductor substrate |
JP2004349341A (ja) * | 2003-05-20 | 2004-12-09 | Sharp Corp | 半導体記憶素子、半導体装置およびそれらの製造方法、携帯電子機器並びにicカード |
US20050006795A1 (en) * | 2003-07-09 | 2005-01-13 | Cheng-Ming Yih | Corner free structure of nonvolatile memory |
-
2005
- 2005-09-05 TW TW094130391A patent/TWI288966B/zh active
- 2005-11-15 US US11/272,685 patent/US20070052003A1/en not_active Abandoned
- 2005-11-15 US US11/272,683 patent/US7535050B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
US20070052003A1 (en) | 2007-03-08 |
US20070052008A1 (en) | 2007-03-08 |
TWI288966B (en) | 2007-10-21 |
US7535050B2 (en) | 2009-05-19 |
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