TW200713329A - Delay locked loop circuit - Google Patents

Delay locked loop circuit

Info

Publication number
TW200713329A
TW200713329A TW095123923A TW95123923A TW200713329A TW 200713329 A TW200713329 A TW 200713329A TW 095123923 A TW095123923 A TW 095123923A TW 95123923 A TW95123923 A TW 95123923A TW 200713329 A TW200713329 A TW 200713329A
Authority
TW
Taiwan
Prior art keywords
power down
down mode
dll
locked loop
delay locked
Prior art date
Application number
TW095123923A
Other languages
Chinese (zh)
Other versions
TWI308345B (en
Inventor
Hoon Choi
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200713329A publication Critical patent/TW200713329A/en
Application granted granted Critical
Publication of TWI308345B publication Critical patent/TWI308345B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Power Sources (AREA)

Abstract

A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a DLL clock having frozen locking information when exiting the power down mode. A controller precludes phase update operation of the DLL when a predetermined time passes after entering the power down mode to thereby obtain a time margin for a phase update operation undertaken in the normal mode.
TW095123923A 2005-09-29 2006-06-30 Delay locked loop circuit TWI308345B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050091671 2005-09-29
KR1020050117122A KR100733465B1 (en) 2005-09-29 2005-12-02 Delay locked loop circuit

Publications (2)

Publication Number Publication Date
TW200713329A true TW200713329A (en) 2007-04-01
TWI308345B TWI308345B (en) 2009-04-01

Family

ID=37959241

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123923A TWI308345B (en) 2005-09-29 2006-06-30 Delay locked loop circuit

Country Status (3)

Country Link
KR (1) KR100733465B1 (en)
CN (1) CN100545942C (en)
TW (1) TWI308345B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401693B (en) * 2009-01-05 2013-07-11 Nanya Technology Corp Voltage providing circuit, and signal delaying system utilizing the voltage providing circuit
TWI749849B (en) * 2019-12-23 2021-12-11 南亞科技股份有限公司 Delay-locked loop, memory device, and method for operating delay-locked loop

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100907002B1 (en) * 2007-07-12 2009-07-08 주식회사 하이닉스반도체 Delay Locked Loop And Method For controlling The Same
KR100881401B1 (en) * 2007-11-02 2009-02-02 주식회사 하이닉스반도체 Circuit for synchronization of clock and method for synchronization of clock
KR100892726B1 (en) * 2007-12-21 2009-04-10 주식회사 하이닉스반도체 Voltage generating circuit for delay locked loop and semiconductor memory devce including the same and method for generating voltage for delay locked loop
KR100902058B1 (en) * 2008-01-07 2009-06-09 주식회사 하이닉스반도체 Semiconductor integrated circuit and method of controlling the same
KR100940849B1 (en) 2008-08-08 2010-02-09 주식회사 하이닉스반도체 Semiconductor integrated circuit and method of controlling the same
KR101923023B1 (en) 2011-08-10 2018-11-28 에스케이하이닉스 주식회사 Delay locked loop
CN102570780A (en) * 2011-09-20 2012-07-11 广东美的电器股份有限公司 Intelligent power module
US9047237B2 (en) * 2012-08-03 2015-06-02 Cypress Semiconductor Corporation Power savings apparatus and method for memory device using delay locked loop
CN104317361B (en) * 2014-10-27 2017-08-04 杭州中天微系统有限公司 A kind of cyclic buffer for postponing to update based on pointer
KR20200091679A (en) * 2019-01-23 2020-07-31 에스케이하이닉스 주식회사 Memory system and operation method thereof
CN114625360B (en) * 2022-05-16 2022-10-21 西安数道航空技术有限公司 Coupling-free digital development platform and system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492794B1 (en) * 1997-12-24 2005-08-23 주식회사 하이닉스반도체 Rambus DRAM Power-Down Shutdown Control

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI401693B (en) * 2009-01-05 2013-07-11 Nanya Technology Corp Voltage providing circuit, and signal delaying system utilizing the voltage providing circuit
TWI749849B (en) * 2019-12-23 2021-12-11 南亞科技股份有限公司 Delay-locked loop, memory device, and method for operating delay-locked loop

Also Published As

Publication number Publication date
TWI308345B (en) 2009-04-01
KR100733465B1 (en) 2007-06-29
CN1941177A (en) 2007-04-04
KR20070036547A (en) 2007-04-03
CN100545942C (en) 2009-09-30

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