TW200713830A - Delay locked loop circuit - Google Patents

Delay locked loop circuit

Info

Publication number
TW200713830A
TW200713830A TW095123709A TW95123709A TW200713830A TW 200713830 A TW200713830 A TW 200713830A TW 095123709 A TW095123709 A TW 095123709A TW 95123709 A TW95123709 A TW 95123709A TW 200713830 A TW200713830 A TW 200713830A
Authority
TW
Taiwan
Prior art keywords
delay
circuit
locked loop
delay locked
tck
Prior art date
Application number
TW095123709A
Other languages
Chinese (zh)
Other versions
TWI339508B (en
Inventor
Hwang Hur
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200713830A publication Critical patent/TW200713830A/en
Application granted granted Critical
Publication of TWI339508B publication Critical patent/TWI339508B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a DRAM is abruptly changed, the locking state can be recovered within a certain time, e.g., 200 tCK, by creating an internal reset signal in the DLL circuit by a circuit that monitors the state and then conducting a phase update using a rough delay value.
TW095123709A 2005-09-29 2006-06-30 Delay locked loop circuit TWI339508B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR20050090966 2005-09-29
KR1020050130880A KR100804154B1 (en) 2005-09-29 2005-12-27 Delay locked loop circuit

Publications (2)

Publication Number Publication Date
TW200713830A true TW200713830A (en) 2007-04-01
TWI339508B TWI339508B (en) 2011-03-21

Family

ID=37959239

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095123709A TWI339508B (en) 2005-09-29 2006-06-30 Delay locked loop circuit

Country Status (3)

Country Link
KR (1) KR100804154B1 (en)
CN (1) CN1941173B (en)
TW (1) TWI339508B (en)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100856070B1 (en) * 2007-03-30 2008-09-02 주식회사 하이닉스반도체 Semiconductor memory device and driving method thereof
US7577056B2 (en) * 2007-04-14 2009-08-18 Taiwan Semiconductor Manufacturing Co., Ltd. System and method for using a DLL for signal timing control in a eDRAM
KR100930416B1 (en) * 2008-08-11 2009-12-08 주식회사 하이닉스반도체 Semiconductor integrated circuit and method of controlling the same
KR101019985B1 (en) 2008-09-10 2011-03-11 주식회사 하이닉스반도체 A delay locked loop circuit and a method of controlling thereof
KR101022674B1 (en) 2008-12-05 2011-03-22 주식회사 하이닉스반도체 Delay locked loop circuit and operating method thereof
US8310292B1 (en) * 2011-07-13 2012-11-13 Nanya Technology Corp. Method for resetting DLL with frequency change application
KR101965397B1 (en) * 2012-05-25 2019-04-03 에스케이하이닉스 주식회사 Semiconductor Apparatus
JP5714622B2 (en) * 2013-02-21 2015-05-07 トヨタ自動車株式会社 Control device
CN104242921B (en) * 2014-09-30 2017-12-19 西安紫光国芯半导体有限公司 A kind of high frequency delay phase-locked loop and its clock processing method
US9614533B2 (en) * 2015-06-19 2017-04-04 Intel Corporation Digital phase control with programmable tracking slope
US10460790B1 (en) * 2018-05-14 2019-10-29 Nanya Technology Corporation Detecting circuit, DRAM, and method for determining a refresh frequency for a delay-locked loop module
TWI685206B (en) * 2019-07-17 2020-02-11 瑞昱半導體股份有限公司 Phase-locked loop circuit
TWI732558B (en) * 2020-05-18 2021-07-01 華邦電子股份有限公司 Delay-locked loop device and operation method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6937680B2 (en) * 2001-04-24 2005-08-30 Sun Microsystems, Inc. Source synchronous receiver link initialization and input floating control by clock detection and DLL lock detection

Also Published As

Publication number Publication date
CN1941173B (en) 2012-02-22
KR20070036564A (en) 2007-04-03
CN1941173A (en) 2007-04-04
TWI339508B (en) 2011-03-21
KR100804154B1 (en) 2008-02-19

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