TW200709270A - Epitaxial imprinting - Google Patents

Epitaxial imprinting

Info

Publication number
TW200709270A
TW200709270A TW095125603A TW95125603A TW200709270A TW 200709270 A TW200709270 A TW 200709270A TW 095125603 A TW095125603 A TW 095125603A TW 95125603 A TW95125603 A TW 95125603A TW 200709270 A TW200709270 A TW 200709270A
Authority
TW
Taiwan
Prior art keywords
epitaxial
present
semiconductor layer
layer
imprinting
Prior art date
Application number
TW095125603A
Other languages
English (en)
Inventor
Toshiharu Furukawa
Carl Radens
William R Tonti
Richard Q Williams
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of TW200709270A publication Critical patent/TW200709270A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
    • H01L29/045—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes by their particular orientation of crystalline planes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Recrystallisation Techniques (AREA)
TW095125603A 2005-07-15 2006-07-13 Epitaxial imprinting TW200709270A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/182,381 US7217629B2 (en) 2005-07-15 2005-07-15 Epitaxial imprinting

Publications (1)

Publication Number Publication Date
TW200709270A true TW200709270A (en) 2007-03-01

Family

ID=37609732

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095125603A TW200709270A (en) 2005-07-15 2006-07-13 Epitaxial imprinting

Country Status (3)

Country Link
US (2) US7217629B2 (zh)
CN (1) CN100466267C (zh)
TW (1) TW200709270A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI393627B (zh) * 2008-12-04 2013-04-21 Asml Netherlands Bv 壓印微影裝置及方法
TWI402160B (zh) * 2008-10-23 2013-07-21 Molecular Imprints Inc 高通量奈米壓印微影術模板之製造技術

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090245838A1 (en) * 2008-03-26 2009-10-01 David William Shuman Fuser heater temperature control
FR2938117B1 (fr) * 2008-10-31 2011-04-15 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride ayant une couche continue electriquement isolante enterree
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
CN102822970B (zh) * 2010-03-31 2015-06-17 Soitec公司 键合半导体结构及其形成方法
US9396948B2 (en) * 2013-05-03 2016-07-19 Texas Instruments Incorporated Layer transfer of silicon onto III-nitride material for heterogenous integration
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01162376A (ja) * 1987-12-18 1989-06-26 Fujitsu Ltd 半導体装置の製造方法
US7329923B2 (en) * 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US6830962B1 (en) * 2003-08-05 2004-12-14 International Business Machines Corporation Self-aligned SOI with different crystal orientation using wafer bonding and SIMOX processes
US6815278B1 (en) * 2003-08-25 2004-11-09 International Business Machines Corporation Ultra-thin silicon-on-insulator and strained-silicon-direct-on-insulator with hybrid crystal orientations
US20050116290A1 (en) * 2003-12-02 2005-06-02 De Souza Joel P. Planar substrate with selected semiconductor crystal orientations formed by localized amorphization and recrystallization of stacked template layers
US7060585B1 (en) * 2005-02-16 2006-06-13 International Business Machines Corporation Hybrid orientation substrates by in-place bonding and amorphization/templated recrystallization

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI402160B (zh) * 2008-10-23 2013-07-21 Molecular Imprints Inc 高通量奈米壓印微影術模板之製造技術
TWI393627B (zh) * 2008-12-04 2013-04-21 Asml Netherlands Bv 壓印微影裝置及方法
TWI494209B (zh) * 2008-12-04 2015-08-01 Asml Netherlands Bv 壓印微影裝置及方法

Also Published As

Publication number Publication date
US20070145373A1 (en) 2007-06-28
CN100466267C (zh) 2009-03-04
US7217629B2 (en) 2007-05-15
US7732865B2 (en) 2010-06-08
CN1897286A (zh) 2007-01-17
US20070013001A1 (en) 2007-01-18

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