TW200705649A - Method for manufacturing SIMOX wafer and SIMOX wafer manufactured thereby - Google Patents

Method for manufacturing SIMOX wafer and SIMOX wafer manufactured thereby

Info

Publication number
TW200705649A
TW200705649A TW094125293A TW94125293A TW200705649A TW 200705649 A TW200705649 A TW 200705649A TW 094125293 A TW094125293 A TW 094125293A TW 94125293 A TW94125293 A TW 94125293A TW 200705649 A TW200705649 A TW 200705649A
Authority
TW
Taiwan
Prior art keywords
silicon wafer
simox wafer
manufacturing
oxygen ions
etching
Prior art date
Application number
TW094125293A
Other languages
Chinese (zh)
Other versions
TWI263329B (en
Inventor
Isao Takahashi
Tetsuya Nakai
Original Assignee
Sumitomo Mitsubishi Silicon
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Mitsubishi Silicon filed Critical Sumitomo Mitsubishi Silicon
Application granted granted Critical
Publication of TWI263329B publication Critical patent/TWI263329B/en
Publication of TW200705649A publication Critical patent/TW200705649A/en

Links

Landscapes

  • Weting (AREA)
  • Cleaning Or Drying Semiconductors (AREA)
  • Element Separation (AREA)

Abstract

This method for manufacturing a SIMOX wafer includes a step of doping oxygen ions in a silicon wafer, a step of cleaning the silicon wafer in which the oxygen ions were doped, and a step of annealing the silicon wafer which was cleaned, thereby forming a buried oxide layer in the silicon wafer, wherein the method further comprises a step of soaking the silicon wafer in a hydrofluoric acid solution after doping the oxygen ions and before cleaning the silicon wafer, thereby etching a SiO2 layer which is formed in a surface of the silicon wafer, and an etching rate of the hydrofluoric acid solution which is used in the step of etching to etch the SiO2 layer is from 150 to 3000 Å/min.
TW94125293A 2004-01-30 2005-07-26 Method for manufacturing SIMOX wafer and SIMOX wafer manufactured thereby TWI263329B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004024330A JP2005217312A (en) 2004-01-30 2004-01-30 Method for manufacturing simox wafer and simox wafer manufactured by the method

Publications (2)

Publication Number Publication Date
TWI263329B TWI263329B (en) 2006-10-01
TW200705649A true TW200705649A (en) 2007-02-01

Family

ID=34907048

Family Applications (1)

Application Number Title Priority Date Filing Date
TW94125293A TWI263329B (en) 2004-01-30 2005-07-26 Method for manufacturing SIMOX wafer and SIMOX wafer manufactured thereby

Country Status (2)

Country Link
JP (1) JP2005217312A (en)
TW (1) TWI263329B (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007227424A (en) * 2006-02-21 2007-09-06 Sumco Corp Production process of simox wafer
CN102623304B (en) * 2011-01-30 2015-03-25 陈柏颖 Wafer suitable for nanometer technology and method for manufacturing the same
US11798802B2 (en) 2022-02-11 2023-10-24 Globalwafers Co., Ltd. Methods for stripping and cleaning semiconductor structures

Also Published As

Publication number Publication date
TWI263329B (en) 2006-10-01
JP2005217312A (en) 2005-08-11

Similar Documents

Publication Publication Date Title
KR100560578B1 (en) Method for limiting divot formation in post shallow trench isolation processes
US7709341B2 (en) Methods of shaping vertical single crystal silicon walls and resulting structures
CN104103520B (en) Form the method and FinFET structure of fin FET device
CN101459116B (en) Shallow groove isolation construction manufacturing method
JP4634923B2 (en) Insulating film manufacturing method, transistor manufacturing method, and electronic device manufacturing method
DE60140379D1 (en) SOI / GLASS PROCESS FOR THE PRODUCTION OF THIN MICROPRODUCTED STRUCTURES
US20060216906A1 (en) Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
TW200601489A (en) STI formation in semiconductor device including SOI and bulk silicon regions
KR20090045130A (en) Method for manufacturing soi substrate
TW200710991A (en) Semiconductor structures formed on substrates and methods of manufacturing the same
WO2010122023A3 (en) Method to thin a silicon-on-insulator substrate
CN101770974A (en) Method for fabricating shallow-trench isolation structure
TW201029050A (en) Method of forming a semiconductor layer
TW461025B (en) Method for rounding corner of shallow trench isolation
CN101577252B (en) Shallow trench isolation structure and method for forming same
TW200705649A (en) Method for manufacturing SIMOX wafer and SIMOX wafer manufactured thereby
US20130122684A1 (en) Semiconductor process for removing oxide layer
CN104637881A (en) Method for forming shallow trench isolation structure
CN103137467A (en) Semiconductor manufacturing process for removing oxide layer
US20030181014A1 (en) Method of manufacturing semiconductor device with STI
CN102479716B (en) Manufacturing method of transistor
CN101314852B (en) Etching solution, method of surface modification of semiconductor substrate and method of forming shallow trench isolation
CN104637797A (en) Method for treating ILD (injection laser diode) layer in gate-last technology
KR20060072498A (en) Semiconductor device and fabrication method thereof
US11211259B2 (en) Structure and method for embedded gettering in a silicon on insulator wafer

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees