TW200701311A - Method of fabricating conductive lines and structure of the same - Google Patents

Method of fabricating conductive lines and structure of the same

Info

Publication number
TW200701311A
TW200701311A TW094120391A TW94120391A TW200701311A TW 200701311 A TW200701311 A TW 200701311A TW 094120391 A TW094120391 A TW 094120391A TW 94120391 A TW94120391 A TW 94120391A TW 200701311 A TW200701311 A TW 200701311A
Authority
TW
Taiwan
Prior art keywords
layer
conductive lines
same
conductive
patterned mask
Prior art date
Application number
TW094120391A
Other languages
English (en)
Other versions
TWI254352B (en
Inventor
Jui-Pin Chang
Chien-Hung Liu
Ying-Tso Chen
Shou-Wei Huang
Original Assignee
Macronix Int Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Macronix Int Co Ltd filed Critical Macronix Int Co Ltd
Priority to TW094120391A priority Critical patent/TWI254352B/zh
Priority to US11/236,961 priority patent/US7307018B2/en
Application granted granted Critical
Publication of TWI254352B publication Critical patent/TWI254352B/zh
Publication of TW200701311A publication Critical patent/TW200701311A/zh
Priority to US11/929,391 priority patent/US20080048346A1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5283—Cross-sectional geometry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
TW094120391A 2005-06-20 2005-06-20 Method of fabricating conductive lines and structure of the same TWI254352B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW094120391A TWI254352B (en) 2005-06-20 2005-06-20 Method of fabricating conductive lines and structure of the same
US11/236,961 US7307018B2 (en) 2005-06-20 2005-09-27 Method of fabricating conductive lines
US11/929,391 US20080048346A1 (en) 2005-06-20 2007-10-30 Method of fabricating conductive lines and structure of the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW094120391A TWI254352B (en) 2005-06-20 2005-06-20 Method of fabricating conductive lines and structure of the same

Publications (2)

Publication Number Publication Date
TWI254352B TWI254352B (en) 2006-05-01
TW200701311A true TW200701311A (en) 2007-01-01

Family

ID=37573912

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094120391A TWI254352B (en) 2005-06-20 2005-06-20 Method of fabricating conductive lines and structure of the same

Country Status (2)

Country Link
US (2) US7307018B2 (zh)
TW (1) TWI254352B (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100641980B1 (ko) * 2004-12-17 2006-11-02 동부일렉트로닉스 주식회사 반도체 소자의 배선 및 그 형성방법

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2544396B2 (ja) * 1987-08-25 1996-10-16 株式会社日立製作所 半導体集積回路装置の製造方法
US5017515A (en) * 1989-10-02 1991-05-21 Texas Instruments Incorporated Process for minimizing lateral distance between elements in an integrated circuit by using sidewall spacers
US5210435A (en) * 1990-10-12 1993-05-11 Motorola, Inc. ITLDD transistor having a variable work function
US5238872A (en) 1990-12-11 1993-08-24 Samsung Semiconductor, Inc. Barrier metal contact architecture
US5270254A (en) * 1991-03-27 1993-12-14 Sgs-Thomson Microelectronics, Inc. Integrated circuit metallization with zero contact enclosure requirements and method of making the same
JPH06310492A (ja) * 1993-04-23 1994-11-04 Fuji Xerox Co Ltd チタン系薄膜のエッチング液及び半導体装置の製造方法
US5639688A (en) * 1993-05-21 1997-06-17 Harris Corporation Method of making integrated circuit structure with narrow line widths
US5538921A (en) * 1994-12-22 1996-07-23 At&T Corp. Integrated circuit fabrication
TW330310B (en) * 1997-07-22 1998-04-21 Winbond Electronics Corp Inter-metal dielectric planarization method
JP3453289B2 (ja) * 1997-11-28 2003-10-06 沖電気工業株式会社 半導体装置及びその製造方法
KR100289389B1 (ko) * 1998-03-05 2001-06-01 김영환 반도체소자의캐패시터제조방법
TW451402B (en) * 1999-04-19 2001-08-21 United Microelectronics Corp Manufacturing method of inter-metal dielectric layer
KR100374228B1 (ko) * 2001-03-28 2003-03-03 주식회사 하이닉스반도체 금속배선 형성 방법
US6525342B2 (en) 2001-05-23 2003-02-25 International Business Machines Corporation Low resistance wiring in the periphery region of displays
KR20030044619A (ko) * 2001-11-30 2003-06-09 주식회사 하이닉스반도체 반도체 소자의 배선 형성 방법
US20040203231A1 (en) * 2003-04-14 2004-10-14 Jung-Yuan Hsieh Method for forming a semiconductor device with a contact plug
KR100579850B1 (ko) * 2003-12-31 2006-05-12 동부일렉트로닉스 주식회사 모스 전계효과 트랜지스터의 제조 방법
US6815337B1 (en) * 2004-02-17 2004-11-09 Episil Technologies, Inc. Method to improve borderless metal line process window for sub-micron designs
KR100641980B1 (ko) * 2004-12-17 2006-11-02 동부일렉트로닉스 주식회사 반도체 소자의 배선 및 그 형성방법

Also Published As

Publication number Publication date
US20080048346A1 (en) 2008-02-28
TWI254352B (en) 2006-05-01
US20060286731A1 (en) 2006-12-21
US7307018B2 (en) 2007-12-11

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