TW200644203A - Semiconductor apparatus and lead frame - Google Patents

Semiconductor apparatus and lead frame

Info

Publication number
TW200644203A
TW200644203A TW095113022A TW95113022A TW200644203A TW 200644203 A TW200644203 A TW 200644203A TW 095113022 A TW095113022 A TW 095113022A TW 95113022 A TW95113022 A TW 95113022A TW 200644203 A TW200644203 A TW 200644203A
Authority
TW
Taiwan
Prior art keywords
wire
island
bonded
semiconductor apparatus
bonding area
Prior art date
Application number
TW095113022A
Other languages
Chinese (zh)
Inventor
Hideki Hiromoto
Sadamasa Fujii
Tsunemori Yamaguchi
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Publication of TW200644203A publication Critical patent/TW200644203A/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/27011—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature
    • H01L2224/27013—Involving a permanent auxiliary member, i.e. a member which is left at least partly in the finished device, e.g. coating, dummy feature for holding or confining the layer connector, e.g. solder flow barrier
    • H—ELECTRICITY
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    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/4805—Shape
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    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/491—Disposition
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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    • H01L2924/01004—Beryllium [Be]
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    • H01L2924/01082—Lead [Pb]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)

Abstract

To provide a semiconductor apparatus to surely prevent a wire wire-bonded by an island from breaking by a thermal shock, a temperature cycle or the like on mounting it or the like, for example. The semiconductor apparatus includes a semiconductor chip 11, the island 12 on whose surface the semiconductor chip 11 is die-bonded, and the wire 14 which connects an electrode 11a formed on the surface of the semiconductor chip 11 and the island 12 electrically. The island 12 has a die bonding area 12a where the semiconductor chip 11 is die-bonded and a wire bonding area 12b where the wire 14 is wire-bonded. The semiconductor apparatus 10 forms a continuous groove 17 reaching the periphery 12c of the island between the die bonding area 12a and the wire bonding area 12b in the island 12.
TW095113022A 2005-04-13 2006-04-12 Semiconductor apparatus and lead frame TW200644203A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005116051A JP2006294998A (en) 2005-04-13 2005-04-13 Semiconductor apparatus and lead frame

Publications (1)

Publication Number Publication Date
TW200644203A true TW200644203A (en) 2006-12-16

Family

ID=37115056

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095113022A TW200644203A (en) 2005-04-13 2006-04-12 Semiconductor apparatus and lead frame

Country Status (6)

Country Link
US (1) US7638860B2 (en)
JP (1) JP2006294998A (en)
KR (1) KR20070114312A (en)
CN (1) CN100514623C (en)
TW (1) TW200644203A (en)
WO (1) WO2006112332A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102428558B (en) 2009-05-15 2014-06-25 罗姆股份有限公司 Semiconductor device
KR101113518B1 (en) * 2009-11-18 2012-02-29 삼성전기주식회사 lead frame
JP2014099534A (en) * 2012-11-15 2014-05-29 Dainippon Printing Co Ltd Lead frame and manufacturing method of the same, and semiconductor device and manufacturing method of the same
JP2014130925A (en) * 2012-12-28 2014-07-10 Dainippon Printing Co Ltd Lead frame and manufacturing method of the same, and semiconductor device and manufacturing method of the same
JP2015233114A (en) * 2014-05-13 2015-12-24 株式会社デンソー Semiconductor device
WO2019049213A1 (en) * 2017-09-05 2019-03-14 新電元工業株式会社 Semiconductor device

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10247701A (en) * 1997-03-05 1998-09-14 Hitachi Ltd Semiconductor device and lead frame for manufacturing the same
JP3062691B1 (en) * 1999-02-26 2000-07-12 株式会社三井ハイテック Semiconductor device
JP2001313363A (en) * 2000-05-01 2001-11-09 Rohm Co Ltd Resin-encapsulated semiconductor device
JP2002016206A (en) 2000-06-28 2002-01-18 Rohm Co Ltd Semiconductor device
JP3895570B2 (en) * 2000-12-28 2007-03-22 株式会社ルネサステクノロジ Semiconductor device
US6661083B2 (en) * 2001-02-27 2003-12-09 Chippac, Inc Plastic semiconductor package
US6608375B2 (en) * 2001-04-06 2003-08-19 Oki Electric Industry Co., Ltd. Semiconductor apparatus with decoupling capacitor
US7262491B2 (en) * 2005-09-06 2007-08-28 Advanced Interconnect Technologies Limited Die pad for semiconductor packages and methods of making and using same
US8536689B2 (en) * 2005-10-03 2013-09-17 Stats Chippac Ltd. Integrated circuit package system with multi-surface die attach pad

Also Published As

Publication number Publication date
US7638860B2 (en) 2009-12-29
KR20070114312A (en) 2007-11-30
US20090032919A1 (en) 2009-02-05
JP2006294998A (en) 2006-10-26
CN100514623C (en) 2009-07-15
CN101160659A (en) 2008-04-09
WO2006112332A1 (en) 2006-10-26

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