TW200641685A - Digital signal system with accelerators and method for operating the same - Google Patents

Digital signal system with accelerators and method for operating the same

Info

Publication number
TW200641685A
TW200641685A TW095110931A TW95110931A TW200641685A TW 200641685 A TW200641685 A TW 200641685A TW 095110931 A TW095110931 A TW 095110931A TW 95110931 A TW95110931 A TW 95110931A TW 200641685 A TW200641685 A TW 200641685A
Authority
TW
Taiwan
Prior art keywords
accelerator
dsp processor
instruction
accelerators
operating
Prior art date
Application number
TW095110931A
Other languages
English (en)
Inventor
Ivo Tousek
Tommy Eriksson
Niklas Persson
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW200641685A publication Critical patent/TW200641685A/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
TW095110931A 2005-03-29 2006-03-29 Digital signal system with accelerators and method for operating the same TW200641685A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/093,195 US20060230213A1 (en) 2005-03-29 2005-03-29 Digital signal system with accelerators and method for operating the same

Publications (1)

Publication Number Publication Date
TW200641685A true TW200641685A (en) 2006-12-01

Family

ID=36918888

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095110931A TW200641685A (en) 2005-03-29 2006-03-29 Digital signal system with accelerators and method for operating the same

Country Status (3)

Country Link
US (1) US20060230213A1 (zh)
CN (1) CN100382016C (zh)
TW (1) TW200641685A (zh)

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US7865703B2 (en) * 2006-05-05 2011-01-04 International Business Machines Corporation Method and apparatus for executing instrumentation code within alternative processor resources
US20070261032A1 (en) * 2006-05-05 2007-11-08 Chen Wen-Tzer T Method and apparatus for hardware assisted profiling of code
US8245199B2 (en) * 2006-05-05 2012-08-14 International Business Machines Corporation Selectively marking and executing instrumentation code
US20070260849A1 (en) * 2006-05-05 2007-11-08 Chen Wen-Tzer T Method and apparatus for executing instrumentation code using a target processor
US7783866B2 (en) * 2006-05-05 2010-08-24 International Business Machines Corporation Method and apparatus for executing instrumentation code using processor instructions
GB0700877D0 (en) * 2007-01-17 2007-02-21 Linear Algebra Technologies Lt A device
US7827383B2 (en) * 2007-03-09 2010-11-02 Oracle America, Inc. Efficient on-chip accelerator interfaces to reduce software overhead
US7809895B2 (en) * 2007-03-09 2010-10-05 Oracle America, Inc. Low overhead access to shared on-chip hardware accelerator with memory-based interfaces
CN104142907B (zh) * 2013-05-10 2018-02-27 联想(北京)有限公司 增强型处理器、处理方法和电子设备
CN110289849B (zh) * 2013-09-20 2023-08-11 阿尔特拉公司 用于信号处理的混合架构
US10599441B2 (en) * 2017-09-04 2020-03-24 Mellanox Technologies, Ltd. Code sequencer that, in response to a primary processing unit encountering a trigger instruction, receives a thread identifier, executes predefined instruction sequences, and offloads computations to at least one accelerator
EP3933664A4 (en) * 2019-07-31 2022-04-06 Huawei Technologies Co., Ltd. INTEGRATED CHIP AND SENSOR DATA PROCESSING
US11874897B2 (en) 2020-04-09 2024-01-16 Micron Technology, Inc. Integrated circuit device with deep learning accelerator and random access memory
US11726784B2 (en) 2020-04-09 2023-08-15 Micron Technology, Inc. Patient monitoring using edge servers having deep learning accelerator and random access memory
US11355175B2 (en) * 2020-04-09 2022-06-07 Micron Technology, Inc. Deep learning accelerator and random access memory with a camera interface
US11887647B2 (en) 2020-04-09 2024-01-30 Micron Technology, Inc. Deep learning accelerator and random access memory with separate memory access connections

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US5440740A (en) * 1992-10-13 1995-08-08 Chen; Fetchi System and method for managing devices on multiple digital signal processors
JPH10340128A (ja) * 1997-06-10 1998-12-22 Hitachi Ltd データ処理装置及び移動体通信端末装置
WO2000004482A2 (en) * 1998-07-17 2000-01-27 Intergraph Corporation Multi-processor graphics accelerator
US6434689B2 (en) * 1998-11-09 2002-08-13 Infineon Technologies North America Corp. Data processing unit with interface for sharing registers by a processor and a coprocessor
US6275891B1 (en) * 1999-02-25 2001-08-14 Lsi Logic Corporation Modular and scalable system for signal and multimedia processing
JP2000307594A (ja) * 1999-04-21 2000-11-02 Nec Corp Ａｖ機器の機能の最適処理分散システム
GB2366012B (en) * 2000-08-14 2002-08-14 Sun Microsystems Inc A computer system
US20020049859A1 (en) * 2000-08-25 2002-04-25 William Bruckert Clustered computer system and a method of forming and controlling the clustered computer system
US6854053B2 (en) * 2000-10-25 2005-02-08 Signet Scientific Company Method for identifying and communicating with a plurality of slaves in a master-slave system
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US20030005261A1 (en) * 2001-06-29 2003-01-02 Gad Sheaffer Method and apparatus for attaching accelerator hardware containing internal state to a processing core
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US20040019704A1 (en) * 2002-05-15 2004-01-29 Barton Sano Multiple processor integrated circuit having configurable packet-based interfaces
US7430652B2 (en) * 2003-03-28 2008-09-30 Tarari, Inc. Devices for performing multiple independent hardware acceleration operations and methods for performing same
US7714870B2 (en) * 2003-06-23 2010-05-11 Intel Corporation Apparatus and method for selectable hardware accelerators in a data driven architecture
TWI234714B (en) * 2003-12-03 2005-06-21 Ind Tech Res Inst Reconfigurable radio processor architecture

Also Published As

Publication number Publication date
CN100382016C (zh) 2008-04-16
US20060230213A1 (en) 2006-10-12
CN1818856A (zh) 2006-08-16

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