TW200641665A - Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability - Google Patents

Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

Info

Publication number
TW200641665A
TW200641665A TW095131462A TW95131462A TW200641665A TW 200641665 A TW200641665 A TW 200641665A TW 095131462 A TW095131462 A TW 095131462A TW 95131462 A TW95131462 A TW 95131462A TW 200641665 A TW200641665 A TW 200641665A
Authority
TW
Taiwan
Prior art keywords
error detection
line error
output bits
parallel output
systolic array
Prior art date
Application number
TW095131462A
Other languages
English (en)
Chinese (zh)
Other versions
TWI325560B (https=
Inventor
Chiou-Yng Lee
Qi-Wen Qiu
Original Assignee
Univ Lunghwa Sci & Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Univ Lunghwa Sci & Technology filed Critical Univ Lunghwa Sci & Technology
Priority to TW095131462A priority Critical patent/TW200641665A/zh
Publication of TW200641665A publication Critical patent/TW200641665A/zh
Application granted granted Critical
Publication of TWI325560B publication Critical patent/TWI325560B/zh

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Error Detection And Correction (AREA)
TW095131462A 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability TW200641665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW095131462A TW200641665A (en) 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW095131462A TW200641665A (en) 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

Publications (2)

Publication Number Publication Date
TW200641665A true TW200641665A (en) 2006-12-01
TWI325560B TWI325560B (https=) 2010-06-01

Family

ID=45074272

Family Applications (1)

Application Number Title Priority Date Filing Date
TW095131462A TW200641665A (en) 2006-08-25 2006-08-25 Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability

Country Status (1)

Country Link
TW (1) TW200641665A (https=)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI457751B (zh) * 2012-07-13 2014-10-21 Univ Feng Chia Tandem fault tolerant device
TWI465958B (zh) * 2012-06-08 2014-12-21 Univ Lunghwa Sci & Technology Error detection of finite field multiplication devices
CN116739042A (zh) * 2023-06-09 2023-09-12 中科南京智能技术研究院 支持四种单比特计算模式的脉动阵列结构及计算模式控制方法

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI465958B (zh) * 2012-06-08 2014-12-21 Univ Lunghwa Sci & Technology Error detection of finite field multiplication devices
TWI457751B (zh) * 2012-07-13 2014-10-21 Univ Feng Chia Tandem fault tolerant device
CN116739042A (zh) * 2023-06-09 2023-09-12 中科南京智能技术研究院 支持四种单比特计算模式的脉动阵列结构及计算模式控制方法

Also Published As

Publication number Publication date
TWI325560B (https=) 2010-06-01

Similar Documents

Publication Publication Date Title
Lee A power-aware scalable pipelined Booth multiplier
EP2391010A3 (en) A programmable logic device having complex logic blocks with improved logic cell functionality
WO2004075403A3 (en) Electronic circuit with array of programmable logic cells
TW200746651A (en) Cyclic redundancy check circuit and semiconductor device having the cyclic redundancy check circuit
TW200634744A (en) Method and system for syndrome generation and data recovery
WO2010016888A3 (en) Computing module for efficient fft and fir hardware accelerator
TW200702980A (en) Error-correcting apparatus including multiple error-correcting modules functioning in parallel and related method
Chiou et al. Concurrent error detection and correction in Gaussian normal basis multiplier over GF (2^ m)
TW200641665A (en) Systolic array dual-basis multiplier having parallel output bits with on-line error detection capability
TW200943725A (en) Programmable delay circuit with integer and fractional time resolution
Hong et al. Efficient online self-checking modulo 2^ n+ 1 multiplier design
WO2008002510A3 (en) Nonlinear associative memories using linear arrays of associative memory cells, and methods of operating same
ATE456091T1 (de) Schnelles redundantes datenverarbeitungssystem
Menon et al. A reconfigurable multi-modulus modulo multiplier
Nikoubin et al. A New Cell Design Methodology for Balanced XOR–XNOR Circuits for Hybrid-CMOS Logic
CN101216752B (zh) 一种二元域乘法器
Chelton et al. Concurrent error detection in GF (2 m) multiplication and its application in elliptic curve cryptography
WO2007029166A3 (en) Full-adder modules and multiplier devices using the same
Paradhasaradhi et al. An area efficient enhanced SQRT carry select adder
Bracci et al. Aleksandrov-Clark measures and semigroups of analytic functions in the unit disc
RU2007114540A (ru) Трехэлементное мажоритарное устройство резервирования
Lu et al. Design-for-testability and fault-tolerant techniques for FFT processors
Dill et al. Optimization of multi-channel BCH error decoding for common cases
Peng et al. Dynamic logic architecture based on piecewise-linear systems
Farazmand et al. Online multiple fault detection in reversible circuits

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees