Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sitronix Technology CorpfiledCriticalSitronix Technology Corp
Priority to TW93131734ApriorityCriticalpatent/TWI235474B/en
Application grantedgrantedCritical
Publication of TWI235474BpublicationCriticalpatent/TWI235474B/en
Publication of TW200614484ApublicationCriticalpatent/TW200614484A/en
A whole-chip electrostatic discharge (ESD) protection method is an ESD protection method for whole chip, which targets at providing a first metal layer and a second metal layer surrounding the periphery of a chip in a proper distance. A second conductor well opposite to a first conductor substrate of the chip is formed underneath the first metal layer. By means of the second conductor well surrounding the periphery of the chip in a proper distance, a capacitor in form of a large chamber is formed to attain the storage function of ESD, such that the whole-chip ESD protection capability is enhanced without changing original integrated circuit design and manufacturing process, thereof require no additional area to set up.