1235474 九、發明說明： 【發明所屬之技術領域】 本發明係有關一種全晶片的靜電放電保護方法，係一 種針對增加全晶片對ESD的防護能力，且不用變動原本積 體電路設計與其製程，也不需額外增加面積之方法。 【先前技術】 積體電路(1C)的晶片（大陸版:怒片）(chip)，隨著量產製 程的演進，元件的尺寸已縮減到深次微米（deep-submicron) 階段，以增進積體電路(1C)的性能及運算速度，以及降低 每顆晶片的製造成本。但隨著元件尺寸的縮減，卻出現一 些可靠度的問題，如靜電放電（Electrostatic Discharge ; ESD) 〇 因ESD產生的原因及其對積體電路放電的方式不 同，ESD目前被分類為下列四類:（1)人體放電模式 (Human_BodyModel，HBM) ; (2)機器放電模式（Machine Model，MM) ; (3)元件充電模式（Charged-Device Model， CDM)，（4)電場感應模式(Field-Induced Model，FIM)。 靜電的累積可能是正的或負的電荷，因此靜電放電測 試對同一 1C腳而言是具有正與負兩種極性。對每一 1/0 (Input or Output) Pin而言，HBM與MM靜電放電對1C的 放電，有下列四種ESD測試組合：（i)PS-mode:VSS腳接 地’正的ESD電壓出現在該〗/〇腳對vss腳放電，此時 VDD與其他腳皆浮接；（2)NS_m〇de:Vss腳接地，負的 電壓出現在該I/O腳對VSS腳放電，此時VDD與其他腳 1235474 皆浮接；（3)PD_mode:VDD腳接地，正的esd電壓出現在 該I/O腳對VDD腳放電，此時VSS與其他腳皆浮接； (4)ND-mode:VDD腳接地，負的ESD電壓出現在該I/C)腳 對VDD腳放電，此時VDD與其他腳浮接。1235474 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a full-chip electrostatic discharge protection method, which aims at increasing the full-chip protection ability against ESD without changing the original integrated circuit design and its manufacturing process. No additional method is required. [Prior technology] As the integrated circuit (1C) chip (mainland version: angry chip) (chip), with the evolution of mass production processes, the size of components has been reduced to the deep-submicron stage to increase the product The performance and operation speed of the body circuit (1C), and reducing the manufacturing cost of each chip. However, with the reduction in component size, some reliability issues have arisen, such as Electrostatic Discharge (ESD). ESD is currently classified into the following four categories due to the causes of ESD and the way in which it discharges integrated circuits. : (1) Human_BodyModel (HBM); (2) Machine Model (MM); (3) Charged-Device Model (CDM), (4) Electric Field Induction Mode (Field- Induced Model (FIM). The accumulation of static electricity may be positive or negative charge, so the electrostatic discharge test has both positive and negative polarities for the same 1C pin. For each 1/0 (Input or Output) Pin, there are four ESD test combinations for HBM and MM electrostatic discharge to 1C: (i) PS-mode: VSS pin is grounded. 'Positive ESD voltage appears at The 〖/ 〇 pin discharges the vss pin, and VDD and other pins are floating at this time; (2) NS_mode: The Vss pin is grounded, and a negative voltage appears when the I / O pin discharges the VSS pin. At this time, VDD and All other pins 1235474 are floating; (3) PD_mode: VDD pin is grounded, positive esd voltage appears on this I / O pin to discharge VDD pin, and VSS and other pins are floating at this time; (4) ND-mode: VDD The pin is grounded, and a negative ESD voltage appears at the I / C pin to discharge the VDD pin. At this time, VDD is floating to other pins.
習知用於對抗ESD之方法係合併大部份的半導體裝 置的輸入/輸出路徑上，設置一靜電放電防護電路(ESD protection circuits)於焊墊至其間，如美國專利us5,514,892 中，提出一種靜電放電保護裝置，係在具半導體井中一連 接線焊墊下形成一二極體。 一般產品被使用的外界環境所產生的靜電並未減 少’故CMOS積體電路因ESD而損傷的情形更形嚴重。 舉例來說，當一常用的輸出緩衝級(outputbuffer)元件的通 道寬度(channel width)固定在300微米(//m)，用2微米傳 統技術製造的NM0S元件可耐壓超過3千伏特（人體放電 模式）；用1微米製程加上LDD技術來製造的元件，其ESD 耐壓度不到2千伏特；用1微米製程加上LDD及silicide 技術來製造的元件，其ESD耐壓度僅約丨千伏特左右而 已。由此可知，就算元件的尺寸大小不變，因製程的先 進，元件的ESD防護能力亦大幅地滑落；就算把元件的 尺寸加大，其ESD耐壓度不見得成正比地被提昇，元件 尺寸增大相對地所佔的佈局面積也被增大，整個晶片大小 也會被增大，其對靜電放電的承受能力卻反而嚴重地下 降，許多深次微米CMOS積體電路產品都面臨了這個棘手 的問題。 1235474 【發明内容】 爰疋本毛明之主要目的係在不增加晶片面積 樣態下，增加全晶片對咖的防護能力，使該晶 焊墊σ零tPad)與輸出焊塾(〇u_pad)具有防護p， PD，及=四種模式的靜電放電能力。 本电明之另一目的係本發明之方法不用變動積體電 路設計與錢程，適用於任何晶片對ESD的加強防護設 計。 " 本發、月係種全晶片的靜電放電保護方法，針對晶片 臨其外周邊適當距離包括—環繞之第—金屬層與第二金 屬層處，於第一金屬層下方，形成一與該晶片的第—導體 犁基材相反之第二導體型井，俾藉該臨其外周邊適當距離 環繞之第二導體型井形成一大儲存槽之電容形態來達到 儲存靜電放電之功能。 如是’因為該井的形成係在晶片未使用到的臨周邊内 緣處下方’所以對現在斤斤計較的晶片面積完成沒有影 響。 ’ 【實施方式】 兹有關本發明之詳細内容及技術說明，現配合圖式說 明如下： 請同時參閱「第1、2、3圖」所示，係本發明之佈局 與實施樣態之截面示意圖。如圖所示：本發明係針對晶片 10臨其外周邊適當距離已存在環繞接高電壓(VDD)之第一 金屬層21與位於第一金屬層21上方接地（gnd)之第二 1235474 金屬層22，及其該第一金屬層21耦合之焊墊20，其特徵 在於本發明該第一金屬層21分開為相臨之第一金屬層一 21a與第一金屬層二21b (如「第2、3圖」所示），及在 第一金屬層一 21a下方，形成一與該晶片10的第一導體型 基材11 (例如：P-substrate)相反之第二導體型井30 (例 如：N-well)，且該焊墊20係透過該第一金屬層一 21a下 方之一接觸栓211與第二導體型井30連接。 所以，該第一金屬層二21b透過接觸栓221、212分 別與第二金屬層22及第一導體型基材11連接，形成一串 聯樣態，據此達到共接地之目地，也藉此連接方式，可將 與串聯路徑上之耦合靜電帶走。 而該臨其外周邊適當距離環繞之第二導體型井30就 可形成一大儲存槽之電容形態來達到儲存靜電放電之效 果。該第二導體型井30表面上係設有一平行相臨或單邊 之氧化層111，且形成一井樣態於該氧化層111下方（其 氧化層111之剖面可為兩邊如「第2圖」，或單邊如「第 3圖」之結構），且該氧化層111上設有一第一導體型多 晶矽12,而該第一金屬層二21b透過一接觸栓213與其連 接。而前述中第一金屬層二21b透過接觸栓221與第二金 屬層22，現又透過接觸栓213與第一導體型多晶矽12連 接，形成一串聯樣態，據此達到共接地之目地，也藉此連 接方式，可將與串聯路徑上之耦合靜電帶走。. 該第二導體型井30將因為透過該第一金屬層一 21a 下方之一接觸栓211與其連接，因為第一金屬層一 21a為 1235474 態:而，所以第一導體型井30將為高電麼（VDD)狀 為-你φ、導體型多晶梦12由前述已知其接地（GND) 3〇間將二壓’所以第一導體型多晶矽12與第二導體型井 1將可形成一大的電容儲存槽。 屬層的’該第—導體型多晶砍12 (低㈣）與第一金 層】2 &(高電壓）也形成一電容形態，及該第二金屬 電容开電壓）與第一金屬層—2U (高電壓）也形成一 高電‘念二此三電容形態對全晶片而言將會形成一並聯之 將&形態，且可由前述之串連共接地之連接方式， 爭聯路徑上之ESD產生之靜電電壓帶走。 金丄本Λ明之第二導體型…^ «目同’也就是說該第二導體型井3。與第一金屬 目同可以是環繞連接，也可依晶片内積體電路設計 太:二，第一金屬層21之分段來分段，可完全隨原 本之積體電路走線來設計。 本發明之功效，以一 ⑽ 〇υϋυ//ιη 1500#m 的 u：D 驅動 晶片（dnverclnp)為例，該第二導體型井3〇之 為2〇em，則將可增加約25〇K//m2之電容面積，二這樣 大面積係由第二導體型井3()與第—導體 電壓）、第一金屬層一 2la(高電壓）、 曰曰夕12(低 弟—金屬择22 (紙The conventional method for combating ESD is to incorporate most of the semiconductor device's input / output paths by placing an ESD protection circuit between the pads. For example, in US Pat. No. 5,514,892, a method is proposed. The electrostatic discharge protection device is a diode formed under a connection pad in a semiconductor well. The static electricity generated by the external environment in which a product is used has not been reduced ', so the situation of CMOS integrated circuit damage due to ESD is more serious. For example, when the channel width of a commonly used output buffer element is fixed at 300 micrometers (// m), the NMOS device manufactured with the traditional technology of 2 micrometers can withstand voltages exceeding 3 kV (human body). (Discharge mode); components manufactured with 1 micron process plus LDD technology have an ESD withstand voltage of less than 2 kV; components manufactured with 1 micron process plus LDD and silicide technology have an ESD withstand voltage of only about丨 It's only about one thousand volts. It can be seen that even if the size of the component remains the same, due to the advanced process, the ESD protection capability of the component also greatly falls; even if the size of the component is increased, its ESD withstand voltage is not necessarily improved in proportion to the component size. The layout area occupied by the increase is also increased, and the size of the entire wafer will be increased. However, its ability to withstand electrostatic discharge has been severely reduced. Many deep sub-micron CMOS integrated circuit products are facing this difficulty. The problem. 1235474 [Content of the invention] The main purpose of this book is to increase the protection capability of the whole chip to the coffee without increasing the area of the wafer, so that the crystal pad σ zero tPad) and the output pad (〇u_pad) have protection. Electrostatic discharge capability of p, PD, and = four modes. Another object of the present invention is that the method of the present invention does not need to change the integrated circuit design and money schedule, and is applicable to any chip's enhanced ESD protection design. " The present invention is a full-chip electrostatic discharge protection method. For the appropriate distance between the wafer and its outer periphery, it includes-surrounding the first metal layer and the second metal layer, under the first metal layer. The second conductor-type well of the first conductor-plow of the wafer is opposite to the substrate, and the second conductor-type well surrounded by a suitable distance around the outer periphery of the chip forms a large storage capacitor to achieve the function of storing electrostatic discharge. If it is 'because the formation of the well is below the inner edge of the peripheral edge where the wafer is not used', it has no effect on the completion of the wafer area which is now being calculated. '[Embodiment] The detailed content and technical description of the present invention are described below in conjunction with the drawings: Please refer to "Figures 1, 2, and 3" at the same time, which is a schematic sectional view of the layout and implementation of the present invention. . As shown in the figure, the present invention is directed to the existence of a first metal layer 21 surrounding the high voltage (VDD) and a second 1235474 metal layer grounded (gnd) above the first metal layer 21 at an appropriate distance from the wafer 10 near its outer periphery. 22, and the bonding pad 20 coupled to the first metal layer 21, which is characterized in that the first metal layer 21 of the present invention is separated into adjacent first metal layers 21a and 21b (such as "the second "," As shown in Fig. 3), and under the first metal layer 21a, a second conductor-type well 30 is formed opposite to the first conductor-type substrate 11 (for example, P-substrate) of the wafer 10 (for example: N-well), and the bonding pad 20 is connected to the second conductive well 30 through a contact pin 211 under the first metal layer 21a. Therefore, the first metal layer 21b is connected to the second metal layer 22 and the first conductive substrate 11 through the contact plugs 221 and 212, respectively, to form a series state, thereby achieving the purpose of common grounding, and also connecting by this. Method, it can take away the coupling static electricity on the series path. And the second conductor-type well 30 surrounded by a proper distance around its outer periphery can form a capacitor shape of a large storage tank to achieve the effect of storing electrostatic discharge. On the surface of the second conductor-type well 30, an oxide layer 111 that is adjacent to or unilateral is provided, and a well-like state is formed below the oxide layer 111 (the cross-section of the oxide layer 111 may be two sides as shown in FIG. 2 Or a single-sided structure such as "Figure 3"), and a first conductive polycrystalline silicon 12 is provided on the oxide layer 111, and the first metal layer 21b is connected to it through a contact plug 213. In the foregoing, the first metal layer 21b is connected to the second metal layer 22 through the contact plug 221, and is now connected to the first conductive polycrystalline silicon 12 through the contact plug 213 to form a series state, thereby achieving the purpose of common grounding. With this connection method, the electrostatic coupling with the series path can be taken away. The second conductive well 30 will be connected to it through one of the contact pins 211 below the first metal layer 21a, because the first metal layer 21a is in the 1235474 state: and the first conductive well 30 will be high. The power (VDD) shape is-you φ, the conductor type polycrystalline dream 12 will be two voltages between 30 and GND, so the first conductor type polycrystalline silicon 12 and the second conductor type well 1 will be formed. A large capacitor storage tank. The metal layer of the first-conductor type polycrystalline cut 12 (low voltage) and the first gold layer 2 & (high voltage) also forms a capacitor form, and the second metal capacitor opens the voltage) and the first metal layer —2U (high voltage) also forms a high-powered capacitor. The three-capacitor configuration will form a parallel connection & configuration for the whole chip, and can be connected in series and grounded as described above. The electrostatic voltage generated by ESD is taken away. The second conductor type of Jin Biben ^ Ming ... ^ «me same 'means that the second conductor type well 3. It can be connected around the same as the first metal, or it can be designed according to the integrated circuit in the chip too. Second, the segmentation of the first metal layer 21 can be segmented, which can be completely designed with the original integrated circuit wiring. The effect of the present invention is based on a u: D driving chip (dnverclnp) of ϋυυυ // ιη 1500 # m as an example. If the second conductive well 30 is 20em, it will increase about 25k. // m2 capacitance area, two such large areas are formed by the second conductor well 3 () and the first conductor voltage), the first metal layer 2la (high voltage), and the day 12 (low brother-metal selection 22) (paper
電壓）間所產生，約可増加131pF之電容 ς DVoltage), which can add about 131pF capacitor ς D
所產生的電量。 仔里來儲存ESD 經由前述可知道，本發明之方法係則了 到的臨周邊内緣處下方，所以不當链冰 斤不而額外的晶片面積來設置 1235474 在不增加晶片面積大小的樣態下’增加全晶片對咖 護能力，使該晶片的輸入焊墊(Inputpad)與輸出焊墊 (Output pad)具有防護Ps，NS，pD，及Ν〇四種模 電放電能力，且該第二導體型井3G、氧化層lu與第 體型多晶们2都是在—般積體電路的製程中以包括的， 發明方法不用變動積體電路料與其製程，適用於 何曰曰片對ESD的加強防護設計。 本發僅為本發明之較佳實施例而已’並非用來限定 等變化~^範圍。即凡依本發明申請專利範圍所做的均 >哪，皆為本發明專利範圍所涵蓋。 【圖式簡單說明】 第1圖，係本笋明^ > 第2圖，# 之佈局示意圖。 ^ λ ^ ^本發明之實施樣態之截面示意圖。 【主要元::：明之另-實施樣態之截面示意圖。 u丨卞付詭說明飞 i〇 :晶片 11:第—導體型基材 ui :氧化層 12 20 第一導體 焊墊 型多晶矽 21 :第一金屬層 21a :第—金屬層 2lb :第一金屬層 22 ·第二金屬層 1235474 211、221、212 :接觸栓The amount of electricity generated. It can be known from the above that the ESD is stored in the method of the present invention, which is located near the inner edge of the periphery. Therefore, if the chain ice weight is improperly set, the extra chip area is set to 1235474. 'Increase the chip-to-coffee protection capability of the chip, so that the input pad and output pad of the chip can protect the four types of electrical discharge of Ps, NS, pD, and NO, and the second conductor The well 3G, the oxide layer lu, and the body type polycrystalline silicon 2 are all included in the process of the general integrated circuit. The inventive method does not need to change the integrated circuit material and its process, which is suitable for the enhancement of ESD by He Yue film. Protective design. The present invention is only a preferred embodiment of the present invention, and is not intended to limit the scope of such changes. That is, everything that is done in accordance with the scope of patent application for the present invention is covered by the scope of patent for the invention. [Simplified description of the drawing] Fig. 1 is a schematic diagram of the present arrangement ^ > Fig. 2 is a schematic layout of #. ^ λ ^ ^ A schematic sectional view of an embodiment of the present invention. [Primary Elements ::: Another Ming-Sectional schematic diagram of implementation. u 丨 Explanation of flying i〇: Wafer 11: Conductive substrate ui: Oxide layer 12 20 First conductive pad type polycrystalline silicon 21: First metal layer 21a: First metal layer 2lb: First metal layer 22Second metal layer 1235474 211, 221, 212: contact plug