TW200541121A - P-type group Ⅲ nitride semiconductor and production method thereof - Google Patents
P-type group Ⅲ nitride semiconductor and production method thereof Download PDFInfo
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,200541121 九、發明說明: 【發明所屬之技術區域】 本發明係關於III族氮化物p型半導體之製法及使用其 所製造之III族氮化物半導體發光元件。尤其是關於可以高 良率獲得低驅動電壓(Vf)、及足夠高的逆電壓(VO之 發光元件之III族氮化物P型半導體之製法。 【先前技術】, 200541121 IX. Description of the invention: [Technical area to which the invention belongs] The present invention relates to a method for manufacturing a group III nitride p-type semiconductor and a group III nitride semiconductor light-emitting device manufactured using the same. In particular, it is related to a method for manufacturing a group III nitride P-type semiconductor of a light-emitting element that can obtain a low driving voltage (Vf) with a high yield and a sufficiently high reverse voltage (VO). [Prior Art]
近年來用以發出短波長光的發光元件用半導體材料,有 一種氮化物半導體材料受到世人的注目。一般而言,氮化 物半導體係以藍寶石單結晶及各種氧化物結晶及III-V族 化合物半導體單結晶等作爲基板,而在其上以金屬有機化 學氣相沉積法(MOCVD法)或分子束磊晶生長法(MBE 法)或以氫化物氣相磊晶生長法(HVPE法)等實施積層 〇 在III族氮化物半導體方面,已有一段長期間不易製造 出具有足夠的載子濃度之p型半導體。然而,根據揭示一 種對經摻雜Mg之氮化鎵(GaN )照射低速度電子射線之方 法(參閱日本發明專利特開平第2-257679號公報),或一 種在不含氫之氣氛中將經同樣地摻雜Mg之氮化鎵加以熱 處理之方法(參閱日本發明專利特開平第5- 1 83 1 89號公報 )等即得知仍有可能製得具有足夠的載子濃度之p型半導 體。何以能製得足夠的載子濃度之機構,其係被認爲藉由 上述方法將以氫所鈍化之半導體中p型摻質予以脫氫即可 使其活性化之緣故。實際上,經施加活性化退火處理之摻 -5- 200541121In recent years, a semiconductor material for a light-emitting element for emitting short-wavelength light has attracted worldwide attention as a nitride semiconductor material. In general, nitride semiconductors use sapphire single crystals, various oxide crystals, and III-V compound semiconductor single crystals as substrates, and metal organic chemical vapor deposition (MOCVD) or molecular beam leaching is used thereon. Crystal growth method (MBE method) or hydride vapor phase epitaxial growth method (HVPE method) is used to perform lamination. In group III nitride semiconductors, it has been difficult to produce p-types with sufficient carrier concentration for a long period of time. semiconductor. However, according to a method of irradiating Mg-doped gallium nitride (GaN) with a low-velocity electron ray (see Japanese Patent Application Laid-Open No. 2-257679), or a method in which Similarly, a method of heat-treating gallium nitride doped with Mg (see Japanese Patent Application Laid-Open No. 5- 1 83 1 89), etc. shows that it is still possible to produce a p-type semiconductor having a sufficient carrier concentration. It is considered that a mechanism capable of obtaining a sufficient carrier concentration can be activated by dehydrogenating a p-type dopant in a semiconductor passivated with hydrogen by the above method. In fact, doping after activation annealing is applied -5- 200541121
Mg的氮化鎵系半導體,其Η之濃度係Mg濃度之約1/10。 生長結晶性佳的ΠΙ族氮化物半導體之方法,一般係使 用金屬有機化學氣相沉積法(MOCVD法)。然而在 MOCVD法中用以進行結晶生長的生長裝置內,卻以高濃度 下存在著用作爲將原料化合物載運至基板上所需之載氣的 氫氣,或因用作爲V族原料的氨(NH3 )發生分解所產生 之氫分子或自由基狀或原子狀之氫。於是該等氫將在III族 氮化物半導體之結晶層的生長中被取入於結晶內,並在施 加從結晶層生長溫度起之冷卻時,將與經摻雜於結晶的p 型摻質產生鍵結。藉由如此方式爲氫所鈍化之p型摻質是 已爲非活性,因此無法產生電洞。然而,只要對該試料照 射電子射線或施加熱處理時,即可切斷結晶內之p型摻質 與氫之鍵結,從結晶內逐出氫以使p型摻質活性化。 上述兩種方法中照射電子射線之方法,由於一次所能施 加處理之區域有限,爲處理全面積則需耗時間,以致無法 應用在工業上。 在另一方面,已知在具有藉由施加熱處理之方法所製造 的P型III族氮化物半導體的發光元件結構之晶圓中,在所 形成電極所測得之電氣特性中對pn接合朝逆方向流通規定 値電流時之電壓(Vr )爲低的晶片,會以某一比率混雜在 一起之現象。Vr爲低係意謂正有電流對pn接合漏洩,因 此對製品而言是不佳。換言之,只要取除該晶片即可使良 率大幅度地降低。一般而言,已知若因熱處理而會從ΠΙ族 氮化物半導體脫氫時,則氮也會同時脫離,以致結晶性將 20Q541121 降低,此現象有可能爲導致Vr降低之原因。 另外,已揭示一種在冷卻經摻雜P型雜質的氮化鎵系化 合物半導體時,藉由在400°C以上之溫度由含氨氣之氣氛 切換爲氫氣或氮氣之氣氛’以使經摻雜P型雜質之層予以 低電阻化之技術(參閲日本發明專利特開平第8- 1 1 5880號 公報)。並且在該文獻則作爲實施例而揭示一種在結束生 長摻Mg的層後,直至600°C爲止以NH3與H2之混合氣體 實施冷卻,且在600°C停止NH3之供應而切換成僅爲氫之 氣氛的實例。 然而,根據本發明之發明人等實驗結果,若直至600°C 爲止使NH3流通以實施冷卻時,卻無法獲得使元件降低驅 動電壓之功效。特別是當正極材料採用Pt等之金屬時,則 得知在施加接合之前是已充分降低的驅動電壓,竟會因接 合時所施加約300 °C之熱而上升。 在另一方面,也有報告指出經生長III族氮化物半導體 後在冷卻至室溫時,若將氣氛氣體取代成H2氣及NH3氣以 外之惰性氣體以進行冷卻時,即可獲得足夠的載子濃度( 參閱日本發明專利特開平第8- 125222號公報)。其在實施 例中則揭示藉由真空狀態而實施氮之取代以取代成氮氣或 惰性氣體以製得p型半導體。 然而,即使將氣氛氣體取代成H2氣、NH3氣以外之惰性 氣體以進行冷卻,也無法一槪而在高良率下獲得低驅動電 壓之晶片。亦即,只使加以控制該文獻所規定之條件,也 不可能在高良率下獲得優良再現性及優良特性之晶片。而 200541121 且,也知道在正極材料使用Pt等之情況時,則將產生驅動 電壓因在接合時所歷經之熱而上升。 此外,也已公開一種在經生長氮化物半導體後,立即在 生長溫度之1,1 〇〇°c予以取代成惰性氣體之技術(參閲曰本 發明專利特開平第9- 1 29929號公報)。並且,若根據此等 方法時,從經取代成惰性氣體後起至降溫成室溫則必須歷 時2〜3小時。 然而,根·據此等經結束生長後立即進行對惰性氣體的取 代之方法時,根據吾等之實驗則查明所製得之晶片的Vr將 降低。並且,以歷經長時間來降低溫度,也會導致Vr降低 〇 最後,已有提案揭示一種將在700°C以上之生長溫度所 生長之結晶在700°C以下之冷卻,以在氫以外之載氣氣氛 下實行之低電阻p型氮化鎵系化合物半導體之生長方法( 參閲日本發明專利特開平第9- 199758號公報)。在此文獻 之實施例,則在經結束在l,〇3(TC的p型氮化鎵系化合物半 導體之生長後,在700°C將由氫與氨所形成之氣氛予以取 代成氮。 該方法吾等也已加以檢討,結果即使在氫以外的氣體氣 氛中實施700°C以下之冷卻,也無法在高良率下獲得低驅 動電壓之晶片。換言之,只是加以控制以該文獻所規定之 ί摩件’仍然無法在高良率下獲得優良再現性及優良特性之 晶片。而且,將產生因正極材料採用Pt等時,在接合時所 施加的熱而導致驅動電壓上升。 ^200541121 總結言之,若根據日本發明專利特開平第5- 1 83 1 89號公 報及特開平第9- 1 29929號公報之方法時,則將變成Vr爲 低之漏拽性之晶片’在另一^方面’右根據日本發明專利特 開平第8- 1 1 5880號公報、特開平第8“ 25222號公報及特 開平第9- 1 99758號公報之方法時,則驅動電壓將增高。尤 其是將產生因正極材料採用Pt等時,在接合時所施加的熱 而導致驅動電壓上升。 如上所述,一種在製造III族氮化物半導體元件時,可 使元件特性與良率同時存在且完全無問題之含有p型摻質 之層之形成方法並未有提案。 而且,在該等先前例中則必須使含有P型摻質之層予以 低電阻化,因此在任一種技術也提及必須提供低電阻之p 型半導體層之必要性。 【發明內容】 本發明係爲解決上述先前技術之問題而達成,其目的係 提供一種可在高良率下獲得低驅動電壓(Vf)、及足夠高 的逆電壓(Vr)之發光元件之III族氮化物p型半導體之 製法。 本發明係提供如下述之發明。 (1 ) 一種III族氮化物p型半導體之製法,其特徵爲經 使含有P型摻質之III族氮化物半導體生長後在降 溫時,以與生長結束時之溫度相同的溫度’從生 長剛結束之後起載氣則使用惰性氣體,且使氮源 之流量減少,並在其後之降溫過程途中停止供應 ,200541121 氮源。 (2) 如申請專利範圍第1項之製法,其中生長結束時 之溫度爲90(TC以上。 (3 ) 如申請專利範圍第1或2項之製法,其中氮源爲 氣氣。 (4) 如申請專利範圍第1至3項中任一項之製法,其 中在生長半導體時之載氣係含有氫氣。For a Mg gallium nitride-based semiconductor, the concentration of rhenium is about 1/10 of the Mg concentration. A method for growing a group III nitride semiconductor with good crystallinity is generally a metal organic chemical vapor deposition method (MOCVD method). However, in the growth device used for crystal growth in the MOCVD method, hydrogen at a high concentration exists as a carrier gas required to carry a raw material compound onto a substrate, or ammonia (NH3) is used as a group V raw material. ) Hydrogen molecules or free radical or atomic hydrogen produced by decomposition. The hydrogen will then be taken into the crystal during the growth of the crystalline layer of the group III nitride semiconductor, and when cooling from the crystalline layer growth temperature is applied, it will be generated with the p-type dopant doped in the crystal. Bonding. In this way, the p-type dopant that is passivated by hydrogen is already inactive and therefore cannot generate holes. However, as long as the sample is irradiated with electron rays or subjected to heat treatment, the bond between the p-type dopant and hydrogen in the crystal can be cut off, and hydrogen can be expelled from the crystal to activate the p-type dopant. Of the two methods described above, the method of irradiating electron rays has a limited area that can be treated at one time, and it takes time to process the entire area, which makes it impossible to apply it to industry. On the other hand, it is known that in a wafer having a light-emitting element structure of a P-type III nitride semiconductor manufactured by a method of applying heat treatment, the pn junction is reversed in the electrical characteristics measured by the formed electrode. A chip with a low voltage (Vr) when a predetermined 値 current flows in the direction will be mixed at a certain ratio. A low Vr means that a current is leaking to the pn junction, so it is not good for the product. In other words, if the wafer is removed, the yield can be greatly reduced. In general, it is known that if hydrogen is dehydrogenated from a group III nitride semiconductor due to heat treatment, nitrogen will also be detached at the same time, so that the crystallinity will be reduced to 20Q541121. This phenomenon may cause the reduction of Vr. In addition, when a gallium nitride-based compound semiconductor doped with a P-type impurity is cooled, it is disclosed that the doped doped by switching from an atmosphere containing ammonia to an atmosphere of hydrogen or nitrogen at a temperature of 400 ° C or higher. A technique for reducing the resistance of the P-type impurity layer (see Japanese Patent Application Laid-Open No. 8-1 15880). In this document, as an example, it is disclosed that after the growth of the Mg-doped layer is completed, the mixture is cooled with a mixture of NH3 and H2 until 600 ° C, and the supply of NH3 is stopped at 600 ° C to switch to only hydrogen. An example of the atmosphere. However, according to the experimental results of the inventors of the present invention, if NH3 is circulated for cooling until 600 ° C, the effect of reducing the driving voltage of the device cannot be obtained. In particular, when a metal such as Pt is used as the positive electrode material, it is known that the driving voltage that has been sufficiently reduced before the bonding is applied may actually increase due to the heat of approximately 300 ° C applied during the bonding. On the other hand, there are reports that when the III-nitride semiconductor is grown and cooled to room temperature, if the atmosphere gas is replaced with an inert gas other than H2 gas and NH3 gas for cooling, sufficient carriers can be obtained Concentration (see Japanese Patent Application Laid-Open No. 8-125222). In the examples, it is disclosed that the substitution of nitrogen is performed in a vacuum state to replace with nitrogen or an inert gas to produce a p-type semiconductor. However, even if the atmosphere gas is replaced with an inert gas other than H2 gas or NH3 gas for cooling, it is not possible to obtain a wafer with a low driving voltage at a high yield at a time. That is, it is impossible to obtain a wafer with excellent reproducibility and excellent characteristics at high yields only by controlling the conditions specified in this document. 200541121 It is also known that when Pt or the like is used as the positive electrode material, the driving voltage will increase due to the heat experienced during bonding. In addition, a technology has also been disclosed in which a nitride semiconductor is grown and then replaced with an inert gas at a growth temperature of 1,100 ° C (see Japanese Patent Application Laid-Open No. 9-1 29929). . In addition, according to these methods, it takes 2 to 3 hours after the temperature is reduced to room temperature after being replaced with an inert gas. However, when the method of substituting the inert gas immediately after the growth is completed, it has been found from our experiments that the Vr of the wafer produced will be reduced. In addition, lowering the temperature over a long period of time will also cause Vr to decrease. Finally, there have been proposals to reveal a method for cooling the crystals grown at a growth temperature above 700 ° C below 700 ° C, so that A method for growing a low-resistance p-type gallium nitride-based compound semiconductor in a gas atmosphere (see Japanese Patent Application Laid-Open No. 9-199758). In the example of this document, after the growth of the p-type gallium nitride-based compound semiconductor at 1.03 ° C, the atmosphere formed by hydrogen and ammonia was replaced with nitrogen at 700 ° C. This method We have also reviewed and found that even if cooling below 700 ° C is performed in a gas atmosphere other than hydrogen, it is not possible to obtain a wafer with a low driving voltage at a high yield. In other words, it is only controlled to meet the requirements specified in this document. It is still impossible to obtain a wafer with excellent reproducibility and excellent characteristics at a high yield. In addition, when Pt is used as the positive electrode material, the driving voltage is increased during bonding. ^ 200541121 In summary, if According to the methods of Japanese Patent Application Laid-Open No. 5- 1 83 1 89 and Japanese Patent Application Laid-Open No. 9-1 29929, the wafer with low Vr of low Vr will be "on the other side" When the methods of Japanese Patent Application Laid-open No. 8-1 1880, No. 8 "25222, and No. 9-1 99758, the driving voltage will be increased. In particular, the positive electrode material will be generated. When Pt is used, the driving voltage rises due to the heat applied during bonding. As described above, when manufacturing a III-nitride semiconductor device, the device characteristics and yield can be coexisted without any problem at all. There is no proposal for the formation method of the doped layer. Moreover, in these previous examples, it is necessary to reduce the resistance of the layer containing the P-type dopant, so it is also mentioned in any technology that a p-type semiconductor having a low resistance must be provided [Summary of the invention] The present invention is achieved in order to solve the above-mentioned problems of the prior art, and its object is to provide a low driving voltage (Vf) and a sufficiently high reverse voltage (Vr) that can be obtained at a high yield. A method for producing a group III nitride p-type semiconductor of a light-emitting device. The present invention provides the following inventions. (1) A method for producing a group III nitride p-type semiconductor, which is characterized in that a III-type nitrogen containing a P-type dopant is included. After the growth of the compound semiconductor, the temperature is the same as the temperature at the end of the growth at the same temperature as that at the end of the growth. From the beginning of the growth, the inert gas is used as the carrier gas, and the flow rate of the nitrogen source is reduced. The supply of nitrogen was stopped during the subsequent cooling process, 200541121. (2) If the manufacturing method of the scope of the patent application is applied, the temperature at the end of the growth is 90 (TC or more.) (3) If the scope of the patent application is 1 or 2 The manufacturing method, wherein the nitrogen source is a gas. (4) The manufacturing method according to any one of claims 1 to 3, wherein the carrier gas used for growing the semiconductor contains hydrogen.
(5 ) 如申請專利範圍第1至4項中任一項之製法,其中減 少後之氮源之流量爲全氣體體積中之0.001〜10 %。 (6) 如申請專利範圍第1至5項中任一項之製法,其 中停止供應氮源之溫度爲700〜95 0°C。 (7 ) —種ΙΠ族氮化物P型半導體,其特徵爲含有多於 p型摻質濃度之1 /5,且少於p型摻質濃度之量的 氫原子。 (8 ) 一種III族氮化物P型半導體,其特徵爲電阻率爲 20Ω cm 〜10,000Ω cm 〇 (9 ) 一種ΙΠ族氮化物半導體發光元件,係在基板上設 置由III族氮化物半導體所構成之η型層、發光層 和Ρ型層,且負極和正極係分別設置在η型層和 ρ型層上,其特徵爲Ρ型層之製法爲如申請專利 範圍第1至6項中任一項之製法。 (10) —種III族氮化物半導體發光元件,係在基板上設 置由III族氮化物半導體所構成之η型層、發光層 和ρ型層,且負極和正極係分別設置在η型層和 •10- 200541121 P型層上’其特徵爲p型層爲如上所述第7或8 項之III族氮化物p型半導體。 (11) 如申請專利範圍第9或1 〇項之發光元件,其中正 極係將選自Pd、Pt、Rh、Os、Ir及Ru之白金族 金屬用正極材料。 (12) 如申請專利範圍第9至1 1項中任一項之發光元件 ,其中發光元件爲覆晶晶片型。(5) If the manufacturing method of any one of items 1 to 4 of the scope of patent application, wherein the flow rate of the reduced nitrogen source is 0.001 to 10% of the total gas volume. (6) If the manufacturing method of any one of items 1 to 5 of the scope of patent application, the temperature at which the supply of nitrogen is stopped is 700 to 95 ° C. (7) A group I-III nitride P-type semiconductor, which is characterized by containing more than one-fifth of the hydrogen concentration of the p-type dopant and less than the concentration of the p-type dopant. (8) A group III nitride P-type semiconductor, which has a resistivity of 20 Ω cm to 10,000 Ω cm. 〇 (9) A group III nitride semiconductor light-emitting device, which is provided on a substrate and is composed of a group III nitride semiconductor. The n-type layer, the light-emitting layer, and the p-type layer, and the negative electrode and the positive electrode are respectively disposed on the n-type layer and the p-type layer. Item system method. (10) A type III nitride semiconductor light-emitting device, wherein an n-type layer, a light-emitting layer, and a p-type layer composed of a group III nitride semiconductor are provided on a substrate, and a negative electrode and a positive electrode are provided on the n-type layer and • 10-200541121 On a P-type layer 'characterized in that the p-type layer is a group III nitride p-type semiconductor of item 7 or 8 as described above. (11) If the light-emitting element of item 9 or 10 of the patent application scope, wherein the positive electrode is a platinum group metal positive electrode material selected from Pd, Pt, Rh, Os, Ir, and Ru. (12) The light-emitting element according to any one of claims 9 to 11 in the scope of patent application, wherein the light-emitting element is a flip-chip wafer type.
(1 3 ) 如申§靑專利$12圍第9至1 1項中任一^項之發光元件 爲面朝上組裝型。 若根據本發明,則可獲得可用作爲半導體元件而使用的 層級之具有足夠的特性之p型III族氮化物半導體。並且, 使用該III族氮化物p型半導體,即可在高良率下製造不致 於產生因熱的驅動電壓上升,且具有高Vr之III族氮化物 半導體發光元件。 【實施方式】 〔本發明之最佳實施方式〕 可適用於本發明之製造方法的III族氮化物p型半導體 之III族氮化物半導體,係除GaN之外也包括:InN、A1N 等之二元系混晶,InGaN、AlGaN等之三元系混晶,及 InAlGaN等之四元系混晶等之所有III族氮化物半導體。但 是在本發明中,則更進一步包括氮以外之V族元素,亦即 GaPN、GaNAs等之三元系混晶,或對其再含有In或A1之 InGaPN、InGaAsN、AlGaPN、AlGaAsN 等之四元系混晶, 並且進一步含有In、A1之兩者的Alin GaPN、Alin GaAsN、 -11 - 20P541121 « 參 或含有P與As之兩者的AlGaPAsN、InGaPAsN等之五元 系混晶,並且含有所有元素的AlInGaPAsN之六元系混晶 ,也包括在ΙΠ族氮化物半導體中。 本發明係在上述中,特別適合使用於製造比較容易且又 無分解之危險性的GaN、InN、A1N等之二元系混晶, InGaN、AlGaN等之三元系混晶,InAlGaN等之四元系混晶 等之作爲V族而僅含有N的III族氮化物半導體。若以通 式AlxInyGabX_yN (Ogx + y^l)來表示時,X較佳爲在〇 ® 〜0.5之範圍,且y較佳爲在0〜0.1之範圍。 另外,可使用於本發明之P型摻質,係包括已揭示所指 出或預估的摻雜於ΙΠ族氮化物半導體即會顯現出p型導電 性的Mg、Ca、Zn、Cd、Hg等。此等之中,藉由熱處理的 活性化率爲高的Mg,係特別適合用作爲p型摻質。摻質之 使用量較佳爲1 X 1〇18〜1 X 1〇21 cnT3。若爲少於1 X 1018 cnT3時,則將導致發光強度降低。相反地,若多於lx 1 021 cm_3時,則將引起結晶性惡化,因此不佳,且更佳爲 • 1 X 1 019 〜1 X 1 02。cm·3。 根據本發明所揭示之方法所製造之P型半導體層’在其 結晶中也可含有氫原子。爲製造逆向之電壓Vr爲高之元件 ,有時寧以在結晶中含有氫原子爲較佳之情況。包含在結 晶中的氫原子之量,較佳爲少於所摻雜的P型摻質之量。 氫原子之含量,在與P型摻質之含量爲相同之情況’或多 於P型摻質之含量的情況時,則不易獲得P型電極之電氣 接觸,因此較佳爲比其爲少者。氫原子之含量更佳爲P型 -12- 200541121 X ** 摻質之9/10以下,且特佳爲7/8以下。然而,若氫原子之 含量爲P型摻質之1/5以下時,則將同時產生氮之脫離, 因此較佳爲多於1/5,更佳爲1/3以上,若爲1/2以上則更 理想。另外’ P型半導體層之鎂及氫之原子濃度係以一般 的 SIMS ( 一 次離子質譜儀:Secondary Ion Mass Spectroscopy)加以定量。 另外,P型層係不會因在結晶中含有氫而成爲低電阻, 但是其並不會對元件特性構成問題。在使用III族氮化物半 ® 導體之元件’由於P型層多半是形成比其他半導體之情況 較薄,因此P型層本身之電阻並不致於對元件之驅動電壓 Vf造成太大的影響。p型層之電阻率爲高,爲保持高Vr是 較爲理想。 P型層之電阻率較佳爲約20Ω cm〜10,000Ω cm。若高於 10,000 Ωοιη時,則將導致發光強度降低,若低於20Qcm 時,則有可能會導致Vr降低,而更佳爲50Ω cm〜2,000 Ω cm,且特佳爲lOOQcm〜l,000 Qcm。另外,電阻率係以 一般的 TLM (遙測:Transfer Length Measurement)法加 以測定。 適用於本發明之III族氮化物p型半導體之生長方法, 並無特殊的限定,可使用MOCVD (金屬有機化學氣相生長 法)、HVPE (氫化氣相磊晶生長法)、MBE (分子束磊晶 生長法)等之習知的可供生長III族氮化物半導體之所有方 法。較佳的生長方法,若從膜厚控制性、量產性的觀點來 考慮則爲MOCVD法。 -13- 200541121€ , 在MOCVD法,載氣係使用氫氣(h2)或氮氣(n2), 屬III族原料之Ga源係使用三甲基鎵(TMG )或三乙基鎵 (TEG ) ,A1源係使用三甲基鋁(TMA )或三乙基錦( TEA) ’ In源係使用二甲基姻(TMI)或二乙基姻(TEI) ’氮源係使用氨氣(NH3)或聯氨(N2H4)等。另外在p 型摻質中,Mg原料係使用例如雙環戊二烯基鎂(Cp2 Mg) 或雙乙基環戊一稀基錢((EtCp)2 Mg) ,Zn原料係使用二 甲基鋅(Zn (CH3)2)。 若載氣係含有Η2,和/或氮源使用N Η3時,本發明之功 效就大。 爲獲得優良的結晶性與接觸電阻,生長溫度較佳爲1,〇〇〇 °C以上之溫度,且更佳爲l,〇50°C以上、1,250°C以下。 經生長含有p型摻質之III族氮化物半導體後,降溫至 室溫,然後從生長裝置取出半導體積層物之順序,若在生 長時載氣含有氫氣時,則必須在剛結束生長之後,在以與 生長溫度相同的溫度下使載氣切換爲未含氫氣之惰性氣體 。若繼續使氫氣流通作爲切換所需時間落後所允許之約1 分鐘以上時,則驅動電壓無法充分地降低。用以取代載氣 之惰性氣體,較佳爲氮氣,但是也可使用氬氣或氦氣等及 其混合物。 另外,與切換載氣同時降低氮源之流量是重要。在生長 時之氮源供應量通常爲全氣體量之體積之20 %〜70 %,但 是經降低氮源後之氮源量,較佳爲全氣體量之體積之10 % 以下,且更佳爲1 %以下。若氮源量過多時,則元件之驅 -14- 200541121 m 動電壓無法隨心所欲地降低。此時,若氮源流量也使其爲 零時,則將會導致來自構成P型層之結晶的氮進行脫離, 以導致元件之Vr降低。氮源量較佳爲設定爲全氣體量之體 積之0.001 %以上,更佳爲0.01 %以上。 此外,較佳爲在氮源之流量變更及剛切換載氣之後開始 降溫。若生長結束後的溫度之保持時間爲長時,則不僅是 將導致結晶性降低,將蓄積對發光層之熱損傷而降低發光 強度。 # 另外,必須將一旦降低流量的氮源之流量,在降溫過程 中實行完全使其成爲零之操作。藉由在未停止氮源流通下 ,使溫度降至例如300°C等之低溫所製造之元件,將因接 合時所施加之熱而產生元件驅動電壓上升之現象。 在降溫途中使氮源流量爲零之溫度,較佳爲950 °C以下 、700°C以上。若以高於950°C之溫度使氮源流量成爲零時 ,則元件之Vr將降低,若繼續使氮源流通至低於70CTC時 ,則將導致因熱使得驅動電壓上升。 B 再者,從生長結束後起至使氮源流量成爲零爲止之時間 ,雖然是視降溫速度而定,但是爲從約30秒鐘至約8分鐘 〇 本發明之III氮化物P型半導體及其製法,係可使用於 各種半導體元件之製造。例如除發光二極體或雷射二極體 等之半導體發光元件以外,只要是需要用到各種高速電晶 體或受光元件等之ΠΙ族氮化物P型半導體的半導體元件之 製造,則可使用於任何元件之製造,但是特別是適合於需 -15· 200541121 m 要形成pn接合與形成優良特性之電極的半導體發光元件之 製造。 第1圖係展示以使用本發明之ΠΙ族氮化物p型半導體 及其製法所製造之III族氮化物半導體發光元件示意模式圖 。其係必要時則隔著緩衝層2而將III族氮化物之η型半導 體層3、發光層4和ρ型半導體層5依此順次積層在基板1 上,且將負極6和正極7分別形成在η型半導體層3和ρ 型半導體層5上。 基板1係可在並無特殊的限定下使用藍寶石、sic、GaN 、AIN、Si、ZnO等及其他氧化物基板等之傳統習知的材料 。但是較佳爲藍寶石。緩衝層2係必要時爲調節基板與將 生長在其上面的η型半導體層3之晶格失配所設置。必要 時可使用傳統習知的緩衝層技術。 η型半導體層3之組成及結構’係可使用在該技術領域 中爲眾所皆知之習知的技術來形成吾人所希望之組成及結 構即可。通常η型半導體層係由可與負極獲得優良的歐姆 接觸之接觸層與比發光層具有大的帶隙能量之包層所構成 。負極6也可使用在該技術領域中爲眾所皆知之習知的技 術來形成吾人所希望之組成及結構即可。 發光層4也是可在並無特殊的限定下使用單一量子井結 構(SQW)及多重量子井結構(MQW)等傳統習知的組成 及結構。 ρ型半導體層5係由本發明之製造方法所形成。關於其 ,組$ &結構,則使用在該技術領域中爲眾人皆知的技術形 -16- 200541121 « m 成吾人所希望之組成及結構即可。通常與n型半導體層同 樣地係由可與負極獲得優良的歐姆接觸之接觸層與具有比 發光層大的帶隙能量之包層所構成。 可供接觸於以本發明之方法所製造之Ρ型層的正極7之 材料,可使用 Au、Ni、Co、Cu、Pd、Pt、Rh、Os、Ir、Ru 等之金屬。而且,也可含有IT〇或Ni0、co〇等之透明氧 化物。含透明氧化物之形態,可製成爲塊而包含在上述金 屬膜中,也可製成爲層狀而與上述金屬膜疊合來形成。 尤其是將Pd、Pt、Rh、Os、Ir、Ru等之白金族金屬用作 爲正極材料時,若使用本發明則可防止在接合時之熱而導 致驅動電壓上升,因此可發揮更大之功效。其中Pd、Pt、 Rh係比較容易取得高純度者,因此較容易使用。 而且,正極也可形成大致會覆蓋全面之方式,也可隔著 間隙而形成格子狀或樹形狀。經形成正極後,也有施加以 合金化或透明化爲目的之熱退火處理之情況,但是不施加 也無妨。 元件之形態也可爲使用透明正極以從半導體側導出發光 之所謂「面朝上組裝(FU )型」,也可製成爲使用反射型 正極以由基板側導出發光之所謂「覆晶晶片(FC )型」。 〔實施例〕 茲根據實施例將本發明詳加說明如下,但是本發明並不 受限於此等實施例。 〔實施例1〕 在第2圖展示使用於根據本實施例所製造LED 1 0之磊晶 -17- 200541121 積層結構體1 1之剖面模式圖。此外,在第3圖則展示 LED 10之俯視(平面)模式圖。 積層結構體1 1係在由藍寶石之c面((〇〇〇 1 )結晶面) 所構成之基板1 〇 1上,隔著由A1N所構成之緩衝層(未圖 示),將非摻雜的GaN層(層厚 =8微米)102、摻Si的 η型GaN層(層厚 =2微米、載子濃度 = lxl019cm·3) 103、摻Si的η型Al0.07Ga0.93N包層(層厚 =25奈米、 載子濃度 =1 X 1〇18 cnT3 ) 104、由6層之摻Si的GaN阻 • 障層(層厚=14.0奈米、載子濃度= lxl〇18 cm·3 )與5 層之非摻雜的InQ.2()Ga〇.8()N之井層(層厚 =2.5奈米)所 構成之多重量子結構之發光層105、摻Mg的p型 Al0.07Ga0.93N包層(層厚 =10奈米)106、及摻Mg的p 型AlG ()2Ga().98N接觸層(層厚 =150奈米)1〇7依此順序 予以積層所構成。上述積層結構體1 1之各構成層i 〇2〜 107係以一般的減壓MOCVD方法使其生長。 尤其是摻Mg的p型A1 GaN接觸層107係以下列順序使 •其生長: (〇 經結束摻Mg的p型Alo.07Gao.93N包層1〇6之生長 後,使生長反應爐內壓力設定爲2 X 1〇4帕斯卡<pa ):載氣係使用氫氣。 (2) 以三甲基鎵、三甲基鋁及氨作爲原料,以雙環戊稀 合鎂作爲Mg之摻雜源,並在1,〇2〇。<3開始摻Mg的 p型AlGaN層之氣相生長。 (3) 將三甲基鎵、三甲基鋁、氨及雙環戊烯合鎂,以歷 -18 - 20.0541121 時4分鐘繼續對生長反應爐內供應,以使層厚爲 0.15微米之丨参Mg的p型Al〇.〇2Ga〇.98N層生長。 (4) 停止對生長反應爐內供應三甲基鎵、三甲基鋁、氨 及雙環戊烯合鎂,以停止摻Mg的p型Alo.o2Gao.98N 層之生長。 經結束由摻Mg的p型AlGaN層所構成之接觸層107之 氣相生長後,立即將載氣由氫切換爲氮,並降低氨之流量 且以相當於所降低的部份之量增加載氣的氮之流量。具體 § 而言,將在生長中是佔全流通氣體量以體積計爲50 %之氨 ,予以減少至0.2 %。同時,停止對爲加熱基板101所使用 的高頻感應加熱式加熱器之通電。 然後,在此狀態保持2分鐘後,停止氨之流通。此時, 基板溫度爲85(TC。於第4圖展示該降溫過程之模式圖。 藉由在此狀態下冷卻至室溫後,由生長反應爐取出積層 結構體11,以一般的SIMS分析法將接觸層107之鎂及氫 之原子濃度加以定量。結果Mg原子係以7 X 1019 cnT3之 § 濃度且從表面向深度方向大致呈一定之濃度分佈。在另一 方面,氫原子係含有6 X 1019 cnT3之約一定的濃度。另外 ,電阻率係藉由一般的TLM (遙測)法之測定結果來估計 則大致爲1 5 0 Ω c m。 使用上述具有P型接觸層之磊晶積層結構體1 1以製造 LED 10。首先,在供形成負極108之預定區域施加一般的 乾蝕刻,且僅限於該區域使摻Si的GaN層103之表面露出 。在經露出的表面部份形成由疊層鈦(Ti ) /鋁(A1 )所構 -19- 200541121 成之負極108。 在剩餘的接觸層1 07之表面的約全域,則予以形成具有 可將來自發光層之發光向藍寶石基板101側反射的功能且 經疊層白金(Pt )膜/鍺(Rh )膜/金(Au )膜所構成之正 極109。與p型接觸層107之表面接觸之金屬膜係使用白 金膜。 經形成負極108和正極109後,則將藍寶石基板1〇1之 背面使用金剛石微粒之硏磨粒來加以硏磨,最後則予以精 ©加工成鏡面。然後切斷積層結構體11,予以分離成350微 米方形之正方形之個別LED 1 0。然後,使負極和正極分別 接著於子安裝架以製成覆晶型之晶片。此時將施加約爲 300°C之熱在晶片之電極。然後進一步使其載置於導線架後 ’以金(A u )線與導線架結線。 如上所述之步驟所製造之LED晶片,在其負極108和正 極109之間使正向電流流通,以評估電氣特性及發光特性 。正向電流設定爲20 mA時之正向驅動電壓(Vf)爲3.0 β V,使電流設定爲10// A時之逆向電壓(Vr)則爲20 V以 上。如此,並未發生因接合時之熱而導致驅動電壓上升。 而且,由藍寶石基板1〇1朝著外部透射的發光之波長爲 455奈米,且藉由一般的積分球所測定之發光輸出爲10 mW。另外,由直徑5 · 1公分(2英寸)之晶圓中除去外觀 不良品後,雖然獲得約爲1〇,〇〇〇個之LED ’但是全部在並 無變化下顯現出如上所述之特性。 〔實施例2〕 -20- 200541121 » · 以實施例2所製造之積層結構體爲如下述之結構。(1 3) If applying for § 靑 Patent $ 12, the light-emitting element in any one of items 9 to 11 is a face-up assembly type. According to the present invention, it is possible to obtain a p-type group III nitride semiconductor having sufficient characteristics at a level that can be used as a semiconductor element. In addition, by using the III-nitride p-type semiconductor, a III-nitride semiconductor light-emitting device having a high Vr without causing a rise in driving voltage due to heat can be manufactured at a high yield. [Embodiment] [Best Mode of the Present Invention] A group III nitride semiconductor of a group III nitride p-type semiconductor that can be applied to the manufacturing method of the present invention, in addition to GaN, includes: InN, A1N, etc. All type III nitride semiconductors such as elementary mixed crystals, ternary mixed crystals such as InGaN and AlGaN, and quaternary mixed crystals such as InAlGaN. However, in the present invention, it also further includes Group V elements other than nitrogen, that is, a ternary mixed crystal of GaPN, GaAs, or the like, or a quaternary of InGaPN, InGaAsN, AlGaPN, AlGaAsN, etc. which further contains In or A1. Is a mixed crystal, and further contains Alin GaPN, Alin GaAsN, -11-20P541121 of both In and A1, or a pentad system of five elementary mixed crystals including AlGaPAsN, InGaPAsN including both P and As, and contains all elements AlInGaPAsN's six-element mixed crystal is also included in the Group III nitride semiconductor. The present invention is among the above, and is particularly suitable for manufacturing binary mixed crystals of GaN, InN, A1N, etc., which are relatively easy to produce without risk of decomposition, ternary mixed crystals of InGaN, AlGaN, and the like Group III nitride semiconductors such as elementary mixed crystals that contain only N as a group V. When expressed by the general formula AlxInyGabX_yN (Ogx + y ^ l), X is preferably in the range of 0 to 0.5, and y is preferably in the range of 0 to 0.1. In addition, the P-type dopants that can be used in the present invention include Mg, Ca, Zn, Cd, Hg, etc., which have been disclosed as indicated or predicted to be doped in a group III nitride semiconductor, and exhibit p-type conductivity. . Among these, Mg having a high activation rate by heat treatment is particularly suitable for use as a p-type dopant. The amount of dopant used is preferably 1 X 1018 to 1 X 1021 cnT3. If it is less than 1 X 1018 cnT3, the luminous intensity will decrease. Conversely, if it is more than lx 1 021 cm_3, crystallinity will be deteriorated, so it is not good, and more preferably 1 X 1 019 to 1 X 1 02. cm · 3. The P-type semiconductor layer 'manufactured by the method disclosed in the present invention may also contain hydrogen atoms in its crystal. In order to manufacture a device having a high reverse voltage Vr, it is sometimes preferable to include a hydrogen atom in the crystal. The amount of hydrogen atoms contained in the crystal is preferably less than the amount of the doped P-type dopant. When the content of the hydrogen atom is the same as the content of the P-type dopant 'or more than the content of the P-type dopant, it is not easy to obtain the electrical contact of the P-type electrode, so it is preferably less than . The content of hydrogen atoms is more preferably P-type -12- 200541121 X ** The dopant is 9/10 or less, and particularly preferably 7/8 or less. However, if the content of the hydrogen atom is less than 1/5 of the P-type dopant, nitrogen detachment will occur at the same time, so it is preferably more than 1/5, more preferably 1/3 or more, and if 1/2 The above is more ideal. In addition, the atomic concentrations of magnesium and hydrogen in the 'P-type semiconductor layer are quantified by a general SIMS (Primary Ion Mass Spectroscopy). In addition, the P-type layer system does not become low in resistance due to the inclusion of hydrogen in the crystal, but it does not pose a problem in device characteristics. In a device using a III-nitride semi-conductor ', since the P-type layer is mostly formed thinner than other semiconductors, the resistance of the P-type layer itself does not cause much influence on the driving voltage Vf of the device. The resistivity of the p-type layer is high, and it is desirable to maintain a high Vr. The resistivity of the P-type layer is preferably about 20 Ω cm to 10,000 Ω cm. If it is higher than 10,000 Ωοιη, the luminous intensity will be reduced. If it is lower than 20Qcm, Vr may be lowered. More preferably, it is 50 Ω cm to 2,000 Ω cm, and particularly preferably 100 Qcm to 1,000 Qcm. In addition, the resistivity is measured by a general TLM (Transfer Length Measurement) method. The method for growing the group III nitride p-type semiconductor of the present invention is not particularly limited, and MOCVD (metal organic chemical vapor growth), HVPE (hydrogen vapor phase epitaxial growth), and MBE (molecular beam) can be used. All methods known for epitaxial growth) are available for growing Group III nitride semiconductors. A preferred growth method is a MOCVD method from the viewpoint of film thickness controllability and mass productivity. -13- 200541121 €, in the MOCVD method, the carrier gas is hydrogen (h2) or nitrogen (n2), and the Ga source of Group III is trimethylgallium (TMG) or triethylgallium (TEG), A1 Source system uses trimethyl aluminum (TMA) or triethyl bromide (TEA) 'In source system uses dimethyl alcohol (TMI) or diethyl alcohol (TEI)' Nitrogen source system uses ammonia (NH3) or Ammonia (N2H4) and so on. In addition, in the p-type dopant, the Mg raw material is, for example, dicyclopentadienyl magnesium (Cp2 Mg) or diethylcyclopentyl diene ((EtCp) 2 Mg), and the Zn raw material is dimethyl zinc ( Zn (CH3) 2). The effect of the present invention is great if the carrier gas contains Η2, and / or NΗ3 is used as the nitrogen source. In order to obtain excellent crystallinity and contact resistance, the growth temperature is preferably a temperature of 1,000 ° C or more, and more preferably 1,050 ° C or more and 1,250 ° C or less. After growing a group III nitride semiconductor containing a p-type dopant, the temperature is lowered to room temperature, and then the semiconductor laminate is removed from the growth device. If the carrier gas contains hydrogen during the growth, it must be immediately after the growth is completed. The carrier gas was switched to an inert gas not containing hydrogen at the same temperature as the growth temperature. If the flow of hydrogen gas continues for about one minute behind the time required for switching, the drive voltage cannot be sufficiently reduced. The inert gas used to replace the carrier gas is preferably nitrogen, but argon, helium, and the like, and mixtures thereof may also be used. In addition, it is important to reduce the flow rate of the nitrogen source at the same time as switching the carrier gas. The nitrogen source supply during growth is usually 20% to 70% of the total gas volume, but the nitrogen source amount after reducing the nitrogen source is preferably 10% or less of the total gas volume, and more preferably 1% or less. If the amount of nitrogen source is too much, the driving voltage of the element cannot be reduced as desired. At this time, if the flow rate of the nitrogen source is also made zero, the nitrogen from the crystals constituting the P-type layer will be detached, and the Vr of the device will be reduced. The amount of nitrogen source is preferably set to 0.001% or more, and more preferably 0.01% or more of the total gas volume. In addition, it is preferable to start the temperature reduction immediately after the flow rate of the nitrogen source is changed and the carrier gas is switched. If the temperature is held for a long time after the growth is completed, not only the crystallinity will be reduced, but also the thermal damage to the light emitting layer will be accumulated and the light emission intensity will be reduced. # In addition, once the flow rate of the nitrogen source is reduced, the operation of completely reducing it to zero during the temperature reduction process must be performed. A component manufactured by reducing the temperature to a low temperature, such as 300 ° C, without stopping the flow of nitrogen source, will increase the driving voltage of the component due to the heat applied during bonding. The temperature at which the flow rate of the nitrogen source is zero during the cooling process is preferably 950 ° C or lower and 700 ° C or higher. If the nitrogen source flow rate becomes zero at a temperature higher than 950 ° C, the Vr of the device will decrease. If the nitrogen source continues to flow below 70CTC, the driving voltage will increase due to heat. B In addition, the time from the completion of growth to the time when the nitrogen source flow rate becomes zero depends on the cooling rate, but it is from about 30 seconds to about 8 minutes. The III nitride P-type semiconductor of the present invention and The manufacturing method can be used for manufacturing various semiconductor devices. For example, in addition to semiconductor light-emitting elements such as light-emitting diodes and laser diodes, as long as it is a semiconductor element that uses a group III nitride P-type semiconductor such as various high-speed transistors or light-receiving elements, it can be used in The manufacture of any element, but especially suitable for the manufacture of semiconductor light-emitting elements that need -15 · 200541121 m to form a pn junction and an electrode with excellent characteristics. FIG. 1 is a schematic diagram showing a group III nitride semiconductor light-emitting device manufactured by using the group III nitride p-type semiconductor of the present invention and a manufacturing method thereof. When necessary, the n-type semiconductor layer 3, the light-emitting layer 4, and the p-type semiconductor layer 5 of the group III nitride are sequentially laminated on the substrate 1 through the buffer layer 2, and the negative electrode 6 and the positive electrode 7 are formed separately. On the n-type semiconductor layer 3 and the p-type semiconductor layer 5. The substrate 1 is a conventionally known material that can use sapphire, sic, GaN, AIN, Si, ZnO, and other oxide substrates without particular limitation. However, sapphire is preferred. The buffer layer 2 is provided for adjusting a lattice mismatch of the substrate and the n-type semiconductor layer 3 to be grown thereon as necessary. Where necessary, conventionally known buffer layer techniques can be used. The composition and structure of the n-type semiconductor layer 3 can be formed into a composition and structure that we desire using a well-known technique known in the technical field. Generally, the n-type semiconductor layer is composed of a contact layer which can obtain excellent ohmic contact with the negative electrode and a cladding layer which has a larger band gap energy than the light emitting layer. The negative electrode 6 may be formed into a composition and a structure desired by us by using a technique known in the art. The light emitting layer 4 also has a conventionally known composition and structure such as a single quantum well structure (SQW) and a multiple quantum well structure (MQW) without special restrictions. The p-type semiconductor layer 5 is formed by the manufacturing method of the present invention. Regarding its structure, the group $ & structure can use the technical form that is well known in the technical field -16- 200541121 «m into the composition and structure that I hope. Usually, the n-type semiconductor layer is composed of a contact layer which can obtain excellent ohmic contact with the negative electrode and a cladding layer having a band gap energy larger than that of the light-emitting layer. As the material for contacting the positive electrode 7 of the P-type layer produced by the method of the present invention, metals such as Au, Ni, Co, Cu, Pd, Pt, Rh, Os, Ir, Ru, and the like can be used. Further, it may contain transparent oxides such as IT0, Ni0, and co0. The transparent oxide-containing form may be formed as a block and included in the above-mentioned metal film, or may be formed in a layered form and laminated with the above-mentioned metal film. In particular, when platinum group metals such as Pd, Pt, Rh, Os, Ir, and Ru are used as the positive electrode material, the use of the present invention can prevent the driving voltage from being increased due to heat during bonding, and thus can exert greater efficacy. . Among them, Pd, Pt, and Rh are relatively easy to obtain with high purity, so they are easier to use. In addition, the positive electrode may be formed so as to cover the entire surface, or may be formed in a grid or tree shape with a gap therebetween. After the positive electrode is formed, a thermal annealing treatment may be applied for the purpose of alloying or transparency, but it may not be applied. The form of the device may be a so-called "face-up assembly (FU) type" that uses a transparent positive electrode to emit light from the semiconductor side, or a so-called "chip-on-chip (FC)" that uses a reflective positive electrode to emit light from the substrate side. )type". [Embodiments] The present invention will be described in detail based on the embodiments, but the present invention is not limited to these embodiments. [Embodiment 1] A schematic cross-sectional view of an epitaxial -17-200541121 laminated structure 11 used in the LED 10 manufactured according to this embodiment is shown in FIG. In addition, the top view (planar) view of the LED 10 is shown in FIG. 3. The laminated structure 11 is non-doped on the substrate 1 01 composed of the c-plane ((001) crystal surface) of sapphire through a buffer layer (not shown) composed of A1N. GaN layer (layer thickness = 8 microns) 102, Si-doped η-type GaN layer (layer thickness = 2 microns, carrier concentration = lxl019cm · 3) 103, Si-doped η-type Al0.07Ga0.93N cladding (layer Thickness = 25 nm, carrier concentration = 1 X 1018 cnT3) 104. Six layers of Si-doped GaN barrier layer (layer thickness = 14.0 nm, carrier concentration = lxl018 cm · 3) Multi-quantum structure light emitting layer 105 composed of 5 layers of non-doped InQ.2 () Ga0.8. (N) well layer (layer thickness = 2.5nm), Mg-doped p-type Al0.07Ga0 A .93N cladding (layer thickness = 10 nm) 106 and a M-doped p-type AlG () 2Ga (). 98N contact layer (layer thickness = 150 nm) 107 are laminated in this order. Each of the constituent layers i 02 to 107 of the laminated structure 11 is grown by a general reduced pressure MOCVD method. In particular, the Mg-doped p-type A1 GaN contact layer 107 is grown in the following order: (0) After the growth of the M-doped p-type Alo.07Gao.93N cladding layer 106 is completed, the pressure in the growth reaction furnace is increased. Set to 2 × 104 Pascal < pa): Hydrogen was used as the carrier gas. (2) Trimethylgallium, trimethylaluminum, and ammonia are used as raw materials, and dicyclopentane dilute magnesium is used as the doping source of Mg, and the concentration is 1.02. < 3 Begin vapor-phase growth of a Mg-doped p-type AlGaN layer. (3) Continue supplying trimethylgallium, trimethylaluminum, ammonia and dicyclopentene magnesium to the growth reaction furnace at -18-20.0541121 for 4 minutes, so that the thickness of the layer is 0.15 μm. A p-type Al.02Ga.98N layer was grown. (4) Stop supplying trimethylgallium, trimethylaluminum, ammonia and dicyclopentenemagnesium to the growth reactor to stop the growth of the M-doped p-type Alo.o2Gao.98N layer. Immediately after the vapor phase growth of the contact layer 107 composed of the Mg-doped p-type AlGaN layer was completed, the carrier gas was immediately switched from hydrogen to nitrogen, and the ammonia flow rate was reduced and the load was increased by an amount equivalent to the reduced portion Gas nitrogen flow. Specifically, § 50% by volume of ammonia, which is the total circulating gas volume, will be reduced to 0.2% during growth. At the same time, the energization of the high-frequency induction heating heater used for heating the substrate 101 is stopped. After this state was maintained for 2 minutes, the circulation of ammonia was stopped. At this time, the substrate temperature is 85 ° C. The schematic diagram of the cooling process is shown in Fig. 4. After cooling to room temperature in this state, the laminated structure 11 is taken out from the growth reaction furnace, and the general SIMS analysis method is used. The atomic concentrations of magnesium and hydrogen in the contact layer 107 were quantified. As a result, the Mg atoms were distributed at a concentration of § 7 X 1019 cnT3 and were approximately constant from the surface to the depth. On the other hand, the hydrogen atom system contained 6 X 1019 cnT3 is about a certain concentration. In addition, the resistivity is estimated by the general TLM (telemetry) measurement result to be approximately 15 0 Ω cm. Using the above epitaxial laminated structure 1 with a P-type contact layer 1 to manufacture the LED 10. First, general dry etching is applied to a predetermined region where the negative electrode 108 is to be formed, and the surface of the Si-doped GaN layer 103 is exposed only in this region. A laminated titanium is formed on the exposed surface portion. (Ti) / aluminum (A1) structure -19- 200541121 into the negative electrode 108. In the entire area of the surface of the remaining contact layer 107, it is formed to have a structure capable of reflecting the light emitted from the light-emitting layer to the sapphire substrate 101 side. Functional and economical The positive electrode 109 composed of a platinum (Pt) film / germanium (Rh) film / gold (Au) film. The metal film in contact with the surface of the p-type contact layer 107 is a platinum film. After forming the negative electrode 108 and the positive electrode 109, The back surface of the sapphire substrate 101 is honed with diamond particles and finally polished into a mirror surface. Then the laminated structure 11 is cut and separated into individual LEDs of 350 micron square 1 0. Then, the negative electrode and the positive electrode are respectively attached to the sub-mounting frame to make a flip-chip type wafer. At this time, about 300 ° C of heat is applied to the wafer electrode. Then it is further placed behind the lead frame ' A gold (Au) wire is connected to the lead frame. In the LED chip manufactured in the above steps, a forward current is passed between the negative electrode 108 and the positive electrode 109 to evaluate the electrical characteristics and light emission characteristics. The forward current setting The forward drive voltage (Vf) at 20 mA is 3.0 β V, and the reverse voltage (Vr) when the current is set to 10 // A is 20 V or more. In this way, no heat caused by the heat during bonding occurs. The driving voltage rises. The wavelength of the light transmitted from the outside to the outside is 455 nanometers, and the luminous output measured by a general integrating sphere is 10 mW. In addition, the appearance is removed from a 5 · 1 cm (2 inch) wafer After defective products, although about 10,000 LEDs were obtained, all of them exhibited the characteristics as described above without change. [Example 2] -20-200541121 »· Manufactured in Example 2 The laminated structure has the following structure.
積層結構體1 1係在由藍寶石之C面((0 0 0 1 )結晶面) 所構成之基板101上,隔著由A1N所構成之緩衝層(未圖 示),將非摻雜的GaN層(層厚=8微米)102、摻Ge的 η型GaN層(層厚 =2微米、載子濃度 = 7xl018cnT3) 103、摻Si的η型Ino.cnGaowN包層(層厚 =18奈米、載 子濃度 =1 x 1〇18 cm·3 ) 1〇4、由6層之摻Si的GaN阻障 層(層厚 =14.0奈米、載子濃度=1 X 1〇17 cnT3 )與5 層之非摻雜的In().2()Ga〇.8()N之井層(層厚 =2.5奈米)所 構成之多重量子結構之發光層105、摻 Mg的ρ型 Al0.07Ga0.93N包層(層厚 =12奈米)106、及摻Mg的 Alo.o2Gao.98N接觸層(層厚 =175奈米)107依此順序予 以積層所構成。上述積層結構體1 1之各構成層102〜107 係使用一般的減壓MOCVD方法使其生長。 摻Mg的AlGaN接觸層107係以與實施例1相同順序使 其生長。氣相生長結束後,積層結構體1 1係以與實施例1 相同順序使其冷卻至室溫。 經冷卻至室溫後,由生長反應爐取出積層結構體1 1,藉 由一般的SIMS分析法將接觸層107之鎂及氫之原子濃度 加以定量。結果Mg原子係以1.5 X 102G cnT3之濃度且從 表面朝著深度方向大致一定之濃度分佈。在另一方面,氫 原子係含有8 X 1019 cnT3之約一定的濃度。另外,電阻率 係藉由一般的TLM法之測定結果來估計則大致爲1 80 Ω cm -21 · 200541121 使用上述具有P型接觸層之磊晶積層結構體11以製造 LED 1 0。製造之順序、電極之結構等係與實施例1相同。 藉由如上所述之步驟所製造之LED晶片,在其負極108 和正極1 09之間使正向電流流通以評估電氣特性及發光特 性。正向電流設定爲20 mA時之正向驅動電壓(Vf)爲 3.3 V,使電流設定爲10 // A時之逆向電壓(Vr )則爲20 V以上。如此,並未發生因接合時之熱而導致驅動電壓上 而且,由藍寶石基板1 〇 1朝著外部透射的發光之波長爲 470奈米,且藉由一般的積分球所測定之發光輸出爲12 m W。另外,由直徑5 · 1公分(2英寸)之晶圓中除去外觀 不良品後,雖然獲得約爲1〇,〇〇〇個之LED,但是全部在並 無變化下顯現出如上所述之特性。 〔比較例1〕 除改變生長後之處理法以外,其餘則以與上述實施例1 相同地形成摻Mg的p型AlGaN接觸層。亦即,在本比較 例,則根據與實施例1所揭示相同之順序、條件形成實施 例1所揭示之積層結構體後,雖然將在氣相生長時所使用 的載氣之氫予以切換爲氮,但是氨則在生長結束時予以減 爲0·2 %後,然後繼續使其流通,降溫至350t。第5圖係 以模式展示該降溫過程之圖。 對於藉由比較例1所製得之試料,根據與實施例相同地 藉由SIMS法測定Mg、Η之濃度,結果Mg原子濃度爲7 X 1019 cnT3之與實施例1之情況相同,在另一方面,氫原子 -22- 200541121 含有7 x l〇19 cm·3之濃度。另外,根據與實施例丨相同之 TLM法測定電阻率結果,大致估計爲15,〇〇〇Qcm。 將與實施例1相同地製成爲FC型元件之晶片載置於導 線架上,然後在負極108和正極109之間使正向電流流通 ’以評估電氣特性及發光特性。正向電流設定爲20 mA時 之正向驅動電壓(Vf)係上升爲4.0 V,發光輸出則爲8 mW。 〔比較例2〕 除改變生長後之處理法以外,其餘則以與上述實施例1 相同地形成摻Mg的p型GaN接觸層。亦即,在本比較例 ,則根據與實施例1所揭示相同之順序、條件形成實施例 1所揭示之積層結構體後,在氣相生長時所使用的載氣之 氫則予以切換爲氮,同時停止氨之流通,並降溫至350°C 。第6圖係以模式展示該降溫過程之圖。 對於藉由比較例2所製得之試料,根據與實施例相同地 藉由SIMS法測定Mg、Η之濃度,結果Mg原子濃度爲7 X 1019 cnT3之與實施例1之情況相同,在另一方面,氫原子 含有1 X 1019 cm_3之濃度。另外,根據與實施例1相同之 TLM法測定電阻率結果,大致估計爲10 Ω cm。 將與實施例1相同地製成爲FC型元件之晶片載置於導 線架上,然後在負極108和正極109之間使正向電流流通 ,以評估電氣特性及發光特性。正向電流設定爲20 mA時 之正向驅動電壓(Vf)爲3.0 V,發光輸出則爲10 mW, 但是電流設定爲1 〇 # A時之逆向電壓(Vr )則爲5 V。 -23- 200541121 〔實施例3〕 在實施例3,則使用與在實施例1所揭示者相同之積層 結構體,並予以形成FU型之電極以製得LED。第7圖係 根據本實施例所形成之電極之俯視(平面)圖。 在剩餘的接觸層1 07之表面的約全域,則予以形成具有 可將來自發光層之發光導出至外部之透光性且經疊層白金 (PO膜/金(Αι〇膜所構成之正極109。與p型接觸層 107之表面接觸之金屬膜係使用白金膜。 β 並且,進一步在上述透光性電極109之上面形成最外表 面爲使用Αιι之接合墊1 1 0。然後,則以與實施例1相同順 序予以分離成350微米方形之正方形的個別LED20。The laminated structure 11 is a substrate 101 composed of the C-plane ((0 0 0 1) crystal plane) of sapphire, and a non-doped GaN is interposed therebetween via a buffer layer (not shown) composed of A1N. Layer (layer thickness = 8 microns) 102, Ge-doped η-type GaN layer (layer thickness = 2 microns, carrier concentration = 7xl018cnT3) 103, Si-doped η-type Ino.cnGaowN cladding (layer thickness = 18 nm, Carrier concentration = 1 x 1018 cm · 3) 104. Six layers of Si-doped GaN barrier layer (layer thickness = 14.0 nm, carrier concentration = 1 X 1017 cnT3) and 5 layers Non-doped In (). 2 () Ga.8 () N well layer (layer thickness = 2.5nm) composed of a multiple quantum structure light emitting layer 105, Mg-doped p-type Al0.07Ga0. The 93N cladding (layer thickness = 12 nm) 106 and the Mg-doped Alo.o2Gao.98N contact layer (layer thickness = 175 nm) 107 are laminated in this order. Each of the constituent layers 102 to 107 of the laminated structure 11 is grown using a general reduced pressure MOCVD method. The Mg-doped AlGaN contact layer 107 was grown in the same order as in Example 1. After the vapor phase growth was completed, the laminated structure 11 was cooled to room temperature in the same procedure as in Example 1. After cooling to room temperature, the laminated structure 11 was taken out from the growth reaction furnace, and the atomic concentrations of magnesium and hydrogen in the contact layer 107 were quantified by a general SIMS analysis method. As a result, the Mg atomic system was distributed at a concentration of 1.5 X 102G cnT3 and a constant concentration from the surface toward the depth. On the other hand, the hydrogen atom system contains about a certain concentration of 8 X 1019 cnT3. In addition, the resistivity is estimated by the measurement result of the general TLM method to be approximately 1 80 Ω cm -21 · 200541121. The above-mentioned epitaxial laminated structure 11 having a P-type contact layer is used to manufacture LED 10. The manufacturing procedure, the structure of the electrodes, and the like are the same as those of the first embodiment. With the LED chip manufactured by the steps described above, a forward current is passed between the negative electrode 108 and the positive electrode 109 to evaluate electrical characteristics and light emission characteristics. When the forward current is set to 20 mA, the forward drive voltage (Vf) is 3.3 V, and when the current is set to 10 // A, the reverse voltage (Vr) is 20 V or more. In this way, the driving voltage did not occur due to the heat at the time of bonding, and the wavelength of the light transmitted from the sapphire substrate 101 to the outside was 470 nm, and the light output measured by a general integrating sphere was 12 m W. In addition, after removing defective appearance products from a wafer with a diameter of 5.1 cm (2 inches), although about 100,000 LEDs were obtained, all of them exhibited the characteristics as described above without change. . [Comparative Example 1] A Mg-doped p-type AlGaN contact layer was formed in the same manner as in Example 1 except that the treatment method after growth was changed. That is, in this comparative example, after forming the laminated structure disclosed in Example 1 under the same sequence and conditions as those disclosed in Example 1, the hydrogen of the carrier gas used in the vapor phase growth was switched to Nitrogen, but ammonia was reduced to 0.2% at the end of the growth, and then continued to circulate and cooled to 350t. Figure 5 is a diagram showing the cooling process in a pattern. With respect to the sample prepared in Comparative Example 1, the Mg and scandium concentrations were measured by SIMS in the same manner as in the Example. As a result, the Mg atomic concentration was 7 X 1019 cnT3, which was the same as that in Example 1. On the one hand, the hydrogen atom-22-200541121 contains a concentration of 7 x 1019 cm · 3. The resistivity measurement result by the same TLM method as in Example 丨 was roughly estimated to be 15,000 Qcm. A wafer fabricated as an FC-type element in the same manner as in Example 1 was placed on a lead frame, and a forward current was passed between the negative electrode 108 and the positive electrode 109 to evaluate electrical characteristics and light emission characteristics. When the forward current is set to 20 mA, the forward drive voltage (Vf) rises to 4.0 V, and the light emission output is 8 mW. [Comparative Example 2] A p-type GaN contact layer doped with Mg was formed in the same manner as in Example 1 except that the treatment method after growth was changed. That is, in this comparative example, after forming the laminated structure disclosed in Example 1 under the same sequence and conditions as those disclosed in Example 1, the hydrogen of the carrier gas used in the vapor phase growth was switched to nitrogen. At the same time, stop the circulation of ammonia and reduce the temperature to 350 ° C. Figure 6 is a diagram showing the cooling process in a pattern. For the sample prepared in Comparative Example 2, the Mg and rhenium concentrations were measured by the SIMS method in the same manner as in the Example. As a result, the Mg atomic concentration was 7 X 1019 cnT3, which was the same as that in Example 1. On the one hand, the hydrogen atom contains a concentration of 1 X 1019 cm_3. The resistivity measured by the same TLM method as in Example 1 was estimated to be about 10 Ω cm. The wafer fabricated as an FC-type element in the same manner as in Example 1 was placed on a lead frame, and then a forward current was passed between the negative electrode 108 and the positive electrode 109 to evaluate electrical characteristics and light emission characteristics. When the forward current is set to 20 mA, the forward drive voltage (Vf) is 3.0 V, and the light-emitting output is 10 mW. However, when the current is set to 1 〇 # A, the reverse voltage (Vr) is 5 V. -23- 200541121 [Example 3] In Example 3, the same laminated structure as that disclosed in Example 1 was used, and a FU-type electrode was formed to obtain an LED. Fig. 7 is a plan (planar) view of an electrode formed according to this embodiment. In the entire area of the surface of the remaining contact layer 107, a positive electrode 109 composed of laminated platinum (PO film / gold (Aluminum film)) having a light-transmitting property that can emit light from the light-emitting layer to the outside is formed. The metal film that is in contact with the surface of the p-type contact layer 107 is a platinum film. Β Further, the outermost surface formed on the light-transmitting electrode 109 is a bonding pad 1 1 0 made of Al. In Example 1, the individual LEDs 20 are separated into 350 micron squares in the same order.
如上所述之步驟所製造之LED晶片,在其負極108和正 極1 09之間使正向電流流通,以評估電氣特性及發光特性 。正向電流設定爲20 mA時之正向驅動電壓(Vf)爲3.0 V,使電流設定爲10 # A時之逆向電壓(V〇則爲20 V以 上。而且,由半導體層側朝著外部透射的發光之波長爲 ® 455奈米,且藉由一般的積分球所測定之發光輸出爲6 mW 。另外,由直徑5.1公分(2英寸)之晶圓中除去外觀不良 品後,雖然獲得約爲1〇,〇〇〇個之LED,但是全部在並無變 化顯現出如上所述之特性。 〔產業上之利用性〕 根據本發明所提供之III族氮化物p型半導體之製法, 係可同時實現高Vr與低驅動電壓之特性。因此,在III族 氮化物半導體發光元件之製造上極其有用。 -24- 200541121 【圖式簡單說明】 第1圖係以模式展示本發明之III族氮化物半導體發光 元件圖。 第2圖係以實施例1所製造之磊晶積層結構體之剖面模 式圖。 第3圖係以實施例1所製造之LED之俯視(平面)模式 圖。 第4圖係展示在實施例1之降溫方法模式圖。In the LED chip manufactured by the steps described above, a forward current is passed between the negative electrode 108 and the positive electrode 109 to evaluate electrical characteristics and light emission characteristics. When the forward current is set to 20 mA, the forward drive voltage (Vf) is 3.0 V, and when the current is set to 10 # A, the reverse drive voltage (V0 is 20 V or more. In addition, the semiconductor layer side is transmitted to the outside. The light emission wavelength is ® 455 nm, and the light emission output measured by a general integrating sphere is 6 mW. In addition, after removing a defective appearance from a wafer having a diameter of 5.1 cm (2 inches), 10,000 LEDs, but all of them show the above-mentioned characteristics without change. [Industrial Applicability] According to the method for manufacturing a group III nitride p-type semiconductor provided by the present invention, it can be simultaneously Realize the characteristics of high Vr and low driving voltage. Therefore, it is extremely useful in the manufacture of III-nitride semiconductor light-emitting devices. -24- 200541121 [Brief Description of the Drawings] Figure 1 shows the III-nitride of the present invention in a pattern. Figure of a semiconductor light-emitting element. Figure 2 is a schematic cross-sectional view of an epitaxial laminated structure manufactured in Example 1. Figure 3 is a plan (planar) schematic view of an LED manufactured in Example 1. Figure 4 is a Shown in Example 1 Temperature method pattern diagram.
第5圖係展示在比較例1之降溫方法模式圖。 第6圖係展示在比較例1之降溫方法模式圖。 第7圖係以實施例2所製造之LED之俯視(平面)模式 圖。 【主要元件符號說明】 1 基板 2 緩衝層 3 η型半導體層 4 發光層 5 Ρ型半導體層 6 負極 7 正極 10 LED 11 積層結構體 20 LED 101 基板 -25- • 200541121FIG. 5 is a schematic diagram showing a cooling method in Comparative Example 1. FIG. FIG. 6 is a schematic diagram showing a cooling method in Comparative Example 1. FIG. FIG. 7 is a plan view (planar view) of the LED manufactured in Example 2. FIG. [Description of main component symbols] 1 substrate 2 buffer layer 3 n-type semiconductor layer 4 light-emitting layer 5 P-type semiconductor layer 6 negative electrode 7 positive electrode 10 LED 11 laminated structure 20 LED 101 substrate -25- • 200541121
102 非摻雜的 103 η 型 GaN 104 包層 105 發光層 106 包層 107 接觸層 108 負極 109 正極 1 10 接合墊102 undoped 103 η-type GaN 104 cladding 105 luminescent layer 106 cladding 107 contact layer 108 negative electrode 109 positive electrode 1 10 bonding pad
GaN層 層GaN layer layer
-26--26-
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