TW200540927A - Composite electronic component, and manufacturing method thereof - Google Patents

Composite electronic component, and manufacturing method thereof Download PDF

Info

Publication number
TW200540927A
TW200540927A TW094105104A TW94105104A TW200540927A TW 200540927 A TW200540927 A TW 200540927A TW 094105104 A TW094105104 A TW 094105104A TW 94105104 A TW94105104 A TW 94105104A TW 200540927 A TW200540927 A TW 200540927A
Authority
TW
Taiwan
Prior art keywords
electronic component
circuit substrate
circuit
resin
circuit board
Prior art date
Application number
TW094105104A
Other languages
Chinese (zh)
Inventor
Yuki Yamamoto
Jun Harada
Katsuro Hirayama
Original Assignee
Murata Manufacturing Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co filed Critical Murata Manufacturing Co
Publication of TW200540927A publication Critical patent/TW200540927A/en

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/162—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits the devices being mounted on two or more different substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/063—Lamination of preperforated insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614—Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

The multilayer board described in patent document 1 has a build-up layer (3) thinner than the height of an electronic component (2) on a core board (1), the laminated body is dipped in an acid plating bath in order to form a copper wiring pattern (4A), and then forms a copper wiring pattern (4) by desmearing with alkaline desmearing liquid. Therefore, the electronic component (2) is exposed to the acid plating liquid. By means of using desmear liquid, it forms the copper wiring pattern(4). Under such condition, the characteristics of the electronic component (2) might be worsened. This invention provides composite electronic component (10). It comprises a first circuit board, a second circuit board, and a resin part. An electronic component (11) is mounted on the first circuit board (12). The second circuit board (14) possesses a through hole (14A), it contains the electronic component (11). The electronic component electrically connects with the first circuit board (12). The electronic component (11) is contained in the through hole (14A). The resin part (15) is formed in the gap between the through hole (14A) and the electronic component (11).

Description

200540927 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種内藏電子零件而模組化之複合型電子 零件及其製造方法，進一步詳細而言，係關於可促進小型 化、扁平化及高功能化之複合型電子零件及其製造方法。 【先前技術】 近年來，隨著行動電話等移動式通訊機器及電子機器之 小型化，電子零件之小型化快速發展。特別是基於節省空 間化之要求，而強烈要求内藏電子零件而模組化之複合型 電子零件之小型化、扁平化。以複合型電子零件之小型化 為目的之技術，如專利文獻1中提出有多層基板，專利文 獻2中提出有内藏零件模組及其製造方法。此外，專利文 獻3中提出有内藏電子零件印刷配線基板。 專利文獻1中之多層基板係具有：核心基板與增加層之 電路基板，且在增加層内内藏電子零件者。製造該多層基 板If况下’如圖13之⑷所示，在核心基板i上搭載電子零 件2，如該圖之（b)所示，在核心基板i之搭載面上形成增加 層後於增加層3之表面形成銅配線圖案4。其次如圖13 之（0所不，藉由在增加層3之上面堆疊增加層5，來製造多 層基板。基板愈形成高密度配線，增加層及銅配線圖案之 疊層數亦愈增加。 此外，專利文獻2之内藏零件模組具有：電絕緣層；經 由電絕緣層而堆疊之數層之第—配線圖案；分別電性連接 在不同層之第一配線圖案間之第-内部導通孔；及埋設於 99412.doc 200540927 電絕緣層内部之電子零件。製造該内藏零件模組情況下， 如圖14之⑷，(b)所示’分別製作：電絕緣層ia，其係包 含具有第-配線圖案2A及第—内部導通孔3A之未硬化狀 態之熱硬化性樹脂；及電絕緣層1β，其係具有第一内部導 通孔3B。此外’如該圖之⑷所示，製作安裝有電子零件 4A之載子5A。而後，在載子从上堆疊、壓接未硬化狀態 之電絕緣層ΙΑ，1B而獲得叠層體。其次，處理該叠層 體’使電絕緣層ΙΑ，1B熱硬化，並藉由除去載子5A而獲 t 得内藏零件模組。 此外，專利文獻3之内藏電子零件印刷配線基板係堆疊 數層具備内層電路之基板而構成，周壁不配置導體，設置 貝穿孔，在該貫穿孔内配置電子零件而連接於内層電路 者。内藏電子零件之印刷配線基板情況下，藉由周壁不配 置導體而鑿開設置貫穿孔，在該貫穿孔内配置電子零件， 因此可使印刷配線基板扁平化並且不需要焊錫。 > 專利文獻1 :特開2002-084071號公報 專利文獻2 :特開2002-29005 1號公報 專利文獻3 :特開2003-168871號公報 【發明内容】 但是’製造專利文獻i之多層基板情況下，在核心基板1 上堆疊比電子零件2之高度薄之增加層3後，為了形成銅配 線圖案4A ’需要將疊層體浸潰於除膠渣處理液、無電解電 錢液、電解電鍍液及蝕刻液等，因此每次形成銅配線圖案 4時，係將電子零件1暴露於上述各處理液中，可能造成電 99412.doc 200540927 子零件2之特性惡化。 此外，製造專利文獻2之内藏零件模組情況下，由於係 . 自電子零件4 A之上方堆疊、壓接未硬化狀態之電絕緣層 • 1A，1B於載子5A上，未硬化狀態之電絕緣層ία，1B在圖 14之（d)中如箭頭所示，藉由電子零件4A而排除至周圍， 電絕緣層1A，1B内之包含導電性導通孔膏之第一内部導 通孔3 A，3B彎曲，而引起位置偏差，可能在第一配線圖 案2A與第一内部導通孔3A，3B之間及第一内部導通孔 ® 3A ’ 3B之間，亦即在基板之内部配線中產生導通不良。 此外，製造專利文獻3之内藏電子零件之印刷配線基板 清況下’形成到達配置於貫穿孔内之電子零件之導通孔， 或在導通孔中形成連接於電子零件之導體膜時，與上述情 況同樣地，可能因蝕刻液及電鍍液等處理液侵入而損傷電 子零件。 為了解決上述問題，本發明之目的在提供一種可確實防 肇止内藏電子零件之特性惡化及内部配線之導通不良，而提 高可靠性，並且可實現小型化及扁平化之複合型電子零件 及其製造方法。 此外，本發明之目的在提供一種可確實防止内藏電子零 件之特性惡化及内部配線之導通不良，而提高可靠性，並 且可實現小型4匕、扁ip·化及高功能化之複合型電子零件及 .其製造方法。此外，本發明之目的在一併提供可對安裝用 基板轉印之複合型電子零件。 本發明之請求们之複合型電子零件之特徵為具備：第 99412.doc 200540927 一電路基板，其係安裝有至少1個電子零件；&第二電路 基板，其係具有收容上述電子零件之貫穿孔，且在該貫穿 孔内收容有上述電子零件狀態下，電性連接於上述第一電 路基板；上述第二電路基板具有：堆疊有數層之絕緣層， 及形成於該絕緣層之一面之面内配線導體。 此外，本發明之請求項2之複合型電子零件之特徵為： 、 以在上述貫穿孔内具備形成於與200540927 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a modular electronic component with a built-in electronic component and a manufacturing method thereof. More specifically, it relates to the promotion of miniaturization and flatness. And highly functional composite electronic parts and manufacturing methods thereof. [Previous Technology] In recent years, with the miniaturization of mobile communication devices such as mobile phones and electronic devices, the miniaturization of electronic parts has rapidly developed. In particular, based on the requirements of space saving, there is a strong demand for miniaturization and flatness of modular electronic components with built-in electronic components. For the purpose of miniaturizing composite electronic parts, for example, a multi-layer substrate is proposed in Patent Document 1, and a built-in component module and a manufacturing method thereof are proposed in Patent Document 2. In addition, Patent Document 3 proposes a printed wiring board with built-in electronic components. The multilayer substrate in Patent Document 1 includes a core substrate and a circuit substrate with an additional layer, and electronic components are embedded in the additional layer. In the case of manufacturing the multilayer substrate If, as shown in FIG. 13 (a), the electronic component 2 is mounted on the core substrate i, and as shown in (b) of the figure, an additional layer is formed on the mounting surface of the core substrate i and then increased. A copper wiring pattern 4 is formed on the surface of the layer 3. Secondly, as shown in FIG. 13 (0), a multi-layer substrate is manufactured by stacking an additional layer 5 on top of the additional layer 3. The more the substrate is formed with high-density wiring, the more the number of layers and the number of copper wiring patterns are stacked. In addition The built-in component module of Patent Document 2 has: an electrically insulating layer; first layers of wiring patterns stacked through the electrically insulating layers; and first through holes electrically connected between the first wiring patterns of different layers, respectively. ; And electronic parts buried inside 99412.doc 200540927 electrical insulation layer. In the case of manufacturing the built-in component module, as shown in Fig. 14 (b), 'produced separately: electrical insulation layer ia, which includes The first-wiring pattern 2A and the first-internal via 3A in a non-hardened state, a thermosetting resin; and an electrical insulating layer 1β, which has a first internal via 3B. In addition, as shown in FIG. There is a carrier 5A of the electronic component 4A. Then, the carrier is stacked from above and the non-hardened electrical insulating layers 1A, 1B are stacked to obtain a laminated body. Next, the laminated body is processed to make the electric insulating layer IA, 1B is heat hardened and removed by The built-in component module is obtained at 5A. In addition, the printed circuit board with built-in electronic components in Patent Document 3 is constructed by stacking several layers of substrates with an inner layer circuit. The conductor is not arranged on the peripheral wall, and a perforation is provided in the through hole. Those who arrange electronic components and connect to the inner layer circuit. In the case of printed wiring boards with built-in electronic components, a through-hole is cut out without a conductor on the peripheral wall, and electronic components are arranged in this through-hole, so that the printed wiring board can be flat ≫ Patent Document 1: Japanese Patent Application Laid-Open No. 2002-084071 Patent Document 2: Japanese Patent Application Laid-Open No. 2002-29005 Japanese Patent Publication No. 1: Japanese Patent Application Laid-Open No. 2003-168871 [Content of the Invention] However, a 'manufacturing patent' In the case of the multi-layer substrate of document i, after stacking the additional layer 3 which is thinner than the height of the electronic component 2 on the core substrate 1, in order to form the copper wiring pattern 4A ', it is necessary to immerse the laminated body in a slag-removing treatment solution, without electrolysis Electrolyte liquid, electrolytic plating liquid, etchant, etc. Therefore, each time the copper wiring pattern 4 is formed, the electronic component 1 is exposed to each of the above-mentioned processing liquids, which may cause electricity 99. 412.doc 200540927 The characteristics of sub-component 2 are deteriorated. In addition, in the case of manufacturing the built-in component module of Patent Document 2, because of the electrical insulation layer stacked on top of the electronic component 4 A and crimped in an unhardened state • 1A, 1B is on the carrier 5A. The uninsulated state of the electrically insulating layer ία, 1B is shown by the arrow in FIG. 14 (d), and is excluded to the surroundings by the electronic component 4A. The electrically insulating layers 1A, 1B contain conductive The first internal vias 3 A, 3B of the conductive via paste are bent and cause positional deviations, which may be between the first wiring pattern 2A and the first internal vias 3A, 3B and the first internal vias 3A '3B. In other words, a conduction failure occurs in the internal wiring of the substrate. In addition, when a printed wiring board with a built-in electronic component in Patent Document 3 is produced, a via hole reaching the electronic component disposed in the through-hole or a conductive film connected to the electronic component is formed in the via hole. In the same way, electronic components may be damaged by the intrusion of a processing liquid such as an etching solution and a plating solution. In order to solve the above-mentioned problems, an object of the present invention is to provide a composite electronic component which can prevent the deterioration of characteristics of built-in electronic components and poor conduction of internal wiring, improve reliability, and can achieve miniaturization and flatness, and Its manufacturing method. In addition, an object of the present invention is to provide a composite electronic device that can reliably prevent deterioration of characteristics of built-in electronic components and poor conduction of internal wiring, and improve reliability, and can realize a compact, flat IP, and high-functionality Parts and their manufacturing methods. Another object of the present invention is to provide a composite electronic component that can be transferred to a mounting substrate. The characteristics of the composite electronic parts of the applicants of the present invention are as follows: No. 99412.doc 200540927 A circuit board, which is installed with at least one electronic part; & A second circuit board, which has a through hole for accommodating the above electronic parts A hole, and in a state in which the electronic component is housed in the through hole, it is electrically connected to the first circuit substrate; the second circuit substrate has: an insulating layer stacked with several layers; Internal wiring conductor. In addition, the composite electronic part of claim 2 of the present invention is characterized in that:

上述電子零件之間隙之樹脂部。 此外，本發明之請求項3之複合型電子零件之特徵為· 於請求項1或2之發明中，上述面内配線導體形成於上述電 子零件之一方主面與另一方主面間之高度。 此外，本發明之請求項4之複合型電子零件之特徵為· 於請求項1〜3中任一項之發明中’在上述第-電路基板與 上述第二電路基板之間介有間隔物或樹脂層。 此外，本發明之請求項5之複合型電子零件之特徵為： 於吻求項4之發明中，上述間隔物或上述樹脂層具有電性 連接上述第一電路基板與上述第二電路基板之導體部。 此外本發明之請求項6之複合型電子零件之特徵為· 於叫求項2〜5中任-項之發明中，上述樹脂部覆蓋上述 子零件及第二電路基板之表面。 电 此外，本發明之請求項7之複合型電子零件之特徵為· 於請求項1〜6中任-項之發明中，上述第-電路基板係堆 疊數個絕緣層而構成之多層電路基板，並具有：形成於上 述絕緣層之一面之面内配線導體，及連接於該面内配線= 99412.doc -9- 200540927 體之導通孔導體。 =@本發明之請求項8之複合型電子零件之特徵為： 於“項w中任一項之發明中，上述第二電路基 連接於上述面内配線導體之導通孔導體。 一 此外，本發明之請求項9之複合型電子零件之 :::Γ中任一項之發明中’上述第二電心藏 曰日片型電子零件。The resin part of the gap of the electronic component. In addition, the composite electronic component of claim 3 of the present invention is characterized in that: In the invention of claim 1 or 2, the in-plane wiring conductor is formed at a height between one main surface and the other main surface of the electronic component. In addition, the feature of the composite electronic part of claim 4 of the present invention is that in the invention of any one of claims 1 to 3, 'a spacer or a spacer is interposed between the first circuit board and the second circuit board. Resin layer. In addition, the composite electronic component of claim 5 of the present invention is characterized in that: in the invention of claim 4, the spacer or the resin layer has a conductor electrically connecting the first circuit substrate and the second circuit substrate. unit. In addition, the composite electronic component of claim 6 of the present invention is characterized in that: in the invention called any one of claims 2 to 5, the resin portion covers the surface of the sub-component and the second circuit board. In addition, the composite electronic part of claim 7 of the present invention is characterized in that: In the invention of any of the claims 1 to 6, the first circuit board is a multilayer circuit board formed by stacking a plurality of insulating layers, And it has: an in-plane wiring conductor formed on one surface of the above-mentioned insulating layer, and a via-hole conductor connected to the in-plane wiring = 99412.doc -9-200540927. = @ The invention of claim 8 of the composite electronic part is characterized in that: In the invention of any of the "items w", the above-mentioned second circuit base is connected to the via-hole conductor of the in-plane wiring conductor.-In addition, this The composite electronic part of claim 9 of the invention: The invention of any one of the ::: Γ described above, wherein the second electric core is a Japanese-style electronic part.

此外，本發明之請求項10之複合型電子零件之特徵為： 於凊求項1〜9中任-項之發明中，上述第二電路基板内藏 膜元件。 肌 此外，本發明之請求項n之複合型電子零件之特徵為： 於請求項WO中任-項之發明中，上述第二電路基板係樹 脂基板。 此外，本發明之請求項12之複合型電子零件之製造方法 之特徵為具備以下步驟：進行至少搭載有丨個電子零件之 第一電路基板與具有收容上述電子零件之貫穿孔之第二電 路基板之對準，及以在上述貫穿孔内收容上述電子零件之 方式’貼合第一電路基板與第二電路基板。 此外’本發明之請求項13之複合型電子零件之製造方法 之特徵為：於請求項12之發明中，具備至少在與上述貫穿 孔内所形成之上述電子零件之間隙填充樹脂之步驟。 此外’本發明之請求項14之複合型電子零件之製造方法 之特徵為：於請求項12或13之發明中，具備在上述第一電 路基板上配置間隔物之步驟。 99412.doc 200540927 此外’本發明之請求項15之複合型電子零件之製造方法 之特徵為：於請求項14之發明中，上述間隔物具有電性導 通上述第一電路基板與上述第二電路基板之導體部。 此外’本發明之請求項16之複合型電子零件之製造方法 之特徵為：於請求項12或13之發明中，上述第二電路基板 在上述第一電路基板侧之面具有樹脂層。 此外’本發明之請求項17之複合型電子零件之製造方法 之特徵為·於請求項16之發明中，上述樹脂層具有電性導 通上述第一電路基板與上述第二電路基板之導體部。 此外’本發明之請求項18之複合型電子零件之製造方法 之特徵為：於請求項16或17之發明中，上述樹脂層包含未 硬化樹脂。 此外，本發明之請求項19之複合型電子零件之製造方法 之特徵為：於請求項13〜18中任一項之發明中，以上述樹 脂覆蓋上述電子零件及上述第二電路基板之表面。 此外，本發明之請求項2〇之複合型電子零件之製造方法 之特徵為：於請求項19之發明中，上述樹脂包含未硬化樹 脂。 此外，本發明請求項21之複合型電子零件之特徵為具 備第一電路基板，其係至少安裝有丨個電子零件·至少工 個第二電路基板，其係在該第—電路基板上與上述電子夕零 件並列安裝；及樹脂部，其係在上述第一電路基板上埋入 上述電子零件與上述第二電路基板之間隙；且上述第二電 路基板形成堆疊有數層絕緣層之疊層體，且至少内藏與上 99412.doc -11 · 200540927 述第一電路基板成為一體之電路圖案。 此外，本發明之請求項22之複合型電子零件之特徵為： 於請求項21之發明中，具有内藏晶片型電子零件之第三電 路基板。 此外，本發明之請求項23之複合型電子零件之特徵為： 於請求項21或22之發明中，在上述樹脂部之上面形成屏障 電極’並且在上述樹脂部内形成連接上述屏障電極與上述 第一電路基板之外部端子電極之導通孔導體。 此外，本發明之請求項24之複合型電子零件之特徵為： 於請求項21〜23中任一項之發明中，上述第二電路基板在 下面具有安裝用端子，在上面具有屏障連接用端子，上述 安裝用端子連接於上述第一電路基板上之外部端子電極， 並且上述屏障連接用端子經由上述樹脂部之導通孔導體而 連接於上述屏障電極。 此外，本發明之請求項25之複合型電子零件之製造方法 之特徵為具備以下步驟：在第一電路基板上分別安裝：至 少1個電子零件；及至少丨個第二電路基板，其係形成堆疊 有數層絕緣層之疊層體，且至少内藏與上述第一電路基板 成為一體之電路圖案；及在上述第一電路基板上，填充樹 脂於上述電子零件與上述第二電路基板之間隙。 此外’本發明之請求項26之複合型電子零件之製造方法 之特徵為：於請求項25之發明中，以上述樹脂覆蓋上述電 子零件及上述第二電路基板之表面。 此外’本發明之請求項27之複合型電子零件之特徵為具 99412.doc -12- 200540927 備：至少1個電子零件；至少丨個電路基板，其係與該電子 零件並列配置；及樹脂部，其係埋入上述電子零件與上述 電路基板之間隙，而將此等兩者予以一體化。 此外，本發明之請求項28之複合型電子零件之特徵為·· 於請求項27之發明中，具有内藏晶片型電子零件之電路基 板。 此外，本發明之請求項29之複合型電子零件之特徵為： 於請求項27或28之發明中，在上述樹脂部之上面形成屏障 電極，並且在上述樹脂部内形成連接上述屏障電極與上述 安裝用基板之導通孔導體。 此外，本發明之請求項30之複合型電子零件之特徵為： 於請求項27〜29中任一項之發明中，上述電路基板在下面 具有安裝用端子，並且在上面具有屏障連接用端子，上述 安裝用端子構成可連接於上述安裝用基板，並且上述屏障 連接用端子構成經由上述樹脂部之導通孔導體可連接於上 述屏障電極。 本發明之請求項1〜26之發明，可提供可確實防止電子零 件之特性惡化及内部配線之導通不良，而提高可靠性，並 且可實現小型化、扁平化及高功能化之複合型電子零件及 其製造方法。 此外’本發明之請求項27〜30之發明，可一併提供可確 實防止電子零件之特性惡化及内部配線之導通不良，而提 高可靠性，並且可實現小型化、扁平化及高功能化，且可 轉印至安裝用基板之複合型電子零件。 99412.doc -13- 200540927 【實施方式】 以下，依據圖1〜圖12所示之實施形態來說明本發明。另 外，圖1之（a)〜(c)分別係顯示本發明之複合型電子零件— 種實施形態之剖面圖，（a)係顯示全體之剖面圖，，⑷ 分別係放大顯示可適用於第二配線電路之一部分之電路圖 案之剖面圖，圖2係顯示用於圖1所示之複合型電子零件之 第一、第二電路基板之分解立體圖，圖3及圖4分別係顯示 圖1所示之複合型電子零件之製造步驟之說明圖，圖5係顯 示本發明之複合型電子零件其他實施形態之剖面圖，圖6 及圖7分別係顯示圖5所示之複合型電子零件之製造步驟之 說明圖，圖8之（a)〜(c)分別係顯示本發明另外實施形態之 複合型電子零件之製造步驟之說明圖，圖9之（a)〜(d)分別 係顯示本發明之複合型電子零件另外實施形態之圖，（a)係 顯不全體之剖面圖，（b)，（c)，（d)係分別放大顯示該圖之 (a)中所不之第二、第三及第四電路基板之剖面圖，圖之 (a)〜(e)分別係顯示圖9所示之複合型電子零件之製造步驟 之。兑月圖，圖11係顯示形成圖9所示之複合型電子零件之 樹脂部前之狀態之立體圖，圖12係顯示本發明之複合型電 子零件另外實施形態之圖，（a)係顯示複合型電子零件與支 撐體體化狀態之剖面圖，（b)係顯示複合型電子零件之剖 面圖。 第一種實施形態 如圖1之（a)所示，本實施形態之複合型電子零件1〇具 備：第一電路基板12，其係安裝有數個電子零件u ;及第 99412.doc •14- 200540927 二電路基板14，其係經由數處之間隔物13，而電性連接於 第一電路基板丨2之上面（安裝面）；第一電路基板12作為與 配置於各電子零件11間之空間之第二電路基板14一體化之 電路基板而構成，如安裝於母板（圖上未顯示）等來使用。 第二電路基板14之上面與高度最高之電子零件丨丨（圖i中全 部之電子零件11均形成相同高度）之上面，設定成自第一 電路基板12之安裝面相同高度。但是，電子零件u之上面 亦可比第二電路基板14之上面高或低。電子零件n如具 有·半導體積體電路元件等之主動晶片零件，及將疊層電 容器及疊層電感器等陶瓷燒結體作為素體之被動晶片零 件。此外，第一、第二電路基板12，14依目的，可藉由分 別具有特定之配線圖案之多層樹脂基板或多層陶瓷基板而 形成多層電路基板。 如圖1之（a)所示，第一電路基板12具備：堆疊有數層之 絕緣層12A ;面内配線導體12b，其係以特定之圖案形成 於各絕緣層12 A之表面；第一導通孔導體12C，其係電性 連接上下之面内配線導體12B間；第一及第二外部端子電 極12D ’ 12E，其係以特定之圖案形成於上下兩面；及第 二導通孔導體12F，其係電性連接於第二外部端子電極 12E ;並藉由面内配線導體12B、第一及第二導通孔導體 12C ’ 12F及第一及第二外部端子電極12D，12£構成特定 之配線圖案。第一電路基板12如上述雖可作為多層樹脂基 板或多層陶瓷基板之多層電路基板而構成，不過考慮彎曲 強度及成本面，宜為通用性高之印刷配線基板等之多層樹 99412.doc -15- 200540927 脂基板。 第一電路基板12為多層樹脂基板情況下，絕緣層12A宜 為藉由熱硬化性樹脂與無機填料之混合樹脂組成物而形成 者熱硬化性樹脂如可使用環氧樹脂、苯紛樹脂及cyanate 樹脂等’無機填料如可使用氧化鋁、二氧化矽、二氧化鈦 等。如此藉由添加無機填料，可提高第一電路基板12之散 熱性’此外，製造第一電路基板丨2時可適切控制樹脂之流 動性及填充性。電子零件丨丨安裝高頻用電子零件情況下， 絕緣層12A宜為介電常數低者。 面内配線導體12B及第一及第二外部端子電極12d，12E 如可應用光蝕刻技術及蝕刻技術，藉由將銅箔等金屬箔予 以圖案化而形成。此外，第一導通孔導體12C可藉由在形 成於絕緣層12A之導通孔内填充導電性膏而形成。導電性 膏係如包含金屬粒子與熱硬化性樹脂之導電性樹脂組成 物。金屬粒子如可使用金、銀、銅、鎳等金屬，熱硬化性 樹月曰如可使用環氧樹脂、苯紛樹脂及Cyanate樹脂等之樹 脂。此外，第二導通孔導體12F如可藉由無電解電鍍銅及 電解電鍍銅而形成。如此，第一電路基板12為多層樹脂基 板情況下，除配線圖案之外，可依目的内藏疊層電容器及 疊層電感器等被動晶片零件及/或半導體積體電路元件等 之主動晶片零件。 第一電路基板12為多層陶瓷基板情況下，絕緣層UA係 藉由陶瓷材料而形成。陶瓷材料宜為低溫燒結陶瓷 (LTCC : Low Temperature Co-fired Ceramic)材料。所謂低 99412.doc -16 - 200540927 溫燒結陶瓷材料，係指可以1050以下之溫度燒成之陶瓷 材料者。低溫燒結陶瓷材料如：在氧化鋁、鎂橄欖石及堇 青石等陶瓷粉末中混合硼矽酸系玻璃之玻璃複合系LTCC 材料，使用Zn0-Mg0-Al203_Si02系之結晶化玻璃之結晶化 玻璃系LTCC材料，及使用Ba0-Al203-Si02系陶瓷粉末及 Al203_Ca0-Si02-Mg0-B203系陶瓷粉末等之非玻璃系LTCC 材料等。藉由在多層陶瓷基板上使用低溫燒結陶瓷材料， 對於面内配線導體、外部端子電極及導通孔導體，可以使 用銀或銅等低電阻且具有低炼點之金屬，可以低溫與陶瓷 層同時燒成而予以一體化。如此，第一電路基板12為多層 陶瓷基板情況下，除配線圖案之外，可依目的内藏將陶瓷 燒結體作為素體之疊層電容器及疊層電感器等被動晶片零 件及電阻元件、電介質元件等之膜元件。該被動晶片零件 可使用包含以比多層陶瓷基板之燒成溫度高之燒成溫度而 燒結之陶瓷燒結體之素體。 如圖1之（a)及圖2所示，第二電路基板14係收容各電子零 件11，且具有數個貫穿孔14A，其係具有比各電子零件u 之平面尺寸大之開口面積之板狀基板，並如圖丨所示，在 第一電路基板12上面以埋入各電子零件丨丨間之空間之方式 配置。而後，在各貫穿孔14A之内周面與電子零件u之間 隙形成有起作用作為絕緣層之樹脂部15。該樹脂部15不但 在電子零件丨丨與第二電路基板14間之間隙，還埋入第一電 路基板12與第二電路基板14之間隙，並且亦覆蓋各電子零 件11與第二電路基板14之上面，密封並固定全部之電子零 99412.doc -17- 200540927 件11及第二電路基板14。此外，在樹脂部15之上面，藉由 銅箔等之金屬箔形成屏障電極16，藉由該屏障電極16自外 部遮蔽内部，避免受到來自外部之電磁性影響。屏障電極 16亦可藉由金屬之濺射、蒸鍵、無電解電鑛及電解電鍍等 而形成。另外，亦可在第二電路基板14上搭載上述之晶片 零件。 第二電路基板14與第一電路基板12同樣地，構成具備堆 疊之數層絕緣層MB、面内配線導體MC、導通孔導體14D 及第一及第二外部端子電極14E，14F之多層電路基板。面 内配線導體14C形成於數層絕緣層14B之適切的面内，配 置於各電子零件11之各個一方主面（上面）與另一方主面（下 面）間之咼度而形成，並有效利用各電子零件1 1間之間隙 來配置。第二電路基板14可由多層樹脂基板或多層陶曼基 板之多層電路基板構成。多層樹脂基板可藉由熱硬化性樹 脂與無機填料之混合樹脂組成物而形成。從防止因第一及 第二電路基板12，14間之熱膨脹率差而引起之剝離等之觀 點，此等兩者12, 14宜藉由同一種材料之多層基板構成。 但是’亦可由μ基板構成第—電路基板12，由樹脂基板 構成第二電路基板14。此種情況下，第一及第二電路基板 12，14間之熱膨脹率之差，可藉由樹脂部。（特別是由於 樹脂部含有無機填料，因此具有陶究基板之熱膨脹率與樹 脂基板之熱膨脹率間之熱膨脹率）來緩和。另外，第二電 路基板14包含形成有貫穿孔14Α之部分時，係形成與^ 電路基板12大致相同面積。 99412.doc -18· 200540927 第二電路基板14上，如圖1之（a)中以〇包圍之部分及其 他部分’依目的如圖1之（b)所示’除包含面内配線導體 14C及導通孔導體14D之配線圖案之外，還可内藏主動晶 片零件14G及被動晶片零件14H等之晶片型電子零件。與 此同樣地，除晶片型電子零件之外，如該圖之（c)所示，亦 可内藏電阻元件141及電介質元件14J等之膜元件。主動晶 片零件14G及被動晶片零件14H等之晶片型電子零件及膜 元件，依目的可適切組合而内藏於第二電路基板14内。 此外，如在第二電路基板14之上面，藉由銅箔等之導電 性薄膜形成接地電極，該接地電極經由樹脂部1 5内以特定 圖案配置之第三導通孔導體17而連接於屏障電極16。此 外，第三導通孔導體17可抑制或防止相鄰之各電子零件i j 之電磁性相互干擾，進一步可高密度安裝數個電子零件 11，可促進複合型電子零件1 〇之小型化。 此外，如圖1之（a)及圖2所示，第一及第二電路基板12， 14經由配置於數處之間隔物13電性連接，而一體化成一個 電路基板（電路模組）。數個間隔物13具有因第一及第二電 路基板12，14各個起伏等之凹凸，可能造成電性連接第一 電路基板12與第二電路基板14困難，而吸收此等起伏等造 成之凹凸，調整第二電路基板14之高度，並且確實電性連 接此等兩者12，14之功能。因此，數個間隔物13中，有僅 具有高度調整功能者，以及具有高度調整功能與電性連接 功能兩者。藉由間隔物13之高度調整功能，可使第二電路 基板14之上面與最高之電子零件丨丨上面平齊。 99412.doc -19- 200540927 上述之間隔物13如可藉由陶瓷、樹脂或金屬而形成圓柱 狀、角柱狀等各種形態。間隔物13為陶瓷製或樹脂製情況 下形成有上下貫穿間隔物13之導體部13A。為陶瓷製間 隔物情況下，藉由將導電性膏與陶瓷材料一起燒結而形 成，為樹脂製間隔物13情況下，藉由使導電性樹脂熱硬化 而升y成特別疋且採用樹脂製間隔物13，因其比陶究及金 屬較具有彈性，而容易吸收起伏等造成之凹凸。此外，金 屬製間隔物13，其本身形成導體部。 此外，在第二電路基板14與形成於貫穿孔14A内之電子 零件11之間隙中形成有樹脂部15。該樹脂部15如藉由熱硬 化|±樹爿曰與無機填料之混合樹脂組成物而形成。該樹脂部 15 /、/頁至、幵〉成於第二電路基板14之貫穿孔14 a内之間隙 即可。但是’本實施形態中，樹脂部丨5係以特定之厚度覆 蓋電子零件11及第二電路基板14之各個上面，來完全密封 電子零件11及第二電路基板14。 本實施形態中使用之銅箔，其樹脂部側之面分別予以粗 面化。粗面化處理如採用矽烷耦合處理、準分子光照射處 理、電暈放電處理及黑化處理等。藉由此種粗面化處理提 供錯固效應’銅箔與樹脂部強固地密合，而不易自樹脂部 剝離。 如以上之說明，由於本實施形態之複合型電子零件1〇具 備·第一電路基板12，其係安裝有數個電子零件丨丨；及第 二電路基板14，其係具有數個貫穿孔14A，且在此等貫穿 孔14A中分別收容有各電子零件丨丨狀態下與第一電路基板 99412.doc -20- 200540927 12電性連接；第二電路基板14具有··堆疊之數層絕緣層 14B，及形成於絕緣層14B之一面之面内配線導體，因 此可由第一電路基板12，與在各電子零件丨丨間之空間内藏 配線圖案、主動晶片零件14G及被動晶片零件14H或電阻 元件141及電介質元件14J等之膜元件等之晶片型電子零件 而配置之第二電路基板14構成一個電路基板，可有效利用 各電子零件11間之空間，並且可實現無導通不良之高密度 配線及高功能化，進一步可促進複合型電子零件1〇之小型 化及扁平化。此外，由於第一及第二電路基板12 , 14可使 用通用之印刷配線基板，因此可以低成本製造複合型電子 零件10。 此外，本實施形態之複合型電子零件丨0由於在第二電路 基板14之各貫穿孔14A内具備形成於與電子零件u之間隙 之樹脂部15，因此可藉由樹脂部15確實密封第一電路基板 12上各電子零件11與第二電路基板丨4之間隙，可提高複合 型電子零件1 0之可靠性。再者，藉由亦以樹脂部丨5覆蓋各 電子零件11及第一電路基板14之表面，可完全密封各電子 零件11及第二電路基板14，因而可獲得可靠性高之複合型 電子零件。此外，由於第二電路基板14之面内配線導體 14C形成於數層絕緣層14B之適切面内，並位於各電子零 件11之各個上面與下面間之高度而形成，因此可有效利用 各電子零件11間之間隙作為配線圖案之設置空間。由於在 第一電路基板12與弟二電路基板14之間介有間隔物η，因 此藉由間隔物13吸收第一及第二電路基板12, 14之各個起 99412.doc -21 - 200540927 伏等造成之凹凸，可精確度佳的確實貼合此等兩者12, 14。再者’由於間隔物I〕具有導體部BA，因此可確實電 性連接第一及第二電路基板12，14。 其次，參照圖2〜圖4，且僅在主要部分註記符號，來說 明圖1之（a)所示之複合型電子零件之製造方法一種實施形 態。 首先’如圖3之（a)所示，預先準備以多層樹脂基板製作 之第一電路基板12。在該第一電路基板丨2之上面，以特定 之圖案形成第一外部端子電極12D ,在其下面貼合形成第 二外部端子電極12E用之銅箔12Έ。對準該第一電路基板 12上面之第一外部端子電極12D之特定位置，如該圖所 不，分別安裝數個電子零件11，並且固定數個間隔物13。 電子零件11及間隔物13可經由導電性樹脂或焊錫膏等而安 裝於第一電路基板12上。 其次’如圖3之（b)所示，對準第一電路基板12與預先以 多層樹脂基板製作之第二電路基板14,在第一電路基板12 之上方’以第二電路基板14之貫穿孔14A位於電子零件11 之正上方之方式配置第二電路基板14後，第一及第二電路 基板12，14彼此以特定之壓力，如該圖之（c)所示地經由各 間隔物13貼合。藉此，第一電路基板12上之各電子零件^ 收納於第二電路基板14之各貫穿孔14Α内。此時，第一及 第二電路基板12，14經由間隔物π之導體部13Α而確實電 性連接。此外，由於第一及第二電路基板12 , 14中預先形 成有導通孔導體，因此，亦不致因此等導通孔導體之變形 99412.doc -22- 200540927 而產生連接不良。 其次，如圖3之（d)所示地，使樹脂部15,在下側，而將預 先準備之具有未硬化狀態（B階段）之樹脂部15,之銅箔16,配 置於第一電路基板12之上方後，在第一電路基板12上堆 疊、壓接時，樹脂流動而埋入第二電路基板14之各貫穿孔 14A内之間隙等，並且覆蓋各電子零件丨丨及第二電路基板 14之上面，而如該圖之（e)所示地形成未硬化狀態之樹脂部 1 5 ’。而後’以比其熱硬化溫度高之溫度來熱處理樹脂部 1 5’ ’使樹脂部15硬化時，即可獲得複合型電子零件丨〇之半 成品10’。 然後’藉由在圖3之（e)所示之半成品10,之上下兩面，分 別以特定之圖案實施蝕刻處理，在銅箔12Έ，16，上設置開 口部O’而如圖4之（a)所示地形成第二外部端子電極12Ε及 屏障電極16。其次，如圖4之（b)所示，照射雷射光，自各 開口部Ο，在第一電路基板12及樹脂部15内形成導通孔H 後，如圖4之（c)所示，藉由實施無電解銅電鍍及電解銅電 鍍，在導通孔Η内形成第二及第三導通孔導體12F，17，即 可獲得複合型電子零件1 〇。 如以上之就明，由於本實施形態具備以下步驟··對準搭 載有數個電子零件u之第—電路基板12，及具有對應於數 個電子零件11之數個貫穿孔14A之第二電路基板14 ;及將 各電子零件11收容於各個貫穿孔14A中，來貼合第一電路 基板12與第二電路基板14;因此準備預先製作之第一及第 二電路基㈣’ 14’僅將第二電路基板14在第—電路基板 99412.doc -23- 200540927 12上對準，即可有效利用第一電路基板12上之電子零件U 1門隙構成一個電路基板，而實現無導通不良之高密 度配線與高功能化，進一步可以低成本促進複合型電子零 件10之小型化及扁平化。此外，由於僅貼合第一及第二電 路基板12，14即可構成一個電路基板，因此可確實防止電 子零件之特性惡化。 此外’由於本實施形態在與各貫穿孔14A内所形成之各 個電子零件11之間隙中填充未硬化狀態之混合樹脂組成 物，來密封各電子零件n及第二電路基板14，因此可藉由 樹脂部15確實保護電子零件^與第二電路基板14，避免受 到外#環境影響’可提高複合型電子零件10之可靠性。此 外’由於具備在第一電路基板12上配置間隔物13之步驟， 因此可確實吸收第一及第二電路基板12，14間之凹凸，來 调整兩者間之間隔，可確實貼合第一電路基板12與第二電 路基板14，且由於間隔物13具有導體部13A，因此，可確 實電性連接第一電路基板12與第二電路基板14。 第二種實施形態 本實施形態如圖5所示，亦可在第二電路基板14之下面 塗敷樹脂層23，來取代上述實施形態之間隔物13。圖5所 示之複合型電子零件10A，除形成於第二電路基板14下面 之樹脂層23之外，具有與圖1及圖2所示之複合型電子零件 1 〇相同之構造，因此在與上述實施形態相同或相當部分註 記相同符號，而省略相同部分之說明。由於形成於第二電 路基板14下面之樹脂層23具有彈性，因此可吸收第一及第 99412.doc -24- 200540927 二電路基板12，14之起伏及凹凸，可確實貼合此等兩者 12，14。該樹脂層23與第二電路基板14之絕緣層14B同樣 地，如可藉由熱硬化性樹脂或熱硬化性樹脂與無機填料之 混合樹脂組成物而形成。該樹脂層23之情況亦如該圖所 示，係在電性連接第一及第二電路基板12，14之部分形成 有導體部23A。該導體部23A可藉由導電性樹脂形成。此 外’本實施形態中亦與上述實施形態同樣地，可在第二電 路基板14中内藏主動晶片零件及被動晶片零件等晶片型電 子零件及膜元件，不過圖上並未顯示。 其次，參照圖6及圖7，並僅在主要部分註記符號來說明 圖5所示之複合型電子零件1〇人之製造方法一種實施形態。 本實施形態之複合型電子零件10A係使用塗敷於第二電路 基板14下面之樹脂層23來取代上述實施形態之間隔物13 , 其他可以與上述實施形態相同之施工方法製造。 亦即，如圖6之（a)所示，在第一電路基板12之第一外部 端子電極12D之特定位置安裝數個電子零件η。其次，如 圖6之（b)所示，對準形成有樹脂層23之第二電路基板14與 第一電路基板12後，第一及第二電路基板12，14彼此以特 定之壓力，如該圖之（c)所示地經由樹脂層23而貼合。藉 此’第一電路基板12上之各電子零件11收納於第二電路基 板14之各貫穿孔14A内。此時，第一及第二電路基板12, 14可藉由樹脂層23之導體部23A確實電性連接。 其次’如圖6之（d)所示，將具有樹脂部15,之銅箔16,配置 於第一電路基板12之上方後，堆疊、壓接於第一電路基板 99412.doc -25- 200540927 12上，埋入第二電路基板14之各貫穿孔14A内之間隙等， 並且覆蓋各電子零件11及第二電路基板14之上面，如該圖 之（e)所示，形成未硬化狀態之樹脂部15,後，使樹脂部 硬化時，獲得複合型電子零件10A之半成品l〇，A。 然後，藉由在圖6之（e)所示之半成品1〇，A之上下兩面之 銅箔12Έ，16’上，如圖7之（a)所示地設置開口部〇，形成 第二外部端子電極12E及屏障電極16。而後，如該圖之（b) 所示，照射雷射光，自各開口部〇，在第一電路基板12及 樹脂部15内形成導通孔Η，如該圖之（c)所示，藉由實施無 電解銅電鍍及電解銅電鍍，在導通孔Η内形成第二及第三 導通孔導體12F，17，即可獲得複合型電子零件1〇Α。因 此，本實施形態除可期待獲得與上述實施形態相同之作用 效果之外，由於在第一電路基板12與第二電路基板14之間 介有樹脂層23，因此可藉由樹脂層23吸收第一及第二電路 基板12，14之各個起伏等之凹凸，而精確度佳的確實貼合 此等兩者12，14。再者，由於樹脂層23具有導體部23a， 因此可確實電性連接第一及第二電路基板12, 14。 第三種實施形態 上述各實施形態係提及可在第一及第二電路基板12 , 14 中内藏主動晶片零件及被動晶片零件等晶片型電子零件， 不過本實施形態如圖8所示，係說明第一電路基板12内藏 電阻元件及電介質元件等膜元件，而第二電路基板14内藏 主動晶片零件及被動晶片零件等晶片型電子零件之複合型 電子零件10B。本實施形態之複合型電子零件丨〇B除第一 99412.doc -26- 200540927 及第二電路基板12，14内藏晶片型電子零件及膜元件之 外’準上述各實施形態而構成，因此省略與上述各實施形 ，態相同或相當部分之說明，而以本實施形態之特徵為主來 • 說明。因此，本實施形態中，第一及第二電路基板12，14 亦與上述各實施形態同樣地可形成包含多層樹脂基板及多 層陶瓷基板之多層電路基板。 用於本實施形態之第一電路基板12，如圖8之（a)所示， 除以内藏數個電阻元件、電介質元件等膜元件12〇及將疊 B 層電容器及疊層電感器等陶瓷燒結體作為素體之被動晶片 零件（圖上未顯示）之多層陶瓷基板形成之外，準上述各實 施形態而構成。數個膜元件12G連接於各個特定位置之面 内配線導體12B，12B間。藉由在第一電路基板内内藏 膜元件12G及被動晶片零件（圖上未顯示），在第一電路基 板12之安裝面上確保安裝主動晶片零件等電子零件u之空 間’並且可促進此等本身之高功能化，且可實現第一電路 g 基板12之扁平化。 第二電路基板14如與圖2所示者同樣地，形成具有貫穿 孔14A之多層樹脂基板。再者第二電路基板14如圖8之（幻 所示，内藏主動晶片零件（圖上未顯示）及被動晶片零件 14H等晶片型電子零件，各晶片型電子零件分別連接於配 置於同一個面内之面内配線導體14C及上下配置之面内配 •、線導體14C。第二電路基板14除晶片型電子零件之外，亦 可同時内藏晶片型電子零件及雷阳士从 也丁令1干次電阻件、電介質元件等膜 元件’不過圖上並未顯示。 99412.doc -27- 200540927 此外，第二電路基板14如可區分成：下部層141，其係 包含：最下段之導通孔導體14D，及包含此之絕緣層 14B ;及上部層142，其係包含：在此等上方之面内配線導 體14C，導通孔導體14D，及包含主動晶片零件（圖上未顯 示）及被動晶片零件14H等之晶片型電子零件之絕緣層 14B。下部層141宜在將第二電路基板14安裝於第一電路基 板12時，貼合於上部層142之下面而形成。形成下部層141 及上部層142之絕緣層14B均包含熱硬化性樹脂與無機填料 之混合樹脂組成物，貼合時之下部層141係半硬化狀態（B 階段）。由於第二電路基板14之下部層141係形成樹脂層， 因此可期待與第二種實施形態相同之作用效果。另外，貫 穿孔14A在貼合下部層141與上部層142後，可貫穿須成為 貫穿孔14A之位置而形成。 製造本實施形態之複合型電子零件10B情況下，如圖8之 (a)所示，係在第一電路基板12之第一外部端子電極12d之 特定位置安裝數個電子零件11。其次如該圖之（a)所示，對 準貼合有下部層141之第二電路基板14之貫穿孔14A與第一 電路基板12之電子零件11後，如該圖之（b)所示，以特定之 壓力壓接第一及第二電路基板12, 14。藉此，第一電路基 板12上之各電子零件11收納於第二電路基板μ之各貫穿孔 14A内。此時，第一及第二電路基板12，14可經由第二電 路基板14之下部層141之導通孔導體14D確實電性連接。 其次，與上述各實施形態同樣地，使樹脂部在下側，而 在第一電路基板12上堆疊、壓接具有未硬化狀態（B階段） 99412.doc 28· 200540927 之樹脂部之銅箔後，使樹脂部1 5硬化，以銅箔形成屏障電 極16,再者，自第二電路基板丨4之上面以特定之圖案形成 導通孔後，實施無電解銅電鍍及電解銅電鍍，藉由於導通 孔内形成第三導通孔導體17，可獲得複合型電子零件 10B。圖8之（c)中，電子零件u距第一電路基板12之安裝 面（上面）之ν度比第^一電路基板14高，不過亦可電子零件 11之南度與第二電路基板14之高度均高。另外，本實施形 態係在第二電路基板14上設置具有導通孔導體14D之下部 層141，並經由導通孔導體14D而電性連接第二電路基板14 與第一電路基板12，不過與第一種實施形態同樣地，亦可 介有間隔物，來取代下部層141之導通孔導體14D。 本實施形態由於在第一電路基板12中内藏有被動晶片零 件12G’並且在其上面安裝電子零件11，此外在第二電路 基板14中内藏有主動晶片零件（圖上未顯示）及被動晶片零 件14H等之晶片型電子零件，因此可有效利用形成於電子 零件11旁之空間，除配線圖案之外，亦可作為配置主動晶 片零件（圖上未顯示）及被動晶片零件14H等之晶片型電子 零件及膜元件等用之空間，可進一步促進複合型電子零件 10B之小型化、扁平化及高功能化。 第四種實施形態 此外，圖9係顯示本發明之複合型電子零件另外實施形 態之圖。本實施形態之複合型電子零件5〇，除將上述各實 施形態之第二電路基板依功能分割成數個之外，準上述各 實施形態而構成。由於本實施形態係將分割之數個電路基 99412.doc -29- 200540927 板個別地安裝於第一電路基板上，因此不需要上述各實施 形態中之間隔物。因此，本實施形態之複合型電子零件 除以下說明之部分外，與上述各實施形態同樣地構成。In addition, the composite electronic component of claim 10 of the present invention is characterized in that: in the invention of any one of claims 1 to 9, the above-mentioned second circuit board has a film element built therein. In addition, the composite electronic part of claim n of the present invention is characterized in that: In the invention of any one of the claim WO, the second circuit board is a resin board. In addition, the method for manufacturing a composite electronic component according to claim 12 of the present invention is characterized by having the following steps: performing a first circuit substrate on which at least one electronic component is mounted and a second circuit substrate having a through hole that houses the electronic component. Align, and affix the first circuit substrate and the second circuit substrate in such a manner that the electronic components are housed in the through-holes. In addition, the method of manufacturing a composite electronic part according to claim 13 of the present invention is characterized in that the invention of claim 12 includes a step of filling a resin with at least a gap between the electronic part and the electronic part formed in the through hole. In addition, the method of manufacturing a composite electronic component according to claim 14 of the present invention is characterized in that the invention of claim 12 or 13 includes a step of disposing a spacer on the first circuit board. 99412. doc 200540927 In addition, the method of manufacturing a composite electronic part according to claim 15 of the present invention is characterized in that: in the invention of claim 14, the spacer has a conductor for electrically conducting the first circuit substrate and the second circuit substrate. unit. In addition, the method of manufacturing a composite electronic component according to claim 16 of the present invention is characterized in that, in the invention of claim 12 or 13, the second circuit board has a resin layer on a surface of the first circuit board side. Further, the method of manufacturing a composite electronic component according to claim 17 of the present invention is characterized in that: in the invention of claim 16, the resin layer has a conductor portion that electrically connects the first circuit substrate and the second circuit substrate. In addition, the method of manufacturing a composite electronic part according to claim 18 of the present invention is characterized in that, in the invention of claim 16 or 17, the resin layer contains an uncured resin. In addition, the method for manufacturing a composite electronic component according to claim 19 of the present invention is characterized in that, in the invention of any one of claims 13 to 18, the surface of the electronic component and the second circuit board is covered with the resin. In addition, the method for manufacturing a composite electronic part according to claim 20 of the present invention is characterized in that in the invention of claim 19, the resin includes an uncured resin. In addition, the composite electronic component of claim 21 of the present invention is characterized by having a first circuit substrate, which is mounted with at least one electronic component, and at least two second circuit substrates, which are provided on the first circuit substrate with the above-mentioned Electronic components are installed side by side; and a resin part is embedded in the gap between the electronic component and the second circuit substrate on the first circuit substrate; and the second circuit substrate forms a laminated body in which several insulating layers are stacked, And at least built in and on 99412. doc -11 · 200540927 describes a circuit pattern in which the first circuit substrate is integrated. In addition, the composite electronic component of claim 22 of the present invention is characterized in that, in the invention of claim 21, a third circuit board having a wafer-type electronic component is incorporated. In addition, the composite electronic component of claim 23 of the present invention is characterized in that: in the invention of claim 21 or 22, a barrier electrode is formed on the resin portion, and a connection between the barrier electrode and the first electrode is formed in the resin portion. A via conductor of an external terminal electrode of a circuit substrate. The composite electronic component of claim 24 of the present invention is characterized in that: in the invention of any one of claims 21 to 23, the second circuit board has a mounting terminal on a lower surface and a barrier connection terminal on the upper surface. The mounting terminal is connected to an external terminal electrode on the first circuit board, and the barrier connection terminal is connected to the barrier electrode via a via-hole conductor in the resin portion. In addition, the method for manufacturing a composite electronic component according to claim 25 of the present invention is characterized by having the following steps: mounting on the first circuit substrate separately: at least one electronic component; and at least one second circuit substrate, which are formed A laminated body with several insulating layers stacked and at least a circuit pattern integrated with the first circuit substrate is embedded; and the gap between the electronic component and the second circuit substrate is filled with resin on the first circuit substrate. Further, the method of manufacturing a composite electronic part according to claim 26 of the present invention is characterized in that, in the invention of claim 25, the surface of the electronic component and the second circuit board is covered with the resin. In addition, the feature of the composite electronic part of claim 27 of the present invention is 99412. doc -12- 200540927 Preparation: at least 1 electronic part; at least 丨 circuit board, which is arranged side by side with the electronic part; and resin part, which is embedded in the gap between the electronic part and the circuit board, and so on The two are integrated. In addition, the composite electronic part of claim 28 of the present invention is characterized in that the invention of claim 27 has a circuit board having a built-in wafer-type electronic part. In addition, the composite electronic part of claim 29 of the present invention is characterized in that: in the invention of claim 27 or 28, a barrier electrode is formed on the resin portion, and a connection between the barrier electrode and the mounting is formed in the resin portion. Use the via conductor of the substrate. In addition, the composite electronic component of claim 30 of the present invention is characterized in that: in the invention of any one of claims 27 to 29, the circuit board has a terminal for mounting on the lower side and a terminal for barrier connection on the upper side, The mounting terminal configuration is connectable to the mounting substrate, and the barrier connection terminal configuration is connectable to the barrier electrode via a via hole conductor of the resin portion. The inventions of claims 1 to 26 of the present invention can provide a composite electronic part that can surely prevent the deterioration of the characteristics of electronic parts and poor conduction of internal wiring, improve reliability, and can achieve miniaturization, flatness and high functionality. And its manufacturing method. In addition, the invention of claims 27 to 30 of the present invention can also provide a combination that can reliably prevent the deterioration of the characteristics of electronic parts and the poor conduction of internal wiring, improve reliability, and can achieve miniaturization, flatness and high functionality. And it can be transferred to a composite electronic component of a mounting substrate. 99412. doc -13- 200540927 [Embodiment] Hereinafter, the present invention will be described with reference to the embodiments shown in Figs. 1 to 12. In addition, (a) to (c) of FIG. 1 are cross-sectional views showing a composite electronic component of the present invention, an embodiment, respectively, (a) is a cross-sectional view showing the whole, and ⑷ is an enlarged display applicable to the first A sectional view of a circuit pattern of a part of a two-wiring circuit. FIG. 2 is an exploded perspective view of the first and second circuit substrates used in the composite electronic part shown in FIG. 1, and FIGS. 3 and 4 are shown in FIG. 1 respectively. 5 is a cross-sectional view showing another embodiment of the composite electronic part of the present invention, and FIG. 6 and FIG. 7 respectively show the manufacturing of the composite electronic part shown in FIG. 5 An explanatory diagram of the steps, (a) to (c) of FIG. 8 are explanatory diagrams showing the manufacturing steps of the composite electronic part of another embodiment of the present invention, and (a) to (d) of FIG. 9 are respectively illustrating the present invention. (A) is a cross-sectional view showing the whole, and (b), (c), (d) are enlarged views showing the second, Sectional views of the third and fourth circuit substrates, respectively (a) to (e) Showing manufacturing steps of the composite electronic part 9 as shown. Moon chart, FIG. 11 is a perspective view showing a state before the resin part of the composite electronic part shown in FIG. 9 is shown, FIG. 12 is a view showing another embodiment of the composite electronic part of the present invention, (a) is a composite view (B) is a cross-sectional view of a composite electronic part. First Embodiment As shown in FIG. 1 (a), the composite electronic component 10 of this embodiment is provided with: a first circuit substrate 12, which is mounted with a plurality of electronic components u; and No. 99412. doc • 14- 200540927 Two circuit substrates 14 are electrically connected to the first circuit substrate 2 (mounting surface) through the spacers 13 at several places; the first circuit substrate 12 is arranged and arranged on each electronic part The second circuit board 14 with a space of 11 is formed by an integrated circuit board, such as being mounted on a motherboard (not shown in the figure) and used. The upper surface of the second circuit substrate 14 and the uppermost electronic component (all the electronic components 11 in Fig. I all have the same height) are set to the same height from the mounting surface of the first circuit substrate 12. However, the upper surface of the electronic component u may be higher or lower than the upper surface of the second circuit board 14. The electronic parts n include active chip parts including semiconductor integrated circuit elements, and passive chip parts using ceramic sintered bodies such as laminated capacitors and laminated inductors as element bodies. In addition, the first and second circuit substrates 12, 14 can be formed into a multilayer circuit substrate by a multilayer resin substrate or a multilayer ceramic substrate having a specific wiring pattern, depending on the purpose. As shown in FIG. 1 (a), the first circuit substrate 12 includes: an insulating layer 12A stacked with several layers; an in-plane wiring conductor 12b formed on a surface of each insulating layer 12A in a specific pattern; and first conduction The hole conductor 12C is electrically connected between the upper and lower in-plane wiring conductors 12B; the first and second external terminal electrodes 12D '12E are formed on the upper and lower sides in a specific pattern; and the second via hole conductor 12F is It is electrically connected to the second external terminal electrode 12E; and a specific wiring pattern is formed by the in-plane wiring conductor 12B, the first and second via hole conductors 12C '12F, and the first and second external terminal electrodes 12D, 12 £. . Although the first circuit substrate 12 can be configured as a multilayer circuit substrate of a multilayer resin substrate or a multilayer ceramic substrate as described above, considering the bending strength and cost, it is preferably a multilayer tree such as a printed wiring substrate with high versatility 99412. doc -15- 200540927 grease substrate. When the first circuit substrate 12 is a multilayer resin substrate, the insulating layer 12A is preferably formed by a mixed resin composition of a thermosetting resin and an inorganic filler. A thermosetting resin such as epoxy resin, benzene resin, and cyanate can be used. As the 'inorganic filler' such as resin, alumina, silicon dioxide, titanium dioxide, and the like can be used. By adding the inorganic filler in this way, the heat dissipation property of the first circuit board 12 can be improved. In addition, when the first circuit board 2 is manufactured, the flowability and filling property of the resin can be appropriately controlled. Electronic parts 丨 In the case of mounting high frequency electronic parts, the insulating layer 12A should be the one with the lower dielectric constant. The in-plane wiring conductor 12B and the first and second external terminal electrodes 12d and 12E can be formed by patterning a metal foil such as a copper foil by applying a photo-etching technique and an etching technique. The first via-hole conductor 12C can be formed by filling a conductive paste in a via-hole formed in the insulating layer 12A. The conductive paste is, for example, a conductive resin composition containing metal particles and a thermosetting resin. For metal particles, metals such as gold, silver, copper, and nickel can be used, and thermosetting resins such as epoxy resin, benzene resin, and Cyanate resin can be used. The second via-hole conductor 12F can be formed by, for example, electroless copper plating and electrolytic copper plating. In this way, when the first circuit substrate 12 is a multilayer resin substrate, in addition to the wiring pattern, passive chip parts such as laminated capacitors and laminated inductors and / or active chip parts such as semiconductor integrated circuit elements can be built in according to the purpose. . When the first circuit substrate 12 is a multilayer ceramic substrate, the insulating layer UA is formed of a ceramic material. The ceramic material is preferably a Low Temperature Co-fired Ceramic (LTCC) material. So-called low 99412. doc -16-200540927 Warm-sintered ceramic materials refer to ceramic materials that can be fired at temperatures below 1050. Low-temperature sintered ceramic materials such as glass composite LTCC materials in which borosilicate glass is mixed with ceramic powders such as alumina, forsterite and cordierite, and crystalline glass LTCC using Zn0-Mg0-Al203_Si02 crystallized glass Materials, and non-glass LTCC materials using Ba0-Al203-Si02-based ceramic powder and Al203_Ca0-Si02-Mg0-B203-based ceramic powder. By using a low-temperature sintered ceramic material on a multilayer ceramic substrate, for in-plane wiring conductors, external terminal electrodes, and via-hole conductors, low-resistance metals such as silver or copper with low refining point can be used, and the ceramic layer can be fired simultaneously at low temperatures. Success and integration. In this way, when the first circuit substrate 12 is a multilayer ceramic substrate, in addition to the wiring pattern, passive chip components such as multilayer capacitors and multilayer inductors using ceramic sintered bodies as element bodies, resistor elements, and dielectrics can be built in according to the purpose. Elements such as film elements. As the passive wafer component, a body including a ceramic sintered body sintered at a firing temperature higher than the firing temperature of the multilayer ceramic substrate can be used. As shown in FIGS. 1 (a) and 2, the second circuit board 14 houses each electronic component 11 and has a plurality of through holes 14A, which are plates having an opening area larger than the planar size of each electronic component u. As shown in FIG. 丨, the substrate is arranged on the first circuit substrate 12 so as to embed a space between the electronic components. Then, a resin portion 15 serving as an insulating layer is formed in the gap between the inner peripheral surface of each of the through holes 14A and the electronic component u. The resin portion 15 not only covers the gap between the electronic component and the second circuit substrate 14, but also embeds the gap between the first circuit substrate 12 and the second circuit substrate 14, and also covers each of the electronic components 11 and the second circuit substrate 14. Above, seal and fix all electronic zero 99412. doc -17- 200540927 Part 11 and second circuit board 14. In addition, a barrier electrode 16 is formed on the resin portion 15 by a metal foil such as a copper foil, and the inside of the barrier electrode 16 is shielded from the outside by the barrier electrode 16 to prevent electromagnetic influence from the outside. The barrier electrode 16 may also be formed by sputtering of a metal, vapor bonding, electroless ore, electrolytic plating, and the like. In addition, the above-mentioned wafer components may be mounted on the second circuit board 14. Like the first circuit substrate 12, the second circuit substrate 14 constitutes a multilayer circuit substrate including a plurality of stacked insulating layers MB, in-plane wiring conductors MC, via conductors 14D, and first and second external terminal electrodes 14E, 14F. . The in-plane wiring conductor 14C is formed in the appropriate plane of several insulating layers 14B, and is formed by being arranged at a degree between one main surface (upper surface) and the other main surface (lower surface) of each electronic component 11 and is effectively used. The electronic components 11 are arranged with a gap therebetween. The second circuit substrate 14 may be composed of a multilayer resin substrate or a multilayer circuit substrate of a multilayer ceramic substrate. The multilayer resin substrate can be formed from a mixed resin composition of a thermosetting resin and an inorganic filler. From the viewpoint of preventing peeling and the like caused by the difference in thermal expansion coefficient between the first and second circuit substrates 12, 14, these two 12, 14 should preferably be composed of a multilayer substrate of the same material. However, 'the first circuit substrate 12 may be constituted by a µ substrate, and the second circuit substrate 14 may be constituted by a resin substrate. In this case, the difference in the coefficient of thermal expansion between the first and second circuit boards 12, 14 can be passed through the resin portion. (Especially because the resin part contains an inorganic filler, it has a thermal expansion coefficient between the thermal expansion coefficient of the ceramic substrate and the thermal expansion coefficient of the resin substrate.) When the second circuit substrate 14 includes a portion where the through-hole 14A is formed, the second circuit substrate 14 is formed to have substantially the same area as the circuit substrate 12. 99412. doc -18 · 200540927 On the second circuit substrate 14, the part surrounded by 0 and other parts as shown in FIG. 1 (a) are shown in FIG. 1 (b) according to the purpose, except that the in-plane wiring conductor 14C and the conduction are included. In addition to the wiring pattern of the hole conductor 14D, chip-type electronic components such as the active chip component 14G and the passive chip component 14H can be built in. Similarly to this, in addition to the wafer-type electronic components, as shown in (c) of the figure, film elements such as a resistance element 141 and a dielectric element 14J may be incorporated. The wafer-type electronic parts and membrane elements such as the active wafer part 14G and the passive wafer part 14H can be appropriately combined and built in the second circuit substrate 14 according to the purpose. In addition, if the ground electrode is formed on the second circuit substrate 14 by a conductive film such as a copper foil, the ground electrode is connected to the barrier electrode via a third via hole conductor 17 arranged in a specific pattern in the resin portion 15. 16. In addition, the third via-hole conductor 17 can suppress or prevent the electromagnetic interference of adjacent electronic parts i j from interfering with each other, and can further mount several electronic parts 11 at high density, which can promote the miniaturization of the composite electronic part 10. In addition, as shown in (a) of FIG. 1 and FIG. 2, the first and second circuit substrates 12 and 14 are electrically connected to each other via spacers 13 disposed at a plurality of locations, and are integrated into one circuit substrate (circuit module). The spacers 13 have irregularities caused by the undulations of the first and second circuit substrates 12 and 14, which may make it difficult to electrically connect the first circuit substrate 12 and the second circuit substrate 14, and absorb the irregularities caused by the undulations. , Adjust the height of the second circuit substrate 14 and surely electrically connect these two functions 12, 14. Therefore, among the plurality of spacers 13, there are only those having a height adjustment function, and those having both a height adjustment function and an electrical connection function. With the height adjustment function of the spacer 13, the upper surface of the second circuit substrate 14 can be flush with the uppermost electronic component. 99412. doc -19- 200540927 The spacer 13 described above can be formed into various shapes such as a columnar shape and a corner column shape by using ceramic, resin, or metal. When the spacer 13 is made of ceramic or resin, a conductor portion 13A penetrating the spacer 13 is formed. In the case of a ceramic spacer, it is formed by sintering a conductive paste together with a ceramic material. In the case of a resin spacer 13, the conductive resin is thermally hardened to raise y to a particularly high temperature. The resin spacer is used. Object 13, because it is more elastic than ceramics and metal, can easily absorb unevenness caused by undulations. The metal spacer 13 itself forms a conductor portion. A resin portion 15 is formed in a gap between the second circuit board 14 and the electronic component 11 formed in the through hole 14A. The resin portion 15 is formed by, for example, thermally hardening a resin composition of a mixed resin composition with an inorganic filler. The resin portion 15 /, / page to, 幵> may be formed in a gap in the through hole 14 a of the second circuit substrate 14. However, in this embodiment, the resin part 5 covers the upper surfaces of the electronic component 11 and the second circuit substrate 14 with a specific thickness to completely seal the electronic component 11 and the second circuit substrate 14. The copper foil used in this embodiment has a roughened surface on the resin portion side. Roughening treatments include silane coupling treatment, excimer light irradiation treatment, corona discharge treatment, and blackening treatment. The roughening effect is provided by such a roughening treatment. The copper foil is strongly adhered to the resin portion and is not easily peeled from the resin portion. As described above, the composite electronic component 10 of this embodiment includes a first circuit substrate 12 on which several electronic components are mounted, and a second circuit substrate 14 on which several through holes 14A are provided. And in these through-holes 14A, each electronic component is contained in the state and the first circuit substrate 99412 in the state. doc -20- 200540927 12 is electrically connected; the second circuit substrate 14 has a number of stacked insulating layers 14B and in-plane wiring conductors formed on one side of the insulating layer 14B. Therefore, the first circuit substrate 12 and the The second circuit board 14 arranged in the space between each electronic component and the wafer-type electronic components such as wiring patterns, active chip components 14G and passive chip components 14H or film elements such as resistance elements 141 and dielectric elements 14J constitutes one. The circuit board can effectively use the space between the electronic components 11 and can realize high-density wiring and high functionality without poor conduction, and further promote the miniaturization and flattening of the composite electronic component 10. In addition, since the first and second circuit boards 12, 14 can use a general-purpose printed wiring board, the composite electronic component 10 can be manufactured at a low cost. In addition, since the composite electronic component of this embodiment is provided with a resin portion 15 formed in a gap with the electronic component u in each of the through holes 14A of the second circuit board 14, the first portion can be surely sealed by the resin portion 15. The gap between each electronic component 11 on the circuit substrate 12 and the second circuit substrate 4 can improve the reliability of the composite electronic component 10. Furthermore, by covering the surfaces of the electronic components 11 and the first circuit substrate 14 with the resin portion 5 as well, the electronic components 11 and the second circuit substrate 14 can be completely sealed, so that a highly reliable composite electronic component can be obtained. . In addition, since the in-plane wiring conductor 14C of the second circuit substrate 14 is formed in a suitable plane of several insulating layers 14B and is formed at a height between each of the upper and lower surfaces of each electronic component 11, each electronic component can be effectively used A gap of 11 is used as a space for wiring patterns. Because the spacer η is interposed between the first circuit substrate 12 and the second circuit substrate 14, the spacers 13 absorb each of the first and second circuit substrates 12, 14 99412. doc -21-200540927 The unevenness caused by volts, etc., can accurately fit these two, 12, 14. Furthermore, since the spacer I] has the conductor portion BA, the first and second circuit boards 12, 14 can be reliably electrically connected. Next, referring to Figs. 2 to 4, and noting the symbols only in the main parts, an embodiment of a method for manufacturing the composite electronic part shown in Fig. 1 (a) will be described. First, as shown in FIG. 3 (a), a first circuit board 12 made of a multilayer resin substrate is prepared in advance. A first external terminal electrode 12D is formed on the first circuit substrate 2 in a specific pattern, and a copper foil 12Έ for the second external terminal electrode 12E is bonded and formed on the lower surface. A specific position of the first external terminal electrode 12D on the first circuit substrate 12 is aligned, as shown in the figure, a plurality of electronic parts 11 are respectively mounted, and a plurality of spacers 13 are fixed. The electronic component 11 and the spacer 13 can be mounted on the first circuit board 12 via a conductive resin, a solder paste, or the like. Secondly, as shown in (b) of FIG. 3, align the first circuit substrate 12 and the second circuit substrate 14 made of a multilayer resin substrate in advance, and above the first circuit substrate 12 with the penetration of the second circuit substrate 14. After the second circuit substrate 14 is disposed such that the hole 14A is located directly above the electronic component 11, the first and second circuit substrates 12 and 14 pass through each spacer 13 at a specific pressure as shown in (c) of the figure. fit. Thereby, the electronic components ^ on the first circuit substrate 12 are housed in the through holes 14A of the second circuit substrate 14. At this time, the first and second circuit boards 12, 14 are surely electrically connected via the conductor portion 13A of the spacer?. In addition, since the first and second circuit substrates 12, 14 are pre-formed with via-hole conductors, the deformation of the via-hole conductors is not caused by this. doc -22- 200540927 caused poor connection. Next, as shown in FIG. 3 (d), the resin portion 15 is placed on the lower side, and the copper portion 16 and the resin portion 15 having the uncured state (B stage) prepared in advance are arranged on the first circuit substrate. After 12 is above, when stacked and crimped on the first circuit substrate 12, the resin flows and is buried in the gaps in the through holes 14A of the second circuit substrate 14, etc., and covers each electronic component and the second circuit substrate. 14 ', and as shown in part (e) of the figure, a resin portion 15' in an unhardened state is formed. Then, 'the resin portion 15' is heat-treated at a temperature higher than its thermal curing temperature, and when the resin portion 15 is hardened, a semi-finished product 10 of a composite electronic part can be obtained. Then, 'the semi-finished product 10 shown in (e) of FIG. 3 is etched in a specific pattern on the upper and lower sides of the semi-finished product 10, respectively, and openings O are provided on the copper foils 12Έ, 16, as shown in FIG. 4 (a ), A second external terminal electrode 12E and a barrier electrode 16 are formed. Next, as shown in FIG. 4 (b), laser light is irradiated, and via holes H are formed in each of the opening portions 0 in the first circuit substrate 12 and the resin portion 15, as shown in FIG. 4 (c). By performing electroless copper plating and electrolytic copper plating, forming second and third via hole conductors 12F, 17 in the via hole ，, a composite electronic part 10 can be obtained. As is clear from the above, since this embodiment has the following steps: align the first circuit board 12 on which a plurality of electronic parts u are mounted, and the second circuit board having a plurality of through holes 14A corresponding to the plurality of electronic parts 11 14; and each electronic component 11 is housed in each through hole 14A to attach the first circuit substrate 12 and the second circuit substrate 14; therefore, the first and second circuit substrates '14' prepared in advance are only Two circuit substrates 14 in the first-circuit substrate 99412. doc -23- 200540927 12 alignment, you can effectively use the electronic part U 1 gate gap on the first circuit substrate 12 to form a circuit substrate, and achieve high-density wiring and high functionality without poor conduction, further lower cost The miniaturization and flattening of the composite electronic component 10 are promoted. In addition, since the first and second circuit boards 12, 14 can be bonded together to form a single circuit board, the characteristics of the electronic components can be reliably prevented from being deteriorated. In addition, since the present embodiment fills the gap between each electronic component 11 formed in each through-hole 14A with an uncured mixed resin composition to seal each electronic component n and the second circuit substrate 14, it is possible to The resin portion 15 does protect the electronic component ^ and the second circuit substrate 14 from external environmental influences, thereby improving the reliability of the composite electronic component 10. In addition, since the step of arranging the spacers 13 on the first circuit substrate 12 is provided, the unevenness between the first and second circuit substrates 12 and 14 can be reliably absorbed, and the interval between the two can be adjusted to reliably adhere to the first The circuit board 12 and the second circuit board 14 are provided with the conductor portion 13A, so that the first circuit board 12 and the second circuit board 14 can be electrically connected. Second Embodiment In this embodiment, as shown in FIG. 5, a resin layer 23 may be applied on the lower surface of the second circuit board 14 instead of the spacer 13 in the above embodiment. The composite electronic component 10A shown in FIG. 5 has the same structure as the composite electronic component 10 shown in FIG. 1 and FIG. 2 except for the resin layer 23 formed under the second circuit substrate 14. In the above embodiments, the same or corresponding parts are denoted by the same reference numerals, and descriptions of the same parts are omitted. Since the resin layer 23 formed under the second circuit substrate 14 has elasticity, it can absorb the first and 99412th. doc -24- 200540927 The undulations and irregularities of the two circuit substrates 12 and 14 can surely fit these two 12,14. The resin layer 23 may be formed of a thermosetting resin or a mixed resin composition of a thermosetting resin and an inorganic filler, similarly to the insulating layer 14B of the second circuit board 14. The resin layer 23 also has a conductor portion 23A formed in a portion electrically connected to the first and second circuit boards 12, 14 as shown in the figure. The conductor portion 23A can be formed of a conductive resin. In addition, in this embodiment, as in the above embodiment, wafer-type electronic components and membrane elements such as active wafer components and passive wafer components can be incorporated in the second circuit substrate 14, but they are not shown in the figure. Next, referring to FIG. 6 and FIG. 7, only the main parts are marked with symbols to explain one embodiment of the manufacturing method of the composite electronic component 10 shown in FIG. 5. The composite electronic component 10A of this embodiment uses a resin layer 23 coated on the lower surface of the second circuit substrate 14 instead of the spacer 13 of the above-mentioned embodiment, and other components can be manufactured by the same construction method as the above-mentioned embodiment. That is, as shown in (a) of FIG. 6, a plurality of electronic components? Are mounted at specific positions of the first external terminal electrode 12D of the first circuit board 12. Secondly, as shown in FIG. 6 (b), after the second circuit substrate 14 and the first circuit substrate 12 on which the resin layer 23 is formed are aligned, the first and second circuit substrates 12, 14 are at a specific pressure to each other, such as As shown in (c) of the figure, bonding is performed via the resin layer 23. Accordingly, each electronic component 11 on the first circuit substrate 12 is housed in each through hole 14A of the second circuit substrate 14. At this time, the first and second circuit boards 12 and 14 can be reliably electrically connected via the conductor portion 23A of the resin layer 23. Next ', as shown in FIG. 6 (d), a copper foil 16 having a resin portion 15 is disposed above the first circuit substrate 12, and then stacked and crimped to the first circuit substrate 99412. doc -25- 200540927 12, the gaps and the like embedded in the through holes 14A of the second circuit substrate 14 are buried, and they cover the upper surfaces of the electronic components 11 and the second circuit substrate 14, as shown in (e) of the figure, After the resin portion 15 is formed in an unhardened state, when the resin portion is hardened, a semi-finished product 10A of the composite electronic component 10A is obtained. Then, the copper foil 12Έ, 16 'on the upper and lower sides of the semi-finished product 10, A shown in FIG. 6 (e) is provided with an opening 0 as shown in FIG. 7 (a) to form a second outer portion. The terminal electrode 12E and the barrier electrode 16. Then, as shown in (b) of the figure, laser light is irradiated, and via holes Η are formed in each of the opening portions 0 in the first circuit substrate 12 and the resin portion 15 as shown in (c) of the figure. Electroless copper plating and electrolytic copper plating, forming the second and third via hole conductors 12F, 17 in the via hole ，, can obtain a composite electronic part 10A. Therefore, in this embodiment, in addition to the expectation that the same effect as that of the above embodiment can be obtained, the resin layer 23 is interposed between the first circuit substrate 12 and the second circuit substrate 14, so that the first layer can be absorbed by the resin layer 23. The undulations of each of the first and second circuit substrates 12 and 14 are good, and the two circuits 12 and 14 are indeed attached with high accuracy. Furthermore, since the resin layer 23 has a conductor portion 23a, the first and second circuit boards 12, 14 can be reliably electrically connected. Third Embodiment Each of the above-mentioned embodiments mentions that wafer-type electronic components such as active wafer components and passive wafer components can be embedded in the first and second circuit substrates 12, 14, but this embodiment is shown in FIG. 8, It is explained that the first circuit substrate 12 includes a film element such as a resistive element and a dielectric element, and the second circuit substrate 14 includes a composite electronic component 10B that includes wafer-type electronic components such as active wafer components and passive wafer components. The composite electronic part of this embodiment is not divided into the first 99412. doc -26- 200540927 and the second circuit substrates 12 and 14 contain wafer-type electronic parts and membrane elements in addition to the above-mentioned embodiments, and therefore descriptions of the same or equivalent parts as those of the above-mentioned embodiments are omitted, and Mainly describe the features of this embodiment. Therefore, in this embodiment, the first and second circuit substrates 12, 14 can be formed into a multilayer circuit substrate including a multilayer resin substrate and a multilayer ceramic substrate in the same manner as in the foregoing embodiments. As shown in (a) of FIG. 8, the first circuit board 12 used in this embodiment is divided by a plurality of film elements 12 including resistance elements and dielectric elements, and ceramics such as laminated B-layer capacitors and laminated inductors. The sintered body is formed as a multilayer ceramic substrate of a passive wafer component (not shown) of the element body, and is constructed in accordance with each of the above embodiments. A plurality of film elements 12G are connected between the in-plane wiring conductors 12B and 12B at each specific position. By including the membrane element 12G and the passive chip component (not shown in the figure) in the first circuit substrate, a space for mounting electronic components such as active chip components on the mounting surface of the first circuit substrate 12 is ensured, and this can be promoted. It is highly functional, and the flatness of the first circuit g substrate 12 can be realized. As in the second circuit board 14 as shown in Fig. 2, a multilayer resin substrate having a through hole 14A is formed. In addition, the second circuit substrate 14 is shown in FIG. 8 (shown as a magic chip, and contains active chip components (not shown in the figure) and passive chip components 14H and other wafer-type electronic components. Each of the wafer-type electronic components is connected to the same arrangement.) In-plane wiring conductors 14C in-plane and in-plane wiring conductors 14C arranged above and below. In addition to chip-type electronic components, the second circuit board 14 can also contain chip-type electronic components and Leiyang Shicong Ding. Order 1 dry-time resistive element, dielectric element and other membrane elements' but not shown in the figure. 99412. doc -27- 200540927 In addition, the second circuit substrate 14 can be divided into: a lower layer 141, which includes: a via conductor 14D at the bottom, and an insulating layer 14B including the same; and an upper layer 142, which includes: Above these in-plane wiring conductors 14C, via-hole conductors 14D, and insulating layers 14B of wafer-type electronic components including active wafer components (not shown in the figure) and passive wafer components 14H. The lower layer 141 is preferably formed by being attached to the lower layer 142 when the second circuit substrate 14 is mounted on the first circuit substrate 12. Each of the insulating layers 14B forming the lower layer 141 and the upper layer 142 includes a mixed resin composition of a thermosetting resin and an inorganic filler, and the lower layer 141 is in a semi-hardened state (B stage) when bonded. Since the lower layer 141 of the second circuit board 14 forms a resin layer, the same effect as that of the second embodiment can be expected. In addition, the through-holes 14A may be formed after the lower layer 141 and the upper layer 142 are bonded to each other and need to be the through-holes 14A. When the composite electronic component 10B of this embodiment is manufactured, as shown in FIG. 8 (a), a plurality of electronic components 11 are mounted at specific positions of the first external terminal electrode 12d of the first circuit board 12. Secondly, as shown in (a) of the figure, after aligning the through-holes 14A of the second circuit board 14 with the lower layer 141 and the electronic component 11 of the first circuit board 12, as shown in (b) of the figure The first and second circuit boards 12, 14 are crimped with a specific pressure. Thereby, the electronic components 11 on the first circuit substrate 12 are housed in the through holes 14A of the second circuit substrate µ. At this time, the first and second circuit substrates 12, 14 can be surely electrically connected via the via-hole conductor 14D of the lower layer 141 of the second circuit substrate 14. Next, as in the above embodiments, the resin portion is placed on the lower side, and the first circuit substrate 12 is stacked and crimped to have an unhardened state (B stage) 99412. doc 28 · 200540927 After the copper part of the resin part is hardened, the resin part 15 is hardened, and the barrier electrode 16 is formed by the copper foil. Furthermore, after a via hole is formed in a specific pattern from the second circuit board 丨 4, In electrolytic copper plating and electrolytic copper plating, since a third via hole conductor 17 is formed in the via hole, a composite electronic part 10B can be obtained. In (c) of FIG. 8, the ν degree of the electronic component u from the mounting surface (upper surface) of the first circuit substrate 12 is higher than that of the first circuit substrate 14, but the south degree of the electronic component 11 and the second circuit substrate 14 may also be The heights are all high. In addition, in this embodiment, a lower layer 141 having a via-hole conductor 14D is provided on the second circuit substrate 14, and the second circuit substrate 14 and the first circuit substrate 12 are electrically connected through the via-hole conductor 14D. In this embodiment, a spacer may be interposed to replace the via-hole conductor 14D of the lower layer 141. In this embodiment, a passive chip component 12G ′ is embedded in the first circuit substrate 12 and an electronic component 11 is mounted thereon. In addition, an active chip component (not shown in the figure) and a passive are embedded in the second circuit substrate 14. Wafer-type electronic parts such as wafer parts 14H, can effectively use the space formed next to the electronic parts 11, besides wiring patterns, they can also be used as wafers with active wafer parts (not shown) and passive wafer parts 14H. The space for electronic components and membrane elements can further promote the miniaturization, flatness, and high functionality of the composite electronic component 10B. Fourth Embodiment In addition, Fig. 9 is a diagram showing another embodiment of the composite electronic component of the present invention. The composite electronic component 50 of this embodiment is constructed in accordance with each of the above embodiments except that the second circuit board of each of the above embodiments is divided into a plurality of functions according to functions. Because this embodiment is divided into several circuit bases 99412. doc -29- 200540927 The boards are individually mounted on the first circuit board, so the spacers in the above embodiments are not needed. Therefore, the composite electronic component of the present embodiment is configured in the same manner as in each of the above embodiments, except for the parts described below.

亦即，如圖9所示，本實施形態之複合型電子零件5〇具 備··安裝有數個（參照圖11}電子零件51之第一電路基板 52，在該第一電路基板52上與電子零件51並列安裝之第 二、第三及第四電路基板53，54，55;及在第一電路基板 52上埋入電子零件51與第二、第三及第四電路基板53, 54, 55之間隙之樹脂部56;與上述各實施形態同樣地，第 一電路基板52之配線圖案與第三、第三及第日電路基板 53 54，55之配線圖案一體化，全體構成一個電路基板之 電路圖案，如安裝於母板（圖上未顯示）等來使用。而後， 在樹脂部56之上面形成有屏障電極57，並且在樹脂部56内 形成有連接屏障電極57與第一電路基板52之導通孔導體 58 〇 φ 如圖9之⑷所示，第一電路基板52具備：堆疊之數層絕 緣層52A ’形成於各絕緣層52A之面内配線導體（圖上未顯 示），連接上下之面内配線導體間之導通孔導體(圖上未顯 不）及以特定之圖案形成於上下兩面之第一及第二外部端 子電極52B，52C;實質上，係準上述各實施形態之第一 t路基板而構成。第—電路基板切為多層㈣基板，亦 .可為多層樹脂基板。第一電路基板52中，如上述，除配線 圖案之外，可内藏被動晶片零件、主動晶片零件、電阻元 件及電介質元件等之膜元件。 99412.doc -30- 200540927 第二、第三及第四電路基板53，54，55分別以相同高度 設定成比電子零件51高。但是，電子零件51之上面可比第 二電路基板53之上面高或低，此外，亦可為第二、第三及 第四電路基板53，54，55分別不是相同高度。電子零件5 1 與上述各實施形態同樣地，係半導體積體電路元件等之主 動晶片零件及將陶瓷燒結體作為素體之被動晶片零件。此 外’第一、第二、第三及第四電路基板52，53，54，55與 上述各實施形態同樣地，可藉由具有特定之配線圖案之多 層樹脂基板或多層陶瓷基板而形成。 而後，如圖9之（b)所示，第二電路基板53具備：堆疊之 數層絕緣層（樹脂層）53A、面内配線導體53B、導通孔導體 53C、安裝用端子53D及晶片型電子零件53E，並經由安裝 用端子5 3D與第一電路基板52之第一外部端子電極5 2B電 性連接。晶片型電子零件53E與上述各實施形態同樣地， 係藉由主動晶片零件及被動晶片零件構成，並連接於包含 面内配線導體53B及導通孔導體53C之配線圖案。亦即， 第一電路基板53係構成内藏晶片型電子零件53E之多層電 路基板’並與第一電路基板52 一體化。 如圖9之（c)所示，第三電路基板54具備··堆疊之數層絕 緣層（樹脂層）54八、面内配線導體54B、導通孔導體54C、 女裝用鳊子54D及屏障連接用端子54E，並經由安裝用端 子54D連接於第一電路基板52之第一外部端子電極52β， 並且經由屏障連接用端子54E及樹脂部56内之導通孔導體 54F(參照該圖之（a))而連接於屏障電極57，自外部之磁性 99412.doc -31 - 200540927 環境保護複合型電子零件丨〇B。 如圖9之⑷所示，第四電路基板55具備··堆疊之數層絕 緣層（樹脂層）55A、面内配線導體55B、導通孔導體55(：、 安裝用端子55D及膜元件55F，並經由安裝用端子55d連接 於第一電路基板52之第一外部端子電極52B。亦即，第四 電路基板55除不具屏障連接用端子及具備膜元件之外，具 有與第三電路基板54相同之構造。另外，第二、第三及第 四電路基板53 , 54，55亦可均為多層陶瓷基板。 如以上之說明，本實施形態除關於間隔物之作用效果之 外’可期待準上述各實施形態之作用效果。 其次，參照圖10及圖11，並僅在主要部分註記符號來說 明圖9所示之複合型電子零件之製造方法一種實施形態。 首先，如圖10之（a)所示，預先準備以多層陶瓷基板製作之 第一電路基板52。在該第一電路基板52之上面以特定之圖 案形成第一外部端子電極52B，在其下面形成有第二外部 端子電極52C。如該圖所示，係在第一電路基板52上面， 對準特定之第一外部端子電極52B，同時如該圖之（b)所 示，個別地安裝電子零件51及預先以多層樹脂基板製作之 各個第二、第三及第四電路基板53，54，55。圖11顯示該 狀態。 其次，將預先準備之未硬化狀態（B階段）之樹脂板（圖上 未顯示）配置於第一電路基板52上方後，堆疊、壓接於第 一電路基板52上時，樹脂流動而埋入電子零件5 1及第二、 第三及第四電路基板53，54，55之間隙，並且覆蓋電子零 99412.doc -32- 200540927 件51及第二、第三及第四電路基板53，54，55之上面，如 圖10之（c)所示，以未硬化狀態之樹脂部56,密封電子零件 51及第二、第三及第四電路基板53，54，55。而後，以比 其熱硬化溫度高之溫度熱處理樹脂部56’，形成硬化之樹脂 部56 ’而獲得複合型電子零件50之半成品50,。然後，如該 圖之（d)所示，在樹脂部56之上面以特定之圖案照射雷射 光，在樹脂部56内形成導通孔Η後，如該圖之（e)所示，實 施無電解銅電鍍及電解銅電鍍，在導通孔Η，H1内形成導 通孔導體58，54F。此時，同時藉由電鍍形成屏障電極（圖 上未顯示），而獲得本實施形態之複合型電子零件5〇。另 外，本實施例亦與上述各實施形態同樣地，一面亦可使用 預先以銅箔覆蓋之樹脂板來形成樹脂部56。此外，亦可在 第一、第二、第三及第四電路基板52，53，54，55上搭載 上述之晶片零件。 如以上之說明，由於本實施形態具備以下步驟··將電子 零件51安裝於第一電路基板52,並且將第二、第三及第四 電路基板53，54，55安裝於第一電路基板52;及在第一電 路基板52上填充樹脂，來填充電子零件51與第二、第三及 第四電路基板5 3 ’ 5 4 ’ 5 5之間隙；因此只須準備預先製作 之第一、第二及第四電路基板53，54，55，並將第二電路 基板53在第一電路基板52上對準，而與第一電路基板52構 成一個電路基板，除可實現無導通不良之高密度配線，進 一步可以低成本促進複合型電子零件50之小型化及扁平化 之外，還可期待準上述各實施形態之作用效果。 99412.doc -33- 200540927 第五種實施形態 此外，圖12係顯示本發明之複合型電子零件另外實施形 態之圖。本實施形態之複合型電子零件6〇係將相當於安裝 於圖9所示之複合型電子零件5〇之第一電路基板52上之電 子零件51及第二、第三及第四電路基板53, 54, 55之電路 基板配置於具有特定之配線圖案，進一步具有成為對母板 專女裝用基板之連接端子之端子電極圖案之轉印用支撐體 上而構成者。因此本實施形態之第二、第三及第四電路基 板63 , 64，65與第四種實施形態之第二、第三及第四電路 基板53，54，55之構造相同。 亦即，如圖12之（a)所示，本實施形態之複合型電子零件 6〇具備：1個電子零件61，與該電子零件61並列配置之第 二、第三及第四電路基板63, 64, 65,及埋入電子零件61 與第一、第二及第四電路基板63，64，65之間隙而將此等 兩者予以一體化之樹脂部66，在支撐體7〇上自由剝離地支 撐，可安裝於母板等之安裝用基板而形成。而後，在樹脂 部66之上面形成有屏障電極67，並且在樹脂部“内形成有 電性連接屏障電極67與配置於支撐體7〇上之電極62B之導 通孔導體68。另外，電子零件61及第二、第三及第四電路 基板63 ’ 64 ’ 65亦經由各個安裝用端子而與配置於支撐體 7〇上之電極62B電性連接。該支撐體7〇如可使用樹脂膜及 不錄鋼板等。亦即，本實施形態之複合型電子零件6〇係設 於支撐體70表面之特定之端子電極圖案轉印於電子零件“ 及第二、第三及第四電路基板63，64，65側，而將電極 99412.doc -34- 200540927 62B作為端子電極之複合型電子零件。 而後，本實施形態之複合型電子零件60如圖12之（b)所 示，自支撐體70剝離，將支撐體70上之電極62B轉印於電 子零件及各電路基板側時，對母板安裝時，第二、第三及 第四電路基板63，64，65與母板之電路圖案一體化，以全 體構成一個電路基板之電路圖案。 另外，本發明並不限定於上述各實施形態。只要是使用 預先製作之第一及第二電路基板，且藉由使用在對應於第 一電路基板上安裝之電子零件之位置形成有貫穿孔之第二 電路基板，不產生導通不良而可形成高密度配線，再者， 藉由使用間隔物或樹脂層，確實貼合第一及第二電路基 板，而取兩者間之電性導通者，全部包含於本發明。此 外，第一電路基板上安裝至少1個第二電路基板而構成之 複合型電子零件及至少包含1個電路基板及電子零件，而 以樹脂一體構成之複合型電子零件亦包含於本發明。 本發明適合用於廣泛使用在行動電話等之移動式通訊裝 置及一般電子機器上之複合型電子零件及其製造方法。 【圖式簡單說明】 圖1(a)〜(c)分別係顯示本發明之複合型電子零件一種實 施形態之剖面圖’（a)係顯示全體之剖面圖，（b)，（c)分別 係放大顯示可適用於第二配線電路之一部分之電路圖案之 剖面圖。 圖2係顯示用於圖1所示之複合型電子零件之第一、第一 電路基板之分解立體圖。 99412.doc -35- 200540927 圖3(a)〜(e)分別係顯示圖1所示之複合型電子零件之製造 步驟之說明圖。 圖4(a)〜(c)分別係顯示繼續圖3所示之製造步驟之說明 圖0 圖5係顯示本發明之複合型電子零件其他實施形態之剖 面圖。 圖6(a)〜(e)分別係顯示圖5所示之複合型電子零件之製造 步驟之說明圖。That is, as shown in FIG. 9, the composite electronic component 50 of this embodiment includes a first circuit board 52 (refer to FIG. 11) in which a plurality of electronic components 51 are mounted. Second, third, and fourth circuit substrates 53, 54, 55 in which the component 51 is mounted in parallel; and electronic components 51 and second, third, and fourth circuit substrates 53, 54, 55 embedded in the first circuit substrate 52 The resin portion 56 of the gap; as in the above embodiments, the wiring pattern of the first circuit board 52 and the wiring patterns of the third, third, and day circuit boards 53 54, 55 are integrated to form a circuit board as a whole. The circuit pattern is used by being mounted on a mother board (not shown), etc. Then, a barrier electrode 57 is formed on the resin portion 56, and a connection between the barrier electrode 57 and the first circuit substrate 52 is formed in the resin portion 56. As shown in FIG. 9 (a), the first circuit board 52 includes a plurality of stacked insulating layers 52A 'formed in the plane of each of the insulating layers 52A. A wiring conductor (not shown in the figure) connects the upper and lower conductors. Conduction between in-plane wiring conductors The conductors (not shown in the figure) and the first and second external terminal electrodes 52B, 52C formed on the upper and lower sides in a specific pattern; essentially, the first t-channel substrate of each of the above embodiments is formed. Section— The circuit substrate is cut into a multi-layer substrate or a multilayer resin substrate. In the first circuit substrate 52, as described above, in addition to the wiring pattern, passive chip parts, active chip parts, resistance elements, and dielectric elements can be embedded. Membrane element. 99412.doc -30- 200540927 The second, third, and fourth circuit boards 53, 54 and 55 are respectively set to be higher than the electronic component 51 at the same height. However, the electronic component 51 may be higher than the second circuit substrate 53 The upper surface is high or low, and the second, third, and fourth circuit substrates 53, 54, and 55 may not be the same height. The electronic component 5 1 is a semiconductor integrated circuit element, etc., as in the above embodiments. The active wafer part and the passive wafer part using the ceramic sintered body as the element body. In addition, the first, second, third, and fourth circuit substrates 52, 53, 54, 55 are the same as the above-mentioned embodiments, It is formed by a multilayer resin substrate or a multilayer ceramic substrate having a specific wiring pattern. Then, as shown in FIG. 9 (b), the second circuit substrate 53 includes a plurality of stacked insulating layers (resin layers) 53A, and a surface. The inner wiring conductor 53B, the via conductor 53C, the mounting terminal 53D, and the chip-type electronic component 53E are electrically connected to the first external terminal electrode 5 2B of the first circuit board 52 via the mounting terminal 5 3D. The chip-type electronic component 53E is composed of an active chip component and a passive chip component, and is connected to a wiring pattern including an in-plane wiring conductor 53B and a via-hole conductor 53C, as in the above-mentioned embodiments. That is, the first circuit substrate 53 is a multilayer circuit substrate 'which is a built-in wafer-type electronic component 53E and is integrated with the first circuit substrate 52. As shown in FIG. 9 (c), the third circuit board 54 includes a plurality of stacked insulating layers (resin layers) 54, in-plane wiring conductors 54B, via conductors 54C, women's ladle 54D, and barriers. The connection terminal 54E is connected to the first external terminal electrode 52β of the first circuit board 52 via the mounting terminal 54D, and via the barrier connection terminal 54E and the via-hole conductor 54F in the resin portion 56 (see (a of the figure) )) And the magnetic electrode connected to the barrier electrode 57 from the outside 99412.doc -31-200540927 environmental protection composite electronic parts. As shown in FIG. 9A, the fourth circuit board 55 includes a plurality of stacked insulating layers (resin layers) 55A, in-plane wiring conductors 55B, via conductors 55 (:, mounting terminals 55D, and film elements 55F, It is connected to the first external terminal electrode 52B of the first circuit substrate 52 via the mounting terminal 55d. That is, the fourth circuit substrate 55 has the same structure as the third circuit substrate 54 except that it has no barrier connection terminals and is provided with a film element. In addition, the second, third, and fourth circuit substrates 53, 54, and 55 may also be multilayer ceramic substrates. As described above, this embodiment is expected to be accurate except for the effect of the spacer. Functions and Effects of Each Embodiment Next, an embodiment of the manufacturing method of the composite electronic component shown in FIG. 9 will be described with reference to FIG. 10 and FIG. 11 and the main parts will be marked with symbols. First, FIG. 10 (a) As shown, a first circuit substrate 52 made of a multilayer ceramic substrate is prepared in advance. A first external terminal electrode 52B is formed on the first circuit substrate 52 in a specific pattern, and a second external portion is formed below the first circuit substrate 52. Terminal electrode 52C. As shown in the figure, it is located on the first circuit board 52, and is aligned with a specific first external terminal electrode 52B. At the same time, as shown in (b) of the figure, the electronic parts 51 are individually mounted and Each of the second, third, and fourth circuit substrates 53, 54, 55 made of a multilayer resin substrate. This state is shown in FIG. 11. Next, a resin plate (not shown) in an unhardened state (stage B) prepared in advance will be prepared. After being disposed above the first circuit substrate 52, when stacked and crimped onto the first circuit substrate 52, the resin flows and is buried in the gap between the electronic component 51 and the second, third, and fourth circuit substrates 53, 54, 55 , And cover the electronic parts 99412.doc -32- 200540927 51 and the second, third and fourth circuit substrates 53, 54, 55, as shown in (c) of FIG. 10, the resin part in an unhardened state 56, seals the electronic component 51 and the second, third, and fourth circuit substrates 53, 54, 55. Then, the resin portion 56 'is heat-treated at a temperature higher than its thermosetting temperature to form a hardened resin portion 56' to obtain a composite. Semi-finished product 50 of the electronic component 50, and then, as shown in the figure As shown in (d), laser light is irradiated on the resin portion 56 in a specific pattern to form a via hole 树脂 in the resin portion 56. As shown in (e) of the figure, electroless copper plating and electrolytic copper are performed. Electroplating forms via-hole conductors 58 and 54F in via holes Η and H1. At this time, a barrier electrode (not shown in the figure) is formed by electroplating at the same time to obtain a composite electronic component 50 of this embodiment. In addition, this The embodiment is also the same as the above-mentioned embodiments, and the resin portion 56 may be formed using a resin plate covered with copper foil in advance on one side. Alternatively, the first, second, third, and fourth circuit boards 52, 53 may be formed. The above-mentioned chip components are mounted on the, 54,55. As described above, the present embodiment has the following steps: the electronic component 51 is mounted on the first circuit substrate 52, and the second, third, and fourth circuit substrates 53, 54, 55 are mounted on the first circuit substrate 52. ; And filling the first circuit substrate 52 with resin to fill the gap between the electronic component 51 and the second, third, and fourth circuit substrates 5 3 '5 4' 5 5; therefore, only the first and The second and fourth circuit substrates 53, 54, 55, and the second circuit substrate 53 is aligned on the first circuit substrate 52, and constitutes a circuit substrate with the first circuit substrate 52, in addition to achieving high density without poor conduction In addition to wiring, the miniaturization and flattening of the composite electronic component 50 can be further promoted at a low cost, and the effects of the foregoing embodiments can be expected. 99412.doc -33- 200540927 Fifth Embodiment In addition, FIG. 12 is a diagram showing another embodiment of the composite electronic part of the present invention. The composite electronic component 60 of this embodiment is equivalent to the electronic component 51 and the second, third, and fourth circuit substrates 53 mounted on the first circuit substrate 52 of the composite electronic component 50 shown in FIG. 9. The circuit substrates of 54, 55 are arranged on a supporting body having a specific wiring pattern and a terminal electrode pattern which is a connection terminal to a substrate for a mother board for women. Therefore, the structures of the second, third, and fourth circuit boards 63, 64, 65 of this embodiment are the same as those of the second, third, and fourth circuit boards 53, 54, 55 of the fourth embodiment. That is, as shown in FIG. 12 (a), the composite electronic component 60 of this embodiment includes one electronic component 61, and second, third, and fourth circuit boards 63 arranged in parallel with the electronic component 61. , 64, 65, and the resin portion 66 in which the gap between the embedded electronic component 61 and the first, second, and fourth circuit boards 63, 64, 65 is integrated, and these two are integrated on the support 70 The support is peeled and can be formed on a mounting substrate such as a motherboard. Then, a barrier electrode 67 is formed on the resin portion 66, and a via hole conductor 68 electrically connecting the barrier electrode 67 and the electrode 62B disposed on the support 70 is formed in the resin portion. In addition, the electronic component 61 And the second, third, and fourth circuit substrates 63'64'65 are also electrically connected to the electrodes 62B disposed on the support body 70 through each mounting terminal. If the support body 70 can use a resin film and Steel plates, etc. That is, the composite electronic component 60 of this embodiment is a specific terminal electrode pattern provided on the surface of the support body 70 and transferred to the electronic component, and the second, third, and fourth circuit boards 63, 64. , 65 side, and the electrode 99412.doc -34- 200540927 62B is used as the terminal electrode of the composite electronic parts. Then, as shown in FIG. 12 (b), the composite electronic component 60 of this embodiment is peeled from the support body 70, and when the electrode 62B on the support body 70 is transferred to the electronic component and each circuit board side, the mother board is At the time of installation, the second, third, and fourth circuit substrates 63, 64, 65 are integrated with the circuit pattern of the motherboard to form the circuit pattern of one circuit substrate as a whole. The present invention is not limited to the above-mentioned embodiments. As long as the first and second circuit substrates are used in advance, and the second circuit substrate is formed with a through hole formed at a position corresponding to the electronic component mounted on the first circuit substrate, high conduction can be achieved without causing a poor conduction. The density wiring is further included in the present invention by using a spacer or a resin layer to surely bond the first and second circuit substrates, and taking the electrical conduction therebetween. In addition, a composite electronic component including at least one second circuit substrate mounted on a first circuit substrate and at least one circuit substrate and electronic components, and a composite electronic component composed of a resin as a whole are also included in the present invention. The present invention is suitable for composite electronic parts widely used in mobile communication devices such as mobile phones and general electronic equipment, and a method for manufacturing the same. [Brief description of the drawings] Figures 1 (a) to (c) are sectional views showing one embodiment of the composite electronic part of the present invention, and (a) is a sectional view showing the whole, (b), (c), respectively. It is an enlarged sectional view of a circuit pattern applicable to a part of the second wiring circuit. FIG. 2 is an exploded perspective view showing the first and first circuit substrates for the composite electronic component shown in FIG. 1. FIG. 99412.doc -35- 200540927 FIGS. 3 (a) to (e) are explanatory diagrams showing the manufacturing steps of the composite electronic part shown in FIG. 1, respectively. Figs. 4 (a) to (c) are explanatory views showing the manufacturing steps continued from Fig. 3, respectively. Fig. 0 and Fig. 5 are sectional views showing other embodiments of the composite electronic part of the present invention. 6 (a) to (e) are explanatory diagrams showing the manufacturing steps of the composite electronic part shown in FIG. 5, respectively.

圖7(a)〜(c)分別係顯示繼續圖6所示之製造步驟之說明 圖。 圖8(a)〜(c)分別係顯示本發明另外實施形態之複合型電 子零件之製造步驟之說明圖。 圖9(a)〜(d)分別係顯示本發明之複合型電子零件另外實 施形態之圖，（a)係顯示全體之剖面圖，（b)，（c)，（d)係分 別放大顯示該圖之（a)中所示之第二、第三及第四電路基板 之剖面圖。 圖10(a)〜(e)分別係顯示圖9所示之複合型電子零件之製 造步驟之說明圖。 圖11係顯示形成圖9所示之複合型電子零件之樹脂部前 之狀態之立體圖。 另外實施形態之 體化狀態之剖面 子零件一種製造 圖12係顯示本發明之複合型電子零件 圖，（a)係顯示複合型電子零件與支撐體一 圖，（b)係顯示複合型電子零件之剖面圖。 圖13(a)〜(c)分別係顯示先前之複合型電 99412.doc -36- 200540927 步驟之說明圖。 種 圖14(a)〜(d)分別係顯示先前其他之複合型電子零件— 製造步驟之說明圖。 _ 99412.doc 【主要元件符號說明】 10，10A，10B，50，60 複合型電子零件 11 ， 51 ， 61 電子零件 12，52 第一電路基板 12A 樹脂層（絕緣層） 12B 面内配線導體 12C 第一導通孔導體 12D，52D 第一外部端子電極 12E ， 52E 第二外部端子電極 12F 第二導通孔導體 12G 膜元件 13 間隔物 13A 導體部 14 第二電路基板 14A 貫穿孔 14B 樹脂層（絕緣層） 14C 面内配線導體 14D 第一導通孔導體 14E 第一外部端子電極 14F 第二外部端子電極 14G 主動晶片零件（晶片 OC •37- 200540927 14H 被動晶片零件（晶片型電子零件） 14H 膜元件 16 ， 57 ， 67 屏障電極 15 ， 56 ， 66 樹脂部 23 樹脂層 23A 導體部 99412.doc -38-Figs. 7 (a) to (c) are explanatory views showing the manufacturing steps continued from that shown in Fig. 6, respectively. Figs. 8 (a) to 8 (c) are explanatory views showing the manufacturing steps of a composite electronic component according to another embodiment of the present invention. Figs. 9 (a) to (d) are diagrams showing another embodiment of the composite electronic part of the present invention, (a) is a sectional view showing the whole, and (b), (c), and (d) are enlarged displays, respectively. Sectional views of the second, third and fourth circuit substrates shown in (a) of the figure. 10 (a) to (e) are explanatory diagrams showing the manufacturing steps of the composite electronic part shown in FIG. 9, respectively. Fig. 11 is a perspective view showing a state before a resin portion of the composite electronic component shown in Fig. 9 is formed. In addition, a manufacturing method of sectional sub-components of the embodiment is shown in FIG. 12 showing a composite electronic part of the present invention, (a) showing a composite electronic part and a support, and (b) showing a composite electronic part. Section view. Figures 13 (a) ~ (c) are explanatory diagrams showing the steps of the previous composite type 99412.doc -36- 200540927, respectively. Species Figures 14 (a) to (d) are explanatory diagrams showing the manufacturing steps of other previous composite electronic parts, respectively. _ 99412.doc [Description of main component symbols] 10, 10A, 10B, 50, 60 Composite electronic parts 11, 51, 61 Electronic parts 12, 52 First circuit board 12A Resin layer (insulation layer) 12B In-plane wiring conductor 12C First via hole conductors 12D, 52D First external terminal electrodes 12E, 52E Second external terminal electrode 12F Second via hole conductor 12G Membrane element 13 Spacer 13A Conductor portion 14 Second circuit board 14A Through hole 14B Resin layer (insulating layer ) 14C In-plane wiring conductor 14D First via hole conductor 14E First external terminal electrode 14F Second external terminal electrode 14G Active wafer component (wafer OC • 37- 200540927 14H Passive wafer component (wafer-type electronic component) 14H Membrane element 16, 57, 67 Barrier electrodes 15, 56, 66 Resin section 23 Resin layer 23A Conductor section 99412.doc -38-

Claims (1)

200540927 十、申謗專利範®: J· 一種複合型電子零 其係安製 ：特徵為具備：第-電路基板’ 1有收^ 個電子零件；及第二電路基板，其係 /、有收各上述電子零件 右、+•雨 員茅孔，且在該貫穿孔内收容 板·：f子零件狀態τ，電性連接於上述第-電路基 =述第二電路基板具有堆叠有數層之絕緣層，及形 成於該絕緣層之一面之面内配線導體。 2 ·如凊求項1之複合型電 内 件，其令至少在上述貫穿孔 二：形成於與上述電子零件之間隙之樹腊部。 .或2之複合型電子零件，其中上述面内配線導 =成為上述電子零件之—方主面與另—方主面間之高 度0 4. 如睛求項!至3中任一項之複合型電子零件，其中在上述 第-電路基板與上述第二電路基板之間介有 脂層。 5. 如請求項4之複合型電子零件，其中上述間隔物或上述 樹脂層具有電性連接上述第一電路基板與上述第二電路 基板之導體部。 6·如請求項2至5中任一項之複合型電子零件，其中上述樹 脂部覆蓋上述電子零件及第二電路基板之表面。 7·如請求項1至6中任一項之複合型電子零件，其中上述第 一電路基板係堆疊數個絕緣層而構成之多層電路基板， 並具有形成於上述絕緣層之一面之面内配線導體，及連 接於該面内配線導體之導通孔導體。 99412.doc 200540927 8. 其中上述第 之導通孔導 如請求項1至7中任-項之複合型電子零件， 一電路基板具有連接於上述面内配線導體 體0 一:求貝1至8中任—項之複合型電子零件，其中上述第 一 路基板内藏晶片型電子零件。 1〇·如明求項!至9中任一項之複合型電子零件，其中上述第 一電路基板内藏膜元件。200540927 X. Patent Claims ®: J. A type of composite electronic zero system: it is characterized by:-the circuit board '1 has received ^ electronic parts; and the second circuit board, its system has Each of the above electronic parts has a right, + • rainman's hole, and a board is housed in the through hole: f sub-part state τ, which is electrically connected to the above-mentioned circuit base = the second circuit board has several layers of insulation stacked Layer, and an in-plane wiring conductor formed on one side of the insulating layer. 2 · If you want the composite electrical component of item 1, it should be at least in the above-mentioned through hole 2: the wax part formed in the gap with the electronic part. Or 2 composite electronic parts, in which the above-mentioned in-plane wiring guide = the height between the-square main surface and the other-square main surface of the above-mentioned electronic component 0 4. Find the item by eye! The composite of any of 3 Type electronic component in which a lipid layer is interposed between the first circuit substrate and the second circuit substrate. 5. The composite electronic component according to claim 4, wherein the spacer or the resin layer has a conductor portion electrically connecting the first circuit substrate and the second circuit substrate. 6. The composite electronic component according to any one of claims 2 to 5, wherein the resin portion covers the surface of the electronic component and the second circuit board. 7. The composite electronic component according to any one of claims 1 to 6, wherein the first circuit substrate is a multilayer circuit substrate formed by stacking several insulating layers, and has in-plane wiring formed on one side of the insulating layer. A conductor, and a via-hole conductor connected to the in-plane wiring conductor. 99412.doc 200540927 8. The above-mentioned through-hole leads are the composite electronic parts of any one of the claims 1 to 7, a circuit board has a wiring conductor connected to the above-mentioned in-plane wiring. 0 1: Seek 1 to 8 Any-item composite electronic parts, wherein the first-path substrate contains a wafer-type electronic part. 1 0. The composite electronic component according to any one of items 9 to 9, wherein the first circuit substrate has a film element embedded therein. 11·如1求項1至10中任一項之複合型電子零件，其中上述 第二電路基板係樹脂基板。 a 12. -種複合型電子零件之製造方法，其特徵為具備以下步 驟行至少搭載有i個電子零件之第一電路基板與具 有收容上述電子零件之貫穿孔之第二電路基板之對準； 及以在上述貫穿孔内收容上述電子零件之方式，貼合第 一電路基板與第二電路基板。 13·如請求項12之複合型電子零件之製造方法，其中具備至 少在與上述貫穿孔内所形成之上述電子零件之間隙填充 樹脂之步驟。 14·如請求項12或13之複合型電子零件之製造方法，其中具 備在上述第一電路基板上配置間隔物之步驟。 15·如請求項14之複合型電子零件之製造方法，其中上述間 隔物具有電性導通上述第一電路基板與上述第二電路基 板之導體部。 16·如請求項12或π之複合型電子零件之製造方法，其中上 述第二電路基板在上述第一電路基板側之面具有樹脂 99412.doc 200540927 層。 17·如請求項16之複合型電子零件之製造方法，其中上述樹 脂層具有電性導通上述第一電路基板與上述第二電路基 板之導體部。 18·如請求項16或17之複合型電子零件之製造方法，其中上 述樹脂層包含未硬化樹脂。 19·如睛求項13至18中任一項之複合型電子零件之製造方 法’其中以上述樹脂覆蓋上述電子零件及上述第二電路 基板之表面。 20. 如請求項19之複合型電子零件之製造方法，其中上述樹 脂包含未硬化樹脂。 21. —種複合型電子零件’其特徵為具備：第一電路基板， 八係至女裝有1個電子零件；至少丨個第二電路基板， 其係在該第一電路基板上與上述電子零件並列安裝；及 樹脂部’其係在上述第-電路基板上填埋上述電子零件 與上述第二電路基板之間U上述第二電路基板形成 為堆疊有數層絕緣層之疊層體，且至少内藏與上述第一 電路基板成為一體之電路圖案。 22·如請求項21之複合型雷早愛 W千零件，其中具有内藏晶片型電 子零件之第三電路基板。 23.如請求項21或22之複合型電子震 # ^ 电于零件，其中在上述樹脂部 试屝=成屏障電極’並且在上述樹脂部内形成連接上 孔：與上述第-電路基板之外部端子電極之導通 孔導體。 99412.doc 200540927 24·如請求項21至23中任一項之複合型電子零件，其中上述 第二電路基板在下面具有安裝用端子，具在上面具有屏 Ρ羊連接用端子，上述安裝用端子連接於上述第一電路美 板上之外部端子電極，並且上述屏障連接用端子經由上 述樹脂部之導通孔導體而連接於上述屏障電極。 25· —種複合型電子零件之製造方法，其特徵為具備以下步 驟·在第一電路基板上分別安裝：至少1個電子零件· 及至少1個第二電路基板，其係形成堆疊有數層絕緣層 之疊層體，且至少内藏與上述第一電路基板成為一體之 電路圖案，及在上述第一電路基板上，填充樹脂於上述 電子零件與上述第二電路基板之間隙。 26.如請求項25之複合型電子零件之製造方法，其中以上述 樹脂覆蓋上述電子零件及上述第二電路基板之表面。 27· —種複合型電子零件，其特徵為具備··至少丨個電子零 件，至少1個電路基板，其係與該電子零件並列配置； 及樹脂部，其係填埋上述電子零件與上述電路基板之間 隙，而將此等兩者予以一體化。 28. 如請求項27之複合型電子零件，其令具有内藏晶片型電 子零件之電路基板。 29. 如請求項27或28之複合型電子零件，其中上述樹脂部之 上面形成屏障電極，並且在上述樹脂部内形成連接上述 屏障電極與上述安裝用基板之導通孔導體。 30. 如請求項27至29中任一項之複合型電子零件，其中上述 電路基板在下面具有安裝用端子，並且在上面具有屏障 99412.doc 200540927 連接用端子，上述安裝用端子構成為可連接於上述安裝 用基板，並且上述屏障連接用端子構成為經由上述樹脂 部之導通孔導體可連接於上述屏障電極。11. The composite electronic component according to any one of 1 to 10, wherein the second circuit substrate is a resin substrate. a 12. A method for manufacturing a composite electronic component, comprising: aligning a first circuit substrate on which at least i electronic components are mounted with a second circuit substrate having a through hole accommodating the electronic component; And the first circuit substrate and the second circuit substrate are bonded together in a manner of accommodating the electronic components in the through holes. 13. The method for manufacturing a composite electronic part according to claim 12, further comprising a step of filling a resin with at least a gap between the electronic part and the electronic part formed in the through hole. 14. The method for manufacturing a composite electronic part according to claim 12 or 13, further comprising a step of disposing a spacer on the first circuit substrate. 15. The method of manufacturing a composite electronic component according to claim 14, wherein the spacer has a conductor portion that electrically connects the first circuit substrate and the second circuit substrate. 16. The method for manufacturing a composite electronic part according to claim 12, wherein the second circuit board has a resin 99412.doc 200540927 layer on a surface of the first circuit board side. 17. The method of manufacturing a composite electronic part according to claim 16, wherein said resin layer has a conductor portion for electrically conducting said first circuit substrate and said second circuit substrate. 18. The method of manufacturing a composite electronic part according to claim 16 or 17, wherein said resin layer contains an uncured resin. 19. The method for manufacturing a composite electronic part according to any one of items 13 to 18, wherein the surface of the electronic part and the second circuit board is covered with the resin. 20. The method of manufacturing a composite electronic part according to claim 19, wherein said resin contains an uncured resin. 21. —A composite electronic component 'characterized in that it includes: a first circuit substrate, one electronic component from the eight series to the women's clothing; at least one second circuit substrate, which is connected to the first circuit substrate and the above-mentioned electronics The parts are installed side by side; and the resin portion is formed by burying the electronic component and the second circuit substrate on the first circuit substrate, and the second circuit substrate is formed as a stacked body in which several insulating layers are stacked, and at least A circuit pattern integrated with the first circuit board is incorporated. 22. The composite Lei Zaoai W-1000 part as claimed in claim 21, which has a third circuit board with a built-in wafer type electronic part. 23. The composite electronic shock of claim 21 or 22 # ^ Electric parts, wherein the above-mentioned resin part is tested to form a barrier electrode and a connection hole is formed in the above-mentioned resin part: and the external terminal of the above-mentioned circuit board A via conductor of an electrode. 99412.doc 200540927 24. The composite electronic component according to any one of claims 21 to 23, wherein the second circuit board has a mounting terminal on the lower side, a terminal for screen connection on the upper side, and the mounting terminal The external terminal electrode is connected to the first circuit board, and the barrier connection terminal is connected to the barrier electrode via a via-hole conductor in the resin portion. 25 · —A method for manufacturing a composite electronic part, comprising the following steps: Mounting on a first circuit board separately: at least one electronic part and at least one second circuit board, which are formed by stacking several layers of insulation A layered body including at least a circuit pattern integrated with the first circuit substrate, and a gap between the electronic component and the second circuit substrate is filled with resin on the first circuit substrate. 26. The method of manufacturing a composite electronic component according to claim 25, wherein the surfaces of the electronic component and the second circuit board are covered with the resin. 27 · A composite electronic part, characterized by having at least one electronic part and at least one circuit board, which are arranged in parallel with the electronic part; and a resin part, which fills the electronic part and the circuit The substrate gap, and these two are integrated. 28. The composite electronic part of claim 27, which has a circuit board having a built-in wafer type electronic part. 29. The composite electronic component according to claim 27 or 28, wherein a barrier electrode is formed on the resin portion, and a via-hole conductor is formed in the resin portion to connect the barrier electrode and the mounting substrate. 30. The composite electronic component according to any one of claims 27 to 29, wherein the circuit board has a mounting terminal on the lower side and a barrier on the upper side. 99412.doc 200540927 The connecting terminal is configured to be connectable On the mounting substrate, the barrier connection terminal is configured to be connectable to the barrier electrode via a via-hole conductor in the resin portion. 99412.doc99412.doc
TW094105104A 2004-04-06 2005-02-21 Composite electronic component, and manufacturing method thereof TW200540927A (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2004111977 2004-04-06
JP2004212335 2004-07-20
JP2004298445 2004-10-13
PCT/JP2004/019231 WO2005101934A1 (en) 2004-04-06 2004-12-22 Composite electronic component and method for producing the same

Publications (1)

Publication Number Publication Date
TW200540927A true TW200540927A (en) 2005-12-16

Family

ID=35150384

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094105104A TW200540927A (en) 2004-04-06 2005-02-21 Composite electronic component, and manufacturing method thereof

Country Status (2)

Country Link
TW (1) TW200540927A (en)
WO (1) WO2005101934A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102119588A (en) * 2008-08-12 2011-07-06 株式会社村田制作所 Method for manufacturing module with built-in component, and module with built-in component
CN102246608A (en) * 2008-12-08 2011-11-16 揖斐电株式会社 Wiring board and method for manufacturing same

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1699277A4 (en) * 2003-12-26 2007-08-15 Murata Manufacturing Co Ceramic multilayer substrate
CN101449634B (en) 2006-05-24 2013-07-24 大日本印刷株式会社 Component internally installed wiring plate and its manufacturing method
FI20085468A0 (en) 2008-05-16 2008-05-16 Polar Electro Oy The electrical circuit arrangement
JP4711026B2 (en) * 2008-10-08 2011-06-29 株式会社村田製作所 Compound module
JP2013033776A (en) * 2009-12-04 2013-02-14 Panasonic Corp Circuit board, circuit module, and electronic apparatus

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06120671A (en) * 1991-03-12 1994-04-28 Japan Radio Co Ltd Multilayer wiring board embedded with component
JPH0579995U (en) * 1992-04-03 1993-10-29 日本無線株式会社 Multilayer wiring board with high-frequency shield structure
JPH1174648A (en) * 1997-08-27 1999-03-16 Kyocera Corp Wiring board
JP4701506B2 (en) * 2000-09-14 2011-06-15 ソニー株式会社 Circuit block body manufacturing method, wiring circuit device manufacturing method, and semiconductor device manufacturing method
JP3553043B2 (en) * 2001-01-19 2004-08-11 松下電器産業株式会社 Component built-in module and manufacturing method thereof
JP2002344146A (en) * 2001-05-15 2002-11-29 Tdk Corp High frequency module and its manufacturing method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102119588A (en) * 2008-08-12 2011-07-06 株式会社村田制作所 Method for manufacturing module with built-in component, and module with built-in component
CN102119588B (en) * 2008-08-12 2014-03-05 株式会社村田制作所 Method for manufacturing module with built-in component, and module with built-in component
CN102246608A (en) * 2008-12-08 2011-11-16 揖斐电株式会社 Wiring board and method for manufacturing same

Also Published As

Publication number Publication date
WO2005101934A1 (en) 2005-10-27

Similar Documents

Publication Publication Date Title
US7684207B2 (en) Composite electronic component
US11058007B2 (en) Component carrier with two component carrier portions and a component being embedded in a blind opening of one of the component carrier portions
US7718901B2 (en) Electronic parts substrate and method for manufacturing the same
DK2768291T3 (en) Built-in component board and method for making same as well as mounting body
KR100745359B1 (en) Ceramic multilayer substrate
JPH1145955A (en) Device built-in multilayered printed circuit board and its manufacture
TW200540927A (en) Composite electronic component, and manufacturing method thereof
CN112992504A (en) Electronic component
KR100747022B1 (en) Imbedded circuit board and fabricating method therefore
WO2014162478A1 (en) Component-embedded substrate and manufacturing method for same
JP2008159973A (en) Electronic component module and circuit board with built-in components incorporating the module
EP1776002B1 (en) Composite electronic component and method for manufacturing the same
TW201536130A (en) Wiring board with embedded components and manufacturing method thereof
US20170020000A1 (en) Component-mounted board, method of manufacturing component-mounted board and component-embedded board
JP2008270778A (en) Method of manufacturing wiring board with built-in component
KR101147343B1 (en) Integrated printed circuit board embedded with multiple component chip and manufacturing method thereof
KR100653247B1 (en) Printed circuit board having embedded electric components and fabricating method therefore
KR100828925B1 (en) Hybrid electronic component and method for manufacturing the same
JP2003168763A (en) Hybrid electronic component
TW200931458A (en) Capacitors and method for manufacturing the same
JP2007305631A (en) Resin multilayer board, compound electronic component, and manufacturing methods of resin multilayer substrate and compound electronic component
KR20100053761A (en) Embedded pcb using unclad and embedded pcb manufactured thereby
JP2004281584A (en) Surface-mounting electronic apparatus
JP2008177612A (en) Electronic component
JP2008182251A (en) Method of manufacturing electronic component