200539202 九、發明說明： 【發明所屬之技術區域】 本發明是關於中間基板。 【先前技術】 〔專利文獻1〕日本專利特開200 1 -03 5966號公報 CPU和其他LSI等之高速動作的半導體積體電路元件近 年來越發小型化，使信號端子、電源端子或接地端子之數目 增加，端子間距離亦進行縮小。多數端子密集的積體電路側 之端子陣列以倒裝式形態來連接於母板側的技術正在一般 化，但積體電路側之端子陣列及母板側的端子陣列在端子間 隔有很大的差距，爲了將此改變必須有中間基板。 如上述中間基板之中，被稱爲有機封裝（organic package)基板者，是具有由高分子材料而成的電介體層及導 電層相互交替所層疊之配線層疊部，在該配線層疊部之電介 體層所形成的第一主表面上，來配置倒裝式連接用之端子陣 列。配線層疊部，是以玻璃纖維所強化的環氧樹脂等，將高 分子材料形成於作爲主體的基板核心上。在1C側之端子間 隔，及成爲連接對象的主基板（母板）側之端子間隔之間有 相當隔開的情況下，爲了其改變之配線或穿孔的配設圖案， 亦使端子數相輔地增加，會有微細化及複雜化之傾向，但有 機封裝基板具有藉由組合光微影技術及電鍍技術，連如此微 細且複雜的配線圖案亦可高精密度且容易地形成之優點。 可是，有機封裝基板除了成爲連接對象之主基板（譬如 母板）係將高分子材料作爲主體之外，由於本身的構成材料 200539202 自體亦將高分子材料作爲主體，所以加上銲錫平焊化處理等 之熱變化現象，則無法完全吸收將矽作爲主體的半導體積體 電路元件（線膨脹係數譬如爲2〜3ppm/°C )及主基板（線 膨脹係數譬如17〜18ppm°C )之線膨脹係數差，會有有關焊 鍚剝離等不適合現象之虞。 另一方面，專利文獻1等揭示有將基板之主材料以陶瓷 來構成的陶瓷封裝基板。使用這樣的陶瓷封裝基板，可彌補 倒裝式所連接之半導體積體電路元件及主基板之間大的線 膨脹係數之差，特別可有效地防止與半導體積體電路元件之 端子間的銲鍚接合部由於熱應力而斷線之不良現象。 【發明內容】 〔發明揭示〕 〔發明所欲解決之問題〕 可是，陶瓷封裝基板因爲配線部利用金屬膏之印刷及燒 成所形成，所以像利用光微影技術的有機封裝基板將配線部 進行微細化及高積體化是有所困難，在半導體積體電路元件 側之端子間隔的縮小亦有所界限。因此，亦可以考慮在主基 板側來連接由有機封裝基板而成的第一中間基板，並在其第 一中間基板來連接由陶瓷而成之第二中間基板，在其第二中 間基板用來連接半導體積體電路元件的多段基板連接構 造，但因增加中間基板片數的部分，就會增大基板連接構造 之高度方向的尺寸所以因應小形化之要求形成困難，又，連 接製程次數亦增加會有非效率的缺點。 本發明之課題是提供一種中間基板，藉由熱應力使斷線 200539202 等難以發生’而且亦可容易達成基板連接構造全體的低背化 亦可削減連接製程次數。 〔解決發明之手段及發明效果〕 爲了解決上述課題，本發明之中間基板，具有： 基板核心，包含：藉由高分子材料（包含與陶瓷纖維或 粒子等之塡料所複合化的材料作爲槪念）來構成爲板狀，在 第一主表面以減少本身厚度的形狀下開口形成有副核心收 容部的核心本體部；及藉由比核心本體部線膨脹係數更小的 材料來構成爲板狀，在副核心收容部內以與核心本體部於厚 度方向一致的形式下由所收容之副核心部； 第一端子陣列，包含：形成在前述基板核心之第一主表 面側，由一方作爲電源端子，另一方作爲接地端子來發揮功 能的第一側第一種端子以及第一側第二種端子；及由第一側 信號端子；及 第二端子陣列，包含：形成在前述基板核心之第二主表 面側，分別導通於前述第一側第一種端子及第二種端子的第 二側第一種端子及第二側第二種端子；及導通於前述第一側 信號端子的第二側信號端子； 其特徵爲前述第一端子陣列在對與前述基板核心之板 面平行的基準面之正射投影中，以在與前述副核心部的投影 區域重疊的位置關係所形成。 根據上述構成，則半導體積體電路元件側及倒裝式所連 接的第一端子陣列之區域形成重疊，由比高分子材料所構成 的核心本體的線膨脹係數更小的材料而成的副核心部，係具 200539202 有埋設於基板核心內的構造，所以對於第一端子陣列內之端 子，可充分地來縮小與半導體積體電路元件側的線膨脹係數 差，進而可不易大幅地產生熱應力造成的斷線等。又，在相 當於第一中間基板之核心本體部，用來埋設相當於第二中間 基板的副核心部，所以可達成使用中間基板之半導體積體電 路元件及主基板的連接構造全體之低背化，亦可削減連接製 程次數。 本發明之中間基板，亦可進行如下的構成。即，具有： 基板核心，包含：藉由高分子材料（包含與陶瓷纖維或粒子 1 等之塡料所複合化的材料作爲槪念）來構成爲板狀，在第一 主表面以減少本身厚度的形狀下開口形成有副核心收容部 的核心本體部；及藉由比核心本體部線膨脹係數更小的材料 來構成爲板狀，並在副核心收容部內以與核心本體部於厚度 方向一致的形狀下所收容之副核心部； 第一端子陣列，包含：形成在基板核心之第一主表面 側’由一方作爲電源端子，另一方作爲接地端子來發揮功能 的第一側第一種端子以及第一側第二種端子；及由第一側信 · 號端子；及 第二端子陣列，包含：形成在基板核心之第二主表面 側’分別導通於第一側第一種端子及第二種端子的第二側第 一種端子及第二側第二種端子；及由導通於第一側信號端子 的第二側信號端子； 且第一端子陣列在對與基板核心之板面平行的基準面 之正射投影中，以在副核心部的投影區域內包含全體之位置 -10- 200539202 f Λ 1 . 關係而形成。 根據上述構成，則包含半導體積體電路元件側及倒裝式 所連接的第一端子陣列之全區域使已調整尺寸的副核心 部，具有埋設於基板核心內的構造，所以對於第一端子陣列 內之全部端子，可充分地來縮小與半導體積體電路元件側的 線膨脹係數差，進而可更不易產生熱應力造成之斷線等。 又，在相當於第一中間基板之核心本體部，由於埋設相當於 第二中間基板的副核心部，所以可達成使用中間基板之半導 體積體電路元件及主基板的連接構造全體之低背化，亦可削 減連接製程次數。 以上本發明之效果，是副核心部與第一端子陣列的形成 區域以同等或大面積所形成的情況下特別顯著。 副核心部比核心本體部線膨脹係數小的話則材質並無 特別的限定。可是，若考慮高分子材料之線膨脹係數較高的 情況等，則副核心部由陶瓷而成作爲陶瓷副核心部，將與縮 小半導體積體電路元件之間的線膨脹係數差之效果來達成 更顯著的觀點是好的情形。 這種情況下，形成陶瓷副核心部的陶瓷，是可使用氧化 鋁（7〜8ppm/°C )或玻璃陶瓷（在硼矽酸鹽系玻璃或硼矽酸 鉛系玻璃將氧化鋁等之無機陶瓷塡料添加40〜60重量部份 的一種複合材料）等。前者是線膨脹係數在各種陶瓷之中特 別的小，與應連接半導體積體電路元件之間的線膨脹係數差 有優越地縮小效果。 又，在氧化鋁，藉由來添加Si、Mn、Ti、Zr及周期表 -11- 200539202 2a族元素等之添加劑，使燒成溫度下降，亦可與含Cu高導 電率材料來同時燒成。作爲具體的添加劑，是用來添加 Si02-Mn02-Ti02-Zr02-Ba0-Mg0，而燒成溫度是在 1 3 5 0°C 以 下（具體而言是125(TC)可進行燒成。另一方面，後者，是容 易低溫燒成，又，根據必要當用來形成金屬配線部或穿孔等 時，優點爲可與將Cu或Ag作爲主體的較低的融點之高導電 率金屬材料同時燒成等的優點。 又，形成陶瓷副核心部的陶瓷，是Si成分之含有率換 算Si02在68質量％以上99質量％以下，Si以外的陽離子成 分係於從室溫到200 °C爲止的溫度範圍內藉由用來形成比 Si〇2線膨脹係數更大的氧化物之氧化物形成陽離子所構 成，從lppm/°C室溫到200°C爲止的平均線膨脹係數調整爲 lppm/°C以上7ppm/°C以下亦可用氧化物系玻璃材料來構成。 從室溫到200°C爲止之溫度範圍內的Si02之線膨脹係 數是大約lppm/°C，非常地小，藉由以含有用來形成比此線 膨脹係數更大的氧化物之氧化物形成陽離子如上述的玻璃 材料，來構成副核心部，與該氧化物形成陽離子種類根據含 有量將玻璃材料之線膨脹係數可自由地調整成lppm/°C以上 的任意値。其結果，使用該玻璃材料之副核心部，與所實際 安裝的半導體積體電路元件可將線膨脹係數差儘可能地來 縮小，藉由倒裝式連接等與半導體積體電路元件可大幅度地 來提高端子連接狀態之可靠性。 成爲連接對象之半導體積體電路元件係Si半導體零件 的情況下，由於Si之線膨脹係數在大約3ppm/°C，所以氧化 200539202 物系玻璃材料的線膨脹係數是lppm以上6ppm以下，特別， 調整爲2PPm/°C以上5ppm/°C以下爲佳。另一方面，成爲連 接對象之半導體積體電路元件係由與GaAs進行格子整合的 I Ϊ I-V族化合物而成之化合物半導體零件的情況下，使該半 導體之線膨脹係數爲5〜6PPm/°C程度，所以氧化物系玻璃 材料的線膨脹係數調整爲4PPm/°C以上7ppm/°C以下爲佳。 任何的情況下，均不易在與實際安裝於副核心部上之半導體 積體電路元件的端子連接構造，產生基於零件/基板間之線 膨脹係數差之熱的剪斷應力之作用，可大幅度來減少連接破 斷等之不合理發生或然率。 這樣情況下，用來構成副核心部之氧化物系玻璃材料 Si 02的含有率在未達68質量％，要將玻璃材料之線膨脹係 數停留在7ppm/°C以下形成困難，與半導體零件之間不能將 線膨脹係數差充分地縮小。超過9 9質量％，則玻璃融點上 昇，氣泡殘留等較小的良質玻璃使玻璃製造成本大增。又， 亦會有難以用來確保玻璃材料之線膨脹係數lppm/°C以上的 情況。 〔實施發明之最佳形態〕 以下，將本發明之實施形態，使用圖式來加以說明。 第1圖，是將形成本發明之一實施形態的中間壓板1， 作爲配置於半導體積體電路元件2及主基板3之間的中間基 板之構成例。又，本實施形態中板狀構件的第一主表面，是 作爲圖中顯現於上側之面，而第二主表面是作爲顯現於下側 之面。 200539202 半導體積體電路元件2是在第二主表面具有各自由複數 的信號端子、電源端子及接地端子而成的元件側端子陣列 4，對於形成於中間基板2 0 0之第一主表面的第一端子陣列 5，介由焊鍚連接部6倒裝式所連接。另一方，主基板3是 成爲母板，或第2段之中間基板的有機層疊封裝基板，皆將 陶瓷粒子或纖維爲塡料所強化的高分子材料構成於主體，由 焊鍚滾球或金屬銷而成之主基板側端子陣列8中，對於形成 於中間基板1的第二主表面之第二端子陣列7，介由焊鍚連 接部9所連接。 如第3圖所示，中間基板200，具有基板核心100，包 含：核心本體部1 〇 〇 m，藉由高分子材料所構成的板狀，在 第一主表面以減低本身厚度的形狀下開口形成有副核心收 容部1 〇〇h ;及陶瓷副核心部1，藉由陶瓷所構成的板狀，在 副核心收容部l〇〇h內以與核心本體部100m在厚度方向一致 的形狀下所收容。在該基板核心1 〇〇之第一主表面側，形成 第1端子陣列5，包含由一方作爲電源端子，另一方作爲接 地端子來發揮功能的第一側第一種端子5 a及第一側第二種 端子5b ;及由第一側信號端子5s。 而且，第一端子陣列5，是對與基板核心1 〇〇之板面平 行的基準面之正射投影中，形成在陶瓷副核心部1的投影區 域內包含全體之位置關係而形成。總之，使第一側第一種端 子5 a、第一側第二種端子5b及第一側信號端子5 s的全體， 在陶瓷副核心部1上與半導體積體電路元件2 (之元件側端 子陣列4)倒裝式所連接。藉此，對於第一端子陣列5內全 200539202 體之端子，與半導體積體電路元件2側可充分地縮小線膨脹 係數差，進而不易大幅產生熱應力造成的斷線等。第3圖之 中間基板200中，使陶瓷副核心部1比第一端子陣列5的形 成區域形成更大面積，可更提高熱應力低減效果。 核心本體部1 〇〇m，譬如，以耐熱性樹脂板（譬如雙馬 來醯亞胺三阱樹脂板），或纖維強化樹脂板（譬如玻璃纖維 強化環氧樹脂）等所構成的板狀。 又，作爲陶瓷副核心部1之構成陶瓷材料，是可使用氧 化鋁（7〜8ppm/°C )或在硼矽酸系玻璃或硼矽酸鉛系玻璃將 鲁 氧化鋁等之無機陶瓷塡料添加40〜60重量份的玻璃陶瓷 等。又，作爲其他陶瓷材料亦可使用氮化鋁、氮化矽、富鋁 紅柱石（mullite)、二氧化矽、氧化鎂等。進而，陶瓷副核 心部1是比核心本體部1 00m更小的線膨脹係數，若可充分 滿足這樣條件的話，則譬如亦可以高分子材料及陶瓷之複合 材料（譬如，比核心本體部的陶瓷重量含有比率高的高分子 材料及陶瓷的複合材料）構成。另一方，作爲參考技術，將 陶瓷副核心部1，從與半導體元件類似線膨脹係數的觀點來 ® 看，亦可置換成矽副核心部。 另一方，成爲陶瓷副核心部之陶瓷，是玻璃材料，譬如 骨格成分亦可用二氧化矽（cilica)也就是二氧化矽系玻璃 所構成。這種情況下，作爲陶瓷電介體爲了進行適合於用途 的物性調整’可用來配合S i Ο 2以外之各種玻璃添加成分。 上述玻璃材料在提高熔融玻璃之流動性，抑制氣泡殘留等的 觀點中’作爲煤熔材成分，是Na2〇、K2〇或Li〇2等之鹼金 -15- 200539202 屬氧化物，或配合B2〇3(硼酸）爲有效。另一方，如添加BaO 或SrO等之鹹土金屬氧化物，則可使玻璃材料的電介率特性 提高。可是，過多的添加，使玻璃之線膨脹係數增大，進而 容易形成引起與零件側之線膨脹係數差的擴大，由於熱應力 會有有關連接不良等的情況。又，藉由玻璃軟化點之上昇使 流動性顯著地下降，會引起氣泡殘留等不適合的情況。 而且，於抑制玻璃之線膨脹係數的增大，提高Si02成 分的含有率，或將ΖηΟ作爲玻璃添加成分來進行配合分別爲 有效。另外，Ti、Zr和Hf之氧化物，除了提高玻璃的電介 率特性之外，在玻璃的耐水性改善亦是有效。可是，過多的 添加，由於玻璃軟化點之上昇使流動性顯著地下降，會引起 氣泡殘留等之不良現象。 二氧化矽系玻璃材料（氧化物系玻璃材料），是S i成 分之含有率換算Si02在68質量％以上99質量％以下，Si以 外之陽離子成分係於從室溫到200 °C爲止的溫度範圍內藉由 形成比Si02線膨脹係數更大之氧化物（以下，稱爲線膨脹 係數調整用氧化物）的氧化物形成陽離子所構成，藉由採用 從 lppm/t：室溫到 200°C爲止之平均線膨脹係數調整爲 1 ρ p m / °C以上7 p p m / °C以下者，根據（線膨脹係數比S i Ο 2更 大）氧化物成分的種類及含有量，將玻璃材料之線膨脹係數 可自由地調整成lppm/°C以上的任意値。其結果，陶瓷副核 心部1，是與所實際安裝之半導體零件1可將線膨脹係數差 儘可能地加以縮小。半導體積體電路元件2爲Si半導體零 件（從室溫到200°C爲止的平均線膨脹係數：3ppm/°C )之 200539202 情況下’一氧化砍系玻璃材料的線膨脹係數是1 以上 6PPm以下，特別，調整爲2ppmrc以上5ppm/t：以下爲佳。 另一方，半導體積體電路元件2亦可是與Ga As格子整合之 I I I-V族化合物而成的化合物半導體零件（譬如GaAs系之 次世代型冋速 CPU 或 MMIC ( Monolithic Microwave Integrated Circuit))來構成，該情況下，該半導體的線膨 脹係數爲5〜6ppm/°C程度，所以二氧化矽系玻璃材料之線 膨脹係數調整爲4 p p m / °C以上7 p p m / °C以下爲佳。200539202 IX. Description of the invention: [Technical area to which the invention belongs] The present invention relates to an intermediate substrate. [Prior Art] [Patent Document 1] Japanese Patent Laid-Open No. 200 1 -03 5966 High-speed semiconductor integrated circuit elements such as CPUs and other LSIs have been miniaturized in recent years, and signal terminals, power terminals, or ground terminals have become smaller. As the number increases, the distance between the terminals also decreases. The technology of connecting the terminal array on the integrated circuit side to the mother board side in a flip-chip manner with most dense terminals is being generalized, but the terminal array on the integrated circuit side and the terminal array on the motherboard side have a large gap between terminals. In order to change this, there must be an intermediate substrate. Among the above-mentioned intermediate substrates, those referred to as organic package substrates have a wiring laminated portion in which a dielectric layer and a conductive layer made of a polymer material are alternately laminated with each other. On the first main surface formed by the interposer layer, a terminal array for flip-chip connection is arranged. The wiring laminated portion is made of a glass fiber-reinforced epoxy resin or the like, and a high-molecular material is formed on a substrate core as a main body. In the case where there is considerable separation between the terminal spacing on the 1C side and the terminal spacing on the main substrate (motherboard) side that is the target of the connection, the number of terminals is also complemented for the wiring or perforation layout pattern that is changed. Increasing the ground will tend to be miniaturized and complicated, but organic package substrates have the advantage of combining high precision and easy formation of such fine and complex wiring patterns by combining photolithography technology and electroplating technology. However, in addition to the main substrate (such as the motherboard) that is the target of the organic packaging substrate, the polymer material is used as the main body. Since the constituent material 200539202 itself also uses the polymer material as the main body, flat soldering is added. Thermal changes such as processing cannot fully absorb the lines of semiconductor integrated circuit elements (linear expansion coefficients, such as 2 to 3 ppm / ° C) and silicon substrates (linear expansion coefficients, such as 17 to 18 ppm ° C) Poor expansion coefficient may cause unsuitable phenomena such as solder peel. On the other hand, Patent Document 1 and the like disclose a ceramic package substrate in which the main material of the substrate is made of ceramic. The use of such a ceramic package substrate can make up for the large linear expansion coefficient difference between the semiconductor integrated circuit components connected to the flip chip and the main substrate, and can effectively prevent soldering with the terminals of the semiconductor integrated circuit components. Defective disconnection at the joint due to thermal stress. [Summary of the Invention] [Disclosure of the Invention] [Problems to be Solved by the Invention] However, since a ceramic package substrate is formed by printing and firing a metal paste on a wiring portion, the wiring portion is formed by an organic package substrate using a photolithography technology. Refinement and high integration are difficult, and there is a limit to the reduction in the terminal spacing on the semiconductor integrated circuit element side. Therefore, it is also conceivable to connect a first intermediate substrate made of an organic package substrate on the main substrate side, and to connect a second intermediate substrate made of ceramics on the first intermediate substrate, and use the second intermediate substrate to A multi-segment substrate connection structure that connects semiconductor integrated circuit elements. However, increasing the number of intermediate substrates increases the size of the substrate connection structure in the height direction. Therefore, it is difficult to meet the requirements of miniaturization, and the number of connection processes is also increased. There will be inefficiencies. The object of the present invention is to provide an intermediate substrate, which makes it difficult to cause breakages such as 200539202 due to thermal stress, and can easily reduce the overall substrate connection structure and reduce the number of connection processes. [Means for Solving the Invention and Effects of the Invention] In order to solve the above-mentioned problems, the intermediate substrate of the present invention has: a substrate core including: a material compounded with a polymer material (including a material compounded with ceramic fibers, particles, and the like) as The core body portion is formed into a plate shape with a sub-core receiving portion opened on the first main surface so as to reduce its thickness; and the plate shape is made of a material having a smaller coefficient of linear expansion than the core body portion. The sub-core portion is contained in the sub-core receiving portion in a form consistent with the thickness direction of the core body portion; the first terminal array includes: formed on the first main surface side of the substrate core, and one side is used as a power terminal , The first terminal of the first side and the second terminal of the first side functioning as the ground terminal; and the signal terminal of the first side; and the second terminal array including: the second terminal formed on the substrate core The main surface side is respectively connected to the second terminal of the first terminal and the second terminal of the second terminal. ; And a second side signal terminal that is electrically connected to the first side signal terminal; characterized in that the first terminal array is in an orthographic projection on a reference plane parallel to the board surface of the substrate core so as to The positional relationship where the projection areas of the parts overlap is formed. According to the above configuration, the area of the semiconductor integrated circuit element side and the area of the first terminal array connected to the flip chip form an overlap, and the sub core portion is made of a material having a smaller coefficient of linear expansion than the core body made of the polymer material. The fixture 200539202 has a structure buried in the core of the substrate, so for the terminals in the first terminal array, the difference in linear expansion coefficient from the side of the semiconductor integrated circuit element can be sufficiently reduced, and it is not easy to cause large thermal stress. Disconnection, etc. In addition, the core body portion corresponding to the first intermediate substrate is used to bury the sub core portion corresponding to the second intermediate substrate. Therefore, it is possible to achieve a low profile of the overall connection structure of the semiconductor integrated circuit element using the intermediate substrate and the main substrate. It can also reduce the number of connection processes. The intermediate substrate of the present invention may be configured as follows. That is, the substrate core includes: a polymer material (including a material compounded with ceramic fibers or particles 1 and the like) as a plate shape, and the first main surface is reduced in thickness. The core body portion of the sub-core receiving portion is formed in the lower opening of the shape; and is formed into a plate shape with a material having a smaller coefficient of linear expansion than the core body portion. A sub-core part accommodated in the shape; a first terminal array including a first type of terminal formed on the first main surface side of the substrate core and having one side as a power terminal and the other as a ground terminal to function; and The second terminal on the first side; and the signal terminal on the first side; and the second terminal array including: the second main surface side formed on the substrate core is respectively connected to the first terminal on the first side and the second terminal The first-type terminal on the second side and the second-type terminal on the second side; and the second-side signal terminal connected to the first-side signal terminal; and the first terminal array Orthographic projection plane parallel to the surface of the core of the plate in order to contain all of the position within the projection area of the sub-core portion is formed -10- 200539202 f Λ 1. Relations. According to the above configuration, the entire area including the semiconductor integrated circuit element side and the first terminal array connected in a flip-chip type has a structure in which the adjusted sub core is embedded in the core of the substrate. All the terminals inside can sufficiently reduce the difference in linear expansion coefficient from the side of the semiconductor integrated circuit element, thereby making it more difficult to cause disconnection due to thermal stress. In addition, since the sub-core portion corresponding to the second intermediate substrate is buried in the core body portion corresponding to the first intermediate substrate, it is possible to reduce the overall connection structure of the semiconductor integrated circuit element using the intermediate substrate and the main substrate. , Can also reduce the number of connection processes. The effects of the present invention described above are particularly significant in the case where the sub-core portion and the formation region of the first terminal array are formed with the same or large area. The material of the sub-core portion having a smaller coefficient of linear expansion than the core body portion is not particularly limited. However, if the linear expansion coefficient of a polymer material is considered to be high, etc., the sub-core portion is made of ceramic as a ceramic sub-core portion, and the effect of reducing the difference in linear expansion coefficient between the semiconductor integrated circuit elements can be achieved. A more significant point is the good situation. In this case, the ceramics forming the ceramic sub-core can be made of alumina (7 ~ 8ppm / ° C) or glass-ceramic (in the case of borosilicate glass or lead borosilicate glass, inorganic materials such as alumina) can be used. A ceramic material is added with a composite material of 40 to 60 parts by weight). The former has a particularly small linear expansion coefficient among various ceramics, and the difference in linear expansion coefficient between the semiconductor integrated circuit components to be connected has an excellent reduction effect. In addition, additives such as Si, Mn, Ti, Zr, and Periodic Table -11-200539202 Group 2a elements are added to alumina to reduce the firing temperature, and it can also be fired simultaneously with Cu-containing high-conductivity materials. As a specific additive, it is used to add Si02-Mn02-Ti02-Zr02-Ba0-Mg0, and the firing temperature is below 1 350 ° C (specifically 125 (TC) can be fired. Another On the other hand, the latter is easy to sinter at low temperature, and when used to form metal wiring parts or perforations, it has the advantage that it can be fired at the same time as high-conductivity metal materials with a lower melting point using Cu or Ag as the main body. In addition, the ceramics forming the sub-core of the ceramic have a Si content of 68% by mass or more and 99% by mass or less, and the cation components other than Si are at a temperature from room temperature to 200 ° C. In the range, it is composed of an oxide forming a cation to form an oxide having a larger linear expansion coefficient than SiO2, and the average linear expansion coefficient from 1 ppm / ° C room temperature to 200 ° C is adjusted to 1 ppm / ° C. The above 7ppm / ° C can also be made of oxide-based glass materials. The linear expansion coefficient of SiO2 in the temperature range from room temperature to 200 ° C is about 1ppm / ° C, which is very small. To form an oxide with a larger coefficient of linear expansion The cation-forming glass material as described above constitutes the sub-core portion, and the cation type with the oxide forms the linear expansion coefficient of the glass material to an arbitrary value of 1 ppm / ° C or more depending on the content. As a result, this is used The sub-core part of glass material can reduce the linear expansion coefficient difference as much as possible with the semiconductor integrated circuit components actually installed, and the terminal connection can be greatly improved by using flip chip connection and semiconductor integrated circuit components. State reliability. In the case of Si semiconductor parts of semiconductor integrated circuit elements to be connected, since the linear expansion coefficient of Si is about 3 ppm / ° C, the linear expansion coefficient of oxidized 200539202 glass materials is 1 ppm to 6 ppm. In the following, in particular, it is preferably adjusted to be 2 PPm / ° C or more and 5 ppm / ° C or less. On the other hand, the semiconductor integrated circuit element to be connected is a compound semiconductor composed of a group of I Ϊ IV compounds that are lattice-integrated with GaAs. In the case of parts, the linear expansion coefficient of the semiconductor is about 5 to 6 PPm / ° C, so the linear expansion of the oxide-based glass material It is better to adjust the coefficient to 4PPm / ° C or more and 7ppm / ° C or less. In any case, it is not easy to produce a terminal connection structure with a semiconductor integrated circuit element actually mounted on the sub-core, resulting in a component / substrate-based The effect of thermal shear stress due to the difference in linear expansion coefficient can greatly reduce the unreasonable probability of occurrence of broken connections, etc. In this case, the content ratio of the oxide-based glass material Si 02 used to form the sub-core portion is between If it is less than 68% by mass, it is difficult to keep the linear expansion coefficient of the glass material below 7 ppm / ° C, and the difference between the linear expansion coefficient and the semiconductor component cannot be sufficiently reduced. If it exceeds 99% by mass, the melting point of the glass will rise, and small good glass, such as bubbles remaining, will greatly increase the glass manufacturing cost. In addition, it may be difficult to ensure a linear expansion coefficient of glass material of 1 ppm / ° C or more. [Best Mode for Carrying Out the Invention] Hereinafter, embodiments of the present invention will be described using drawings. Fig. 1 shows an example of the configuration of an intermediate plate 1 forming an embodiment of the present invention as an intermediate substrate disposed between a semiconductor integrated circuit element 2 and a main substrate 3. In this embodiment, the first main surface of the plate-like member is a surface appearing on the upper side in the figure, and the second main surface is a surface appearing on the lower side. 200539202 The semiconductor integrated circuit element 2 is an element-side terminal array 4 each having a plurality of signal terminals, a power terminal, and a ground terminal on a second main surface. A terminal array 5 is flip-chip connected via a solder pad connection portion 6. On the other hand, the main substrate 3 is an organic laminated package substrate that becomes a mother board or an intermediate substrate in the second stage. All of the main substrates are composed of polymer particles reinforced with ceramic particles or fibers, and are made of solder balls or metal. In the main substrate-side terminal array 8 formed by the pins, the second terminal array 7 formed on the second main surface of the intermediate substrate 1 is connected to each other via a solder joint portion 9. As shown in FIG. 3, the intermediate substrate 200 includes a substrate core 100, which includes a core body portion 100 m, a plate shape made of a polymer material, and is opened on the first main surface to reduce its thickness. A sub-core receiving section 100h is formed; and a ceramic sub-core section 1 is formed in a plate shape made of ceramics in a shape consistent with the thickness of the core body portion 100m within the sub-core receiving section 100h. Contained. A first terminal array 5 is formed on the first main surface side of the substrate core 1000. The first terminal array 5 includes a first side 5a and a first side that function as one power terminal and the other as a ground terminal. The second terminal 5b; and the first side signal terminal 5s. In addition, the first terminal array 5 is formed by ortho-projection of a reference plane parallel to the board surface of the substrate core 1000, and is formed including the entire positional relationship in the projection area of the ceramic sub-core portion 1. In short, the entirety of the first-side first-type terminal 5a, the first-side second-type terminal 5b, and the first-side signal terminal 5s are connected to the semiconductor integrated circuit element 2 (the element side of the ceramic sub-core portion 1). The terminal array 4) is flip-chip connected. Thereby, for the 200539202 terminals in the first terminal array 5, the difference between the linear expansion coefficient and the semiconductor integrated circuit element 2 side can be sufficiently reduced, and furthermore, it is not easy to cause large disconnection caused by thermal stress. In the intermediate substrate 200 of FIG. 3, the ceramic sub-core portion 1 is formed to have a larger area than the formation region of the first terminal array 5, and the thermal stress reduction effect can be further enhanced. The core body 100 m is, for example, a plate-like structure made of a heat-resistant resin plate (such as a double maleimide triple well resin plate) or a fiber-reinforced resin plate (such as a glass fiber-reinforced epoxy resin). In addition, as the constituent ceramic material of the ceramic sub-core portion 1, an inorganic ceramic material such as alumina (7 to 8 ppm / ° C) or alumina can be used in borosilicate glass or lead borosilicate glass. 40 to 60 parts by weight of glass ceramics are added. In addition, as other ceramic materials, aluminum nitride, silicon nitride, mullite, silicon dioxide, magnesium oxide, and the like can be used. Furthermore, the ceramic sub-core portion 1 has a coefficient of linear expansion smaller than 100 m from the core body portion. If such a condition can be sufficiently satisfied, for example, a polymer material and a ceramic composite material (for example, ceramics than the core body portion) may be used. Polymer materials and ceramic composite materials with a high content ratio by weight). On the other hand, as a reference technology, the ceramic sub-core 1 can be replaced with a silicon sub-core from the viewpoint of a linear expansion coefficient similar to that of a semiconductor element. On the other hand, the ceramic that becomes the sub-core of the ceramic is a glass material. For example, the bone composition can also be composed of silicon dioxide (silica) glass. In this case, it is possible to mix various glass addition components other than S i 0 2 as a ceramic dielectric to adjust physical properties suitable for the application. From the viewpoints of improving the fluidity of the molten glass and suppressing the remaining of bubbles, the glass material is an alkali metal of 15-20200539202, such as Na2O, K2O, or Li02, as a component of the coal melting material, or blended with B2. 〇3 (boric acid) is effective. On the other hand, if a salty metal oxide such as BaO or SrO is added, the dielectric properties of the glass material can be improved. However, excessive addition will increase the coefficient of linear expansion of the glass, which will easily lead to an increase in the coefficient of linear expansion from the component side, and may cause poor connection due to thermal stress. In addition, the increase in the softening point of the glass drastically reduces the fluidity, which may cause unsuitable situations such as residual air bubbles. Furthermore, it is effective to suppress an increase in the linear expansion coefficient of glass, increase the content of the SiO2 component, or to mix ZnO as a glass addition component. In addition, the oxides of Ti, Zr, and Hf are effective in improving the water resistance of glass in addition to improving the dielectric properties of glass. However, excessive addition will cause a significant decrease in fluidity due to an increase in the softening point of the glass, which may cause problems such as residual bubbles. Silicon dioxide-based glass materials (oxide-based glass materials) are based on Si content of 68% by mass or more and 99% by mass or less. Cationic components other than Si are at a temperature from room temperature to 200 ° C. In the range, the cation is formed by forming an oxide having a larger coefficient of linear expansion than that of SiO2 (hereinafter, referred to as an oxide for adjusting the coefficient of linear expansion), and by using from 1 ppm / t: room temperature to 200 ° C If the average linear expansion coefficient is adjusted to 1 ρ pm / ° C or more and 7 ppm / ° C or less, the linearity of the glass material is determined based on the type and content of the oxide component (the linear expansion coefficient is larger than S i Ο 2). The expansion coefficient can be freely adjusted to any value above 1 ppm / ° C. As a result, the difference in linear expansion coefficient between the ceramic sub-core portion 1 and the semiconductor component 1 actually mounted can be reduced as much as possible. The semiconductor integrated circuit element 2 is a Si semiconductor part (average linear expansion coefficient from room temperature to 200 ° C: 3ppm / ° C) in 200539202. The linear expansion coefficient of the monolayer glass material is 1 to 6 PPm. In particular, it is adjusted to be 2 ppmrc or more and 5 ppm / t or less: preferably the following. On the other hand, the semiconductor integrated circuit element 2 may also be composed of a compound semiconductor component (such as a next-generation high-speed CPU or MMIC (Monolithic Microwave Integrated Circuit)) of a group II compound integrated with a Ga As lattice. In this case, the linear expansion coefficient of the semiconductor is about 5 to 6 ppm / ° C. Therefore, the linear expansion coefficient of the silicon dioxide-based glass material is preferably adjusted to 4 ppm / ° C or more and 7 ppm / ° C or less.
比Si02線膨脹係數更大的氧化物，是鹼金屬氧化物 (Na20、K20、Li2〇 : 20 〜5 0ppm/°C )、鹼土 類金屬氧化物 (BeO、MgO、CaO、SrO、BaO ： 8 〜15ppm/〇C ) 、ZnO (6ppm/°C ) 、Al2〇3 ( 7ppm/°C )等，可作各種例示，爲了 考慮電介特性或熔點，進而玻璃流動性等若適當選定即可。 還有，Si02之含有率，是因爲將線膨脹係數作爲上述範圍內 者，所以調整爲68質量％以上99質量％以下（較佳是80質 量％以上8 5質量％以下），並將剩餘部可用上述線膨脹係數 調整用氧化物來構成。 以下，是本發明可採用之玻璃組成的具體例：The oxides with a larger linear expansion coefficient than Si02 are alkali metal oxides (Na20, K20, Li20: 20 to 50 ppm / ° C), alkaline earth metal oxides (BeO, MgO, CaO, SrO, BaO: 8 ~ 15ppm / ° C), ZnO (6ppm / ° C), Al2O3 (7ppm / ° C), and the like can be exemplified in various ways. In consideration of dielectric properties or melting points, glass fluidity and the like may be appropriately selected. The content of Si02 is adjusted to be 68% by mass or more and 99% by mass or less (preferably 80% by mass or more by 85% by mass or less) because the linear expansion coefficient falls within the above range. It can be comprised by the said oxide for linear expansion coefficient adjustment. The following are specific examples of glass compositions that can be used in the present invention:
Si02: 80· 9 質量 ％、B2〇3: 12. 7質量％、A12〇3: 2. 3 質量 ％、Na20 : 4 · 0 質量 ％、K2O : 〇 · 〇4 質量 ％、Fe203 : 0 · 0 3質量％、軟化點·· 8 2 1 °C、線膨脹係數（從2 0 °C到2 0 0 °C 之平均値）：3 · 25ppm/°C。 其次，在基板核心1 〇 〇之第二主表面側’是由分別導通 於第一側第一種端子5a及第一側第二種端子5b的第二側第 200539202 一種端子7a及第二側第二種端子7b，及導通於第一側信號 端子5s之第二側信號端子7s而成的第二端子陣列7所形 成。而且，第一端子陣列5，在對與基板核心1 00之板面平 行的基準面（譬如，可設定於基板核心1 〇〇的第一主表面 MP 1本身）之正射投影中，在陶瓷副核心部1的投影區域內 以包含全體之位置關係形成。還有，在副核心收容部1 0Oh 內形成陶瓷副核心部1及核心本體部1 〇〇m的間隙之空間， 形成由高分子材料而成的充塡結合層55。該充塡結合層55 是將陶瓷副核心部1對於核心本體部1 〇〇m來加以固定，同 · 時將陶瓷副核心部1及核心本體部1 〇〇m之面內方向及厚度 方向的線膨脹係數差藉由本身之彈性變形來吸收並發揮功 能。 如第2圖所示，第一端子陣列5中，第一側第一種端子 5 a及第一側第二種端子5b是相互配列成不同的格子狀（或 交錯狀亦可）。同樣第二端子陣列7中，第二側第一種端子 7a及第二側第二種端子7b，配列成對應於第一端子陣列5 之端子配列的相互不同之格子狀（或交錯狀亦可）。還有，# 任何其中的陣列5、7，皆以包圍電源端子及接地端子之格子 狀配列的形態下具有複數之第一側信號端子5 s及第=彻| {言 號端子7s。 第3圖中基板核心100，係核心本體部l〇〇m之第—主 表面和陶瓷副核心部1的弟一'主表面’由尚分子材料而成的 電介體層1〇2，及含配線或接地用或電源用之面導體的導體 層所交替層疊的第一配線層疊部61 (所謂層疊（build-up) -18- 200539202 配線層）所覆蓋，並使第一端子陣列5露出於該第一配線層 疊部6 1之第一主表面（MP 1 )所形成。藉由這樣的構成， 則因爲與核心本體部1 00m —起將陶瓷副核心部1以第一配 線層疊部6 1總括地覆蓋，所以將第一配線層疊部6 1及第一 端子陣列5，與一般的層疊型有機封裝基板大致以同一製程 可形成，有助於製造製程之簡略化。 又，基板核心100之第二主表面（MP2)，是由高分子 材料而成的電介體層1 02，及含配線或接地用或電源用之面 導體的導體層所交替層疊的第二配線層疊部62所覆蓋，並 ® 使第二端子陣列7露出於該第二配線層疊部62之第一主表 面所形成。 任何其中之配線層疊部 61、62中之電介體層102，是 作爲由環氧樹脂等的樹脂組成物而成層疊，厚度譬如形成爲 2〇μιη以上50/xm以下。本實施形態中電介體層1〇2是以環氧 樹脂所構成，由Si02而成的電介體塡料配合成10質量％以 上30質量％以下之比率者，使電介率€調整爲2〜4(譬如3 程度）。又，導體層，是配線及面導體，皆對電介體層1 02 ^ 上作爲圖案電鍍層（譬如電解Cu電鑛層），而厚度譬如形 成爲lOjitm以上20μιη以下。 第3圖中’是對應於第一端子陣列5之第一側第一種端 子5 a及第側桌一種端子5 b，且使分別導通於第二端子陣 列7的第二側第一種端子7a及第二側第二種端子7b之第一 種副核心導體5 1 a及第二種副核心導體5 lb，形成於陶瓷副 核心部1之厚度方向。又，使此等第一種副核心導體5 1 a及 -19- 200539202 第二種副核心導體5 lb，介由以貫穿第一配線層疊部 61的 各電介層1 02之形狀所形成的穿孔導體1 07分別導通於第一 側第一種端子5 a及第一側第二種端子5b所構成。在陶瓷副 核心部1內，以用來並列形成接地用及電源用之導體5 1 a、 5 1 b，可達成接地用及電源用的經路之低電感化進而低阻抗 化。還有，第一種副核心導體5 1 a及第二種副核心導體5 lb， 皆介於穿孔導體1 07，來結合於第二配線層疊部62內的第二 側第一種面導體2 1 1 a及第二側第二種面導體2 1 1 b。進而， 在此等第二側第一種面導體211a及第二側第二種面導體 ® 2 1 1 b，分別來連接前述第二端子陣列7之第二側第一種端子 7a及第二側第二種端子7b。 如上述陶瓷副核心部1，是含有構成陶瓷之原料粉末眾 所周知的陶瓷綠胚片，及藉由在穿孔或雷射穿孔等所形成之 穿孔，藉由用來層疊充塡有金屬粉末膏者來進行燒成，將前 述副核心導體5 1 a、5 1 b (進而後述的5 1 s )作爲層疊穿孔所 形成。 又，配線層疊部61、62之穿孔導體107，是在電介體 ® 層102藉由光穿孔處理（電介體層102是感光性樹脂組成 物，譬如以紫外線硬化型環氧樹脂所構成），或雷射穿孔處 理（電介體層1 02是以非感光性樹脂組成物所構成）等之眾 所周知方法來穿設穿孔，並具有將其內側藉由電鑛等穿孔導 體充塡或覆蓋的構造。還有，任何其中之配線層疊部6 1、62 ’ 皆以露出端子陣列5、7的形狀，由感光性樹脂組成物而成 焊料抗蝕層1 〇 1所覆蓋。 -20- 200539202 如第2圖所示，第一端子陣列5 (及第二端子陣列7 ) 中，各自使第一側第一種端子5a及第一側第二種端子5b配 置在陣列內側區域，第一側信號端子5 s在陣列外側區域。 如第3圖所示，在第一配線層疊部61內，以導通於第一側 信號端子5 s之形狀’設有在陶瓷副核心部1的配置區域之 外側拉出信號傳達經路第一側信號用配線1 08。該第一側信 號用配線1 08之末端，以用來迂回陶瓷副核心部1的形狀來 導通於形成在核心本體部1 00Π1之厚度方向的信號用貫通孔 導體109s。 ® 半導體積體電路元件2之元件側端子陣列4，是信號端 子4s與電源用及接地用的端子4a、4b以同樣的窄間隔所配 置，位於陣列之外周圍部的信號端子4s，是形成於中間基板 2 00之背面側的第二端子陣列內，到對應之第二側信號端子 7 s爲止的面內方向距離亦變大，大多情況下，不得不露出於 陶瓷副核心部1之外。可是，若依據上述構成，則所焊鍚連 接的元件側信號端子4s及第一側信號端子5 s，可定位於線 膨脹係數差顯著縮小效果的陶瓷副核心部1的直接上面， ® 且，對於非常遠的第二側信號端子7s亦無問題可形成導通 狀態。 還有，在核心本體部1 00m所形成之貫通孔導體，是比 形成於配線層疊部6 1、62的穿孔導體1 07之軸剖面徑更大。 這樣的貫通孔導體，譬如將核心本體部1 00m以貫通於板厚 度方向之形狀藉由鑽頭等來穿設貫通孔，並將其內面藉由 Cu電鍍等之金屬層來覆蓋所形成。貫通孔導體之內側藉由 -21 - 200539202 環氧樹脂等的樹脂製孔塡埋材1 〇9f所充塡。進而，貫通孔 導體之兩端面，是藉由導體墊片110所密封。又，穿孔導體 107或導體墊片110，及電源層或接地層等的面導體欲達成 直流式的分離情況下，用來形成形成於該面導體之孔部 1 〇7i，在其內側以隔著圓環狀的間隙之形狀來配置穿孔導體 107或導體墊片110即可。 還有，第3圖之中間基板200中，副核心收容部100h 是以貫通核心本體部1 〇〇m的形態所構成，而第二配線層疊 部62是與收容於副核心收容部1 00h之陶瓷副核心部1的第 ® 二主表面接觸所形成。這樣的構成，是由陶瓷副核心部1之 位置，排除線膨脹係數大的高分子材料成爲主體之核心本體 部100m，所以可達成半導體積體電路元件2及中間基板200 之間的線膨脹係數差更顯著地縮小效果。 以下，對於本發明之中間基板的各種變形例來加以說 明。還有，以下構成中，與第3圖之中間基板200同樣所構 成的部分，是賦予共通的符號並省略其詳細說明。首先，第 4圖之中間基板300，是其副核心收容部100h，作爲開口於 ® 核心本體部1 〇〇m的第一主表面之有底凹狀部所構成。第二 配線層疊部62，是在該凹狀部的背面側與核心本體部1 〇〇m 之第二主表面進行連接所形成。這樣的構造，是在核心本體 部1 00m之第二主表面側不使陶瓷副核心部1露出，所以具 有可將平坦的第二配線層疊部62更簡便形成之優點。具體 而言，核心本體部l〇〇m係以貫通成爲副核心收容部i〇〇h 的底部之部分形狀，形成與形成第二端子陣列7的各端子導 -22- 200539202 通之底部貫通孔導體部209，而形成於陶瓷副核心部1的各 副核心導體5 1 a、5 1 b是導通於該等底部貫通孔導體部 209。更詳細而言，底部貫通孔導體部209側之墊片80 ’及 副核心導體側的墊片70介由焊鍚連接部6成爲倒裝式所連 接的形態。 其次，第5圖之中間基板4 0 0，是在第一端子陣列5的 第一側第一種端子5 a及第一側第二種端子5 b使各自導通的 第一側第一種面導體Ilia及第一側第二種面導體111b，在 第一配線層疊部6 1內，分別與陶瓷副核心部1 一起以覆蓋 核心本體部1 00m之第一主表面的形狀所形成。又，此等第 一側第一種面導體1 1 1 a及第一側第二種面導體1 1 1 b，是以 迂回陶瓷副核心部1之形狀分別來導通於形成在核心本體部 100m的厚度方向所形成之第一種貫通孔導體l〇9a及第二種 貫通孔導體 1 〇9b。藉由這樣的構成，則在陶瓷副核心部1 內，未形成導通於第一側第一種端子5 a及第一側第二種端 子5b之副核心導體。Cu等之導體用金屬是線膨脹係數較 大，藉由上述構成，則可使金屬製之副核心導體的形成體積 率減少，所以可減小陶瓷副核心部1全體之平均的線膨脹係 數，進而，更顯著地可達成半導體積體電路元件2及中間基 板200之間的線膨脹係數差之縮小效果。還有，第一種貫通 孔導體l〇9a及第二種貫通孔導體109b，皆介由穿孔導體 1 07，並結合於第二配線層疊部62內的第二側第一種面導體 211a及第二側第二種面導體211b。 這種情況下，第一端子陣列5中，如第2圖，分別使第 -23- 200539202 嫁齡 ·- 一側第一種端子5 a及第一側第二種端子5b配置在陣列內側 區域，使第一側信號端子5 s配置在陣列外側區域的情況下’ 是與第3圖同樣，以導通於第一側信號端子5 s的形狀在第 一配線層疊部61內，可裝設在陶瓷副核心部1之配置區域 的外側來拉出信號傳達經路的第一側信號用配線1 〇8。該第 一側信號用配線1 08的末端，是以迂回陶瓷副核心部1之形 狀可導通於形成在核心本體部1 〇〇m的厚度方向之信號用貫 通孔導體1 〇9a。藉由這樣構成，從陶瓷副核心部1可完全地 排除副核心導體，由於可用陶瓷之無垢板來構成，所以不僅 ® 提高半導體積體電路元件2及中間基板200之間的線膨脹係 數差之縮小效果，而且可大幅度地簡略化陶瓷副核心部1的 製造製程。 第6圖之中間基板500，是將第5圖的中間基板400與 第4圖之中間基板3 00形成同樣，將副核心收容部1 00h，作 爲開口於核心本體部1 00m之第一主表面的有底凹狀部所構 成的例。於此，在陶瓷副核心部1未形成副核心導體，因此， 在成爲副核心收容部1 〇〇h之底部的部分是未形成第4圖之 β 底部貫通孔導體部 209。 其次，第7圖之中間基板600，係將構成第一端子陣列 5的第一側第一種端子5 a及第一側第二種端子5 b露出於陶 瓷副核心部1之第一主表面上所形成。又，對應於第一端子 陣列5的第一側第一種端子5a及第一側第二種端子5b，且 在第二端子陣列7之第二側第一種端子7a及第二側第二種 端子7b使分別導通的第一種副核心導體5 1 a及第二種副核 -24- 200539202 * . * . 心導體5 1 b，形成於該陶瓷副核心部1之厚度方向。藉由這 種構成，從陶瓷副核心部1的第一主表面，排除將高分子材 料作爲主體之第一配線層疊部 6 1，並使半導體積體電路元 件2及陶瓷副核心部1藉由焊鍚連接部6所直接連接。藉此’ 用來更提高半導體積體電路元件2及中間基板200之間的線 膨脹係數差之縮小效果。又，在陶瓷副核心部1的直接上面’ 未圍上導通於端子之配線，所以可達成導通於該端子的傳送 經路之低電感化進而低阻抗化。還有，本實施形態的中間基 板600中，是未形成第一側配線層疊部。 第7圖之中間基板600中，使用來構成第一端子陣列5 的第一側信號端子5s露出於陶瓷副核心部1之第一主表面 上所形成，對應於該第一側信號端子5 s，且使導通於第二端 子陣列7之第二側信號端子7s的信號用副核心導體5 1 s，在 該陶瓷副核心部1之厚度方向所形成。這樣構成，是第一端 子陣列5的端子間距離在沒有那麼小的情況下可採用，對於 信號端子亦形成副核心導體5 1 s，所以不僅接地用及電源用 之傳送經路，亦可達成信號用的傳送經路之低電感化進而低 阻抗化。 另一方，第1 1圖之中間基板1 〇〇〇中，陶瓷副核心部1 的第一主表面之外周緣部，與核心本體部l〇〇m的第一主表 面一起，係由高分子材料而成的電介體層1 02，和含配線或 接地用或電源用之面導體的導體層所交替地層疊之第一配 線層疊部61所覆蓋。第一側信號端子5s，是以露出於第一 配線層疊部61表面的形狀所形成。而且，以導通於第一側 -25- 200539202 信號端子5s之形狀在第一配線層疊部61內’在陶瓷副核心 部1的配置區域之外側裝設拉出丨目號傳達經路之弟一側丨目號 用配線108。第一側信號用配線108的末端’是以廷回陶瓷 副核心部1之形狀下來導通於形成在核心本體部1 00m的厚 度方向之信號用貫通孔導體l〇9s°這樣構成’是可將導通 於陣列外周圍部的信號用端子之配線大大地拉出到面內外 方，所以在第一端子陣列5的端子間距離小的情況下可說有 利。 第8圖之中間基板7 〇 〇，是將第3圖的配線基板2 0 0之 β 陶瓷副核心部1在面內方向進而進行擴張’同時對應於第一 端子陣列5的第一側信號端子5s，且將導通於第二端子陣列 7之第二側信號端子7s的信號用副核心導體5 1 s ’形成於副 核心部1之厚度方向的例。 又，以上之實施形態中，皆使副核心部1比半導體積體 電路元件1形成更大面積，但亦可將副核心部1與半導體積 體電路元件1的投影區域大致形成同面積。進而，如第9圖 之中間基板8 00，將第一端子陣列5的全體收容在副核心部 Φ 1之區域內，亦可將副核心部1來構成比半導體積體電路元 件1更小面積。又，對於位於比半導體積體電路元件1更外 周的端子中的焊鍚連接部6之連接狀態的影響沒有那麼掛念 的情況下，如第1 〇圖之中間基板900，並非不可能比第一端 子陣列5的區域將副核心部1構成更小面積。 【圖式之簡單說明〕】 第1圖是顯不本發明之中間基板的使用形態一例之側面 -26- 200539202 * . ·. 模式圖。 第2圖是顯示第1圖之中間基板的第一端子陣列之配置 形態一例的平面圖。 第3圖是顯示本發明之中間基板的第一實施形態之剖面 模式圖。 第4圖是顯示同樣第二實施形態之剖面模式圖。 第5圖是顯示同樣第三實施形態之剖面模式圖。 第6圖是顯示同樣第四實施形態之剖面模式圖。 第7圖是顯示同樣第五實施形態之剖面模式圖。 鲁 第8圖是顯示同樣第六實施形態之剖面模式圖。 第9圖是顯示本發明之中間基板的第七實施形態之剖面 模式圖。 第1 〇圖是顯示本發明之中間基板的第八實施形態之剖 面模式圖。 第1 1圖是顯示本發明之中間基板的第九實施形態之剖 面模式圖。 【元件符號說明】 ® 1 ...陶瓷副核心部 5…第一端子陣列 5 a…第一側第一種端子 5b…第一側第二種端子 7…第二端子陣列 7a…第二側第一種端子 7b…第二側第二種端子 -27- 200539202 5 la...第一種副核心導體 5 lb...第二種副核心導體 5 Is...信號用副束導體 6 1...第一配線層疊部 100…基板核心 100h...副核心收容部 100m…核心本體部 102…電介體層Si02: 80 · 9% by mass, B2〇3: 12.7% by mass, A12〇3: 2.3% by mass, Na20: 4.0% by mass, K2O: 〇 · 〇4% by mass, Fe203: 0 · 0 3% by mass, softening point 8 2 1 ° C, coefficient of linear expansion (average 値 from 20 ° C to 200 ° C): 3 · 25 ppm / ° C. Secondly, on the second main surface side of the substrate core 100, the second side of the first side first terminal 5a and the first side second terminal 5b are electrically connected to the second side 200539202 one terminal 7a and the second side. The second terminal 7b is formed by a second terminal array 7 formed by conducting the second side signal terminal 7s of the first side signal terminal 5s. Furthermore, the first terminal array 5 is orthographically projected on a reference plane parallel to the plate surface of the substrate core 100 (for example, the first main surface MP 1 itself which can be set on the substrate core 100) in ceramics. The projection area of the sub core portion 1 is formed in a positional relationship including the entirety. In addition, a space of 100 m between the ceramic sub-core portion 1 and the core body portion 100 is formed in the sub-core receiving portion 100h to form a filling and bonding layer 55 made of a polymer material. This filling and bonding layer 55 fixes the ceramic sub-core part 1 to the core body part 1000 m, and simultaneously fixes the ceramic sub-core part 1 and the core body part 1000 m in the plane direction and thickness direction. The linear expansion coefficient difference is absorbed and functions by its elastic deformation. As shown in FIG. 2, in the first terminal array 5, the first-side first-type terminal 5 a and the first-side second-type terminal 5 b are arranged in a different grid shape (or staggered shape). Similarly, in the second terminal array 7, the second-side first-type terminal 7a and the second-side second-type terminal 7b are arranged in different grid shapes (or staggered shapes) corresponding to the terminal arrangement of the first terminal array 5. ). In addition, # any of the arrays 5 and 7 has a plurality of first-side signal terminals 5 s and the first full signal terminal 7s in a grid-like arrangement surrounding the power terminals and the ground terminals. The substrate core 100 in FIG. 3 is the first main surface of the core body 100m—the main surface and the main surface of the ceramic sub-core portion 1—a dielectric layer 10 made of a still molecular material and containing The first wiring lamination portion 61 (the so-called build-up -18- 200539202 wiring layer) alternately laminated with the conductor layers of the surface conductors for wiring, grounding, or power supply, and the first terminal array 5 is exposed on A first main surface (MP 1) of the first wiring laminated portion 61 is formed. With such a configuration, since the ceramic sub-core portion 1 is collectively covered with the first wiring laminated portion 61 with the core body portion 100m, the first wiring laminated portion 61 and the first terminal array 5 are covered. It can be formed in approximately the same process as a general multilayer organic package substrate, which helps simplify the manufacturing process. In addition, the second main surface (MP2) of the substrate core 100 is a second wiring alternately laminated with a dielectric layer 102 made of a polymer material and a conductor layer including a surface conductor for wiring or grounding or power supply. The second terminal array 7 is covered by the laminated portion 62 and is formed by exposing the second terminal array 7 on the first main surface of the second wiring laminated portion 62. The dielectric layer 102 in any one of the wiring laminated portions 61 and 62 is laminated as a resin composition such as an epoxy resin and has a thickness of, for example, 20 μm to 50 / xm. In this embodiment, the dielectric layer 10 is made of epoxy resin, and a dielectric material made of SiO 2 is blended to a ratio of 10% by mass to 30% by mass, so that the dielectric ratio € is adjusted to 2 ~ 4 (for example, 3 degrees). In addition, the conductor layer is a wiring and a surface conductor, and is a pattern plating layer (such as an electrolytic Cu ore layer) on the dielectric layer 10 02 ^, and has a thickness of 10 μm to 20 μm, for example. In the third figure, 'the first type terminal 5a corresponding to the first side of the first terminal array 5 and the first type terminal 5b of the side table, and are respectively connected to the first terminal of the second side of the second terminal array 7 The first sub core conductor 5 1 a and the second sub core conductor 5 lb of 7a and the second terminal 7b on the second side are formed in the thickness direction of the ceramic sub core portion 1. In addition, these first sub core conductors 5 1 a and -19-200539202 were formed as the second sub core conductors 5 lb through the shape of each dielectric layer 102 passing through the first wiring laminated portion 61. The through-hole conductor 107 is constituted by being electrically connected to the first-type first terminal 5a and the first-type second terminal 5b. In the ceramic sub-core portion 1, conductors 5 1 a and 5 1 b for grounding and power supply are formed in parallel to achieve low inductance and low impedance of the grounding and power supply pathways. In addition, the first type of sub-core conductor 5 1 a and the second type of sub-core conductor 5 lb are interposed between the perforated conductor 107 and the second type first surface conductor 2 in the second wiring laminated portion 62. 1 1 a and second surface conductor 2 1 1 b on the second side. Furthermore, the second-side first-type surface conductor 211a and the second-side second-type surface conductor® 2 1 1 b are connected to the second-side first-type terminal 7a and the second-side of the second terminal array 7 respectively. Side second terminal 7b. As mentioned above, the ceramic sub-core part 1 is a well-known ceramic green embryo containing raw material powder constituting ceramics, and a perforation formed by perforation or laser perforation, etc. The firing is performed, and the sub-core conductors 5 1 a and 5 1 b (and further 5 1 s described later) are formed as laminated through-holes. In addition, the perforated conductors 107 of the wiring laminated portions 61 and 62 are subjected to photoperforation treatment on the dielectric® layer 102 (the dielectric layer 102 is a photosensitive resin composition such as an ultraviolet curable epoxy resin), Or laser perforation treatment (the dielectric layer 102 is made of a non-photosensitive resin composition) and other well-known methods for perforation, and has a structure in which the inside is filled or covered with a perforated conductor such as a power mine. In addition, any of the wiring laminated portions 6 1 and 62 ′ is covered with a solder resist layer 101 made of a photosensitive resin composition in a shape exposing the terminal arrays 5 and 7. -20- 200539202 As shown in FIG. 2, in the first terminal array 5 (and the second terminal array 7), the first-side first-type terminal 5a and the first-side second-type terminal 5b are respectively arranged in the area inside the array. , The first side signal terminal 5 s is in the area outside the array. As shown in FIG. 3, in the first wiring lamination portion 61, the signal transmission path is provided in a shape that is connected to the first-side signal terminal 5 s. Side signal wiring 1 08. The end of the first-side signal wiring 108 is routed to the signal through-hole conductor 109s formed in the thickness direction of the core body portion 100Π1 so as to bypass the shape of the ceramic sub-core portion 1. ® Semiconductor-integrated circuit element 2 element-side terminal array 4, signal terminals 4s and power terminals and ground terminals 4a, 4b are arranged at the same narrow interval, and signal terminals 4s located outside the array are formed. In the second terminal array on the back side of the intermediate substrate 200, the in-plane distance to the corresponding second-side signal terminal 7 s also becomes larger, and in most cases, it has to be exposed outside the ceramic sub-core 1 . However, according to the above configuration, the element-side signal terminals 4s and the first-side signal terminals 5s connected to the solder joints can be positioned directly above the ceramic sub-core portion 1 having a significantly reduced linear expansion coefficient difference, and, The second side signal terminal 7s, which is very far away, can be turned on without any problem. The through-hole conductor formed in the core body portion 100m has a larger axial cross-sectional diameter than the through-hole conductor 107 formed in the wiring laminated portions 61 and 62. Such a through-hole conductor is formed, for example, by penetrating a core body 100 m through a through-hole with a drill or the like in a thickness direction, and covering the inner surface with a metal layer such as Cu plating. The inside of the through-hole conductor is filled with a resin hole-buried material 109f, such as -21-200539202 epoxy resin. Further, both end surfaces of the through-hole conductor are sealed by a conductor gasket 110. In addition, in the case where the perforated conductor 107 or the conductor pad 110 and the surface conductor such as the power supply layer or the ground layer are to be separated from each other in a DC type, a hole portion 107i formed in the surface conductor is formed with a space between them. It is sufficient to arrange the perforated conductor 107 or the conductor pad 110 in the shape of the annular gap. In the intermediate substrate 200 shown in FIG. 3, the sub-core storage section 100h is configured to penetrate the core body section 100m, and the second wiring stacking section 62 is stored in the sub-core storage section 100h. The second major surface of the ceramic sub-core 1 is formed by contact. Such a configuration is based on the position of the ceramic sub-core portion 1 and excludes a polymer material having a large linear expansion coefficient as the main body of the core body 100m. Therefore, the linear expansion coefficient between the semiconductor integrated circuit element 2 and the intermediate substrate 200 can be achieved. The difference is more significantly reduced. Hereinafter, various modifications of the intermediate substrate of the present invention will be described. In the following configurations, the same components as those of the intermediate substrate 200 shown in FIG. 3 are given the same reference numerals and detailed descriptions thereof are omitted. First, the intermediate substrate 300 shown in FIG. 4 is a sub-core receiving portion 100h, which is constituted as a bottomed concave portion opening at the first main surface of the ® core body portion 1000m. The second wiring laminated portion 62 is formed by connecting the second main surface of the core body portion 1000m on the back side of the concave portion. This structure has the advantage that the ceramic sub-core portion 1 is not exposed on the second main surface side of the core body portion 100m, so that the flat second wiring laminated portion 62 can be formed more easily. Specifically, the core body 100m is formed in a shape of a portion penetrating the bottom of the sub-core receiving portion 100h, and forms a bottom through-hole through which each of the terminal guides 22-200539202 forming the second terminal array 7 passes. The conductor portion 209 is formed by the respective sub-core conductors 5 1 a and 5 1 b formed in the ceramic sub-core portion 1. More specifically, the gasket 80 'on the bottom through-hole conductor portion 209 side and the gasket 70 on the sub-core conductor side are connected to each other via the solder joint portion 6 in a flip-chip manner. Next, the intermediate substrate 4 0 in FIG. 5 is a first side first surface of the first side 5 a and a second side terminal 5 b of the first side of the first terminal array 5. The conductor Ilia and the first-side second-type surface conductor 111b are formed in the first wiring laminated portion 61 together with the ceramic sub-core portion 1 so as to cover the first main surface of the core body portion 100m. In addition, these first-side first-type surface conductors 1 1 1 a and first-side second-type surface conductors 1 1 1 b are respectively connected to the core body portion 100m formed in the shape of the detour ceramic sub-core portion 1. The first type of through-hole conductor 109a and the second type of through-hole conductor 109b are formed in the thickness direction of. With such a configuration, in the ceramic sub-core portion 1, no sub-core conductors that are conducted to the first-side first-type terminal 5a and the first-side second-type terminal 5b are formed. The metal for conductors such as Cu has a large linear expansion coefficient. With the above configuration, the formation volume ratio of the metal sub-core conductor can be reduced. Therefore, the average linear expansion coefficient of the entire ceramic sub-core portion 1 can be reduced. Furthermore, the effect of reducing the linear expansion coefficient difference between the semiconductor integrated circuit element 2 and the intermediate substrate 200 can be achieved more significantly. In addition, the first type of through-hole conductor 109a and the second type of through-hole conductor 109b are both connected to the second-side first type surface conductor 211a and The second-side second-type surface conductor 211b. In this case, in the first terminal array 5, as shown in FIG. 2, the -23- 200539202 marrying age ·-side of the first terminal 5 a and the first-side second terminal 5 b are arranged in the area inside the array. In the case where the first-side signal terminal 5 s is arranged in the outer area of the array, as in FIG. 3, the first-side signal terminal 5 s is connected to the first-side signal terminal 5 s in the first wiring stacking portion 61 and can be installed in The first-side signal wiring 108 for the signal transmission path is pulled out of the ceramic sub-core portion 1 outside the arrangement area. The end of the first-side signal wiring 108 is a signal through-hole conductor 1 09a which is formed in a shape of a bypass ceramic sub-core portion 1 and can be conducted to a thickness direction of the core body portion 100m. With this structure, the sub-core conductor can be completely excluded from the ceramic sub-core portion 1, and since it can be composed of a ceramic scale plate, it not only improves the difference in linear expansion coefficient between the semiconductor integrated circuit element 2 and the intermediate substrate 200 The effect is reduced, and the manufacturing process of the ceramic sub-core portion 1 can be greatly simplified. The intermediate substrate 500 shown in FIG. 6 is the same as the intermediate substrate 400 shown in FIG. 5 and the intermediate substrate 300 shown in FIG. 4. The sub-core receiving portion 100 h is used as the first main surface of the core body 100 m. Example of a bottomed concave portion. Here, since the sub-core conductor is not formed in the ceramic sub-core portion 1, the portion that becomes the bottom of the sub-core receiving portion 100h is the β bottom through-hole conductor portion 209 of FIG. 4 that is not formed. Next, the intermediate substrate 600 in FIG. 7 exposes the first-side first-type terminal 5 a and the first-side second-type terminal 5 b constituting the first terminal array 5 on the first main surface of the ceramic sub-core portion 1. On the formation. In addition, the first terminal 5a and the second terminal 5b on the first side of the first terminal array 5 correspond to the first terminal 7a and the second terminal on the second side of the second terminal array 7. The seed terminal 7b allows the first type of sub core conductor 5 1 a and the second type of sub core 24-200539202 *. *. Core conductor 5 1 b to be conducted, respectively, and is formed in the thickness direction of the ceramic sub core portion 1. With this configuration, the first main wiring lamination section 61, which is made of a polymer material as the main body, is excluded from the first main surface of the ceramic sub-core section 1, and the semiconductor integrated circuit element 2 and the ceramic sub-core section 1 are passed through. The welding pad connection portion 6 is directly connected. This is used to further improve the effect of reducing the linear expansion coefficient difference between the semiconductor integrated circuit element 2 and the intermediate substrate 200. In addition, since the wiring connected to the terminal is not directly surrounded by the ceramic sub-core portion 1, it is possible to achieve a low inductance and a low impedance of the transmission path leading to the terminal. In the intermediate substrate 600 of this embodiment, the first-side wiring laminated portion is not formed. In the intermediate substrate 600 of FIG. 7, the first-side signal terminals 5 s used to constitute the first terminal array 5 are formed on the first main surface of the ceramic sub-core portion 1, corresponding to the first-side signal terminals 5 s. A sub core conductor 5 1 s for a signal that is conducted to the second side signal terminal 7 s of the second terminal array 7 is formed in the thickness direction of the ceramic sub core portion 1. This structure can be adopted when the distance between the terminals of the first terminal array 5 is not so small, and the sub-core conductor 5 1 s is also formed for the signal terminals. Therefore, it can be used not only for the grounding and power transmission paths, but also for The signal transmission path has low inductance and low impedance. On the other hand, in the intermediate substrate 1000 shown in FIG. 11, the outer peripheral part of the first main surface of the ceramic sub-core part 1 is made of polymer together with the first main surface of the core body part 100 m. The dielectric layer 102 made of a material is covered with a first wiring laminated portion 61 which is alternately laminated with a conductor layer including a surface conductor for wiring, grounding, or power supply. The first-side signal terminal 5s is formed in a shape exposed on the surface of the first wiring laminated portion 61. Moreover, in the shape of being connected to the first side -25- 200539202 signal terminal 5s, a pull-out is installed inside the first wiring lamination section 61 'outside the arrangement area of the ceramic sub-core section 1' The side 丨 head number wiring 108. The end of the signal wiring 108 on the first side 'is formed in the shape of the ceramic core sub-core 1 and is connected to the signal through-hole conductor 109 s ° formed in the thickness direction of the core body 100 m. The wiring of the signal terminals that are conducted to the outer peripheral portion of the array is largely pulled out to the outside and in the plane, so it is advantageous when the distance between the terminals of the first terminal array 5 is small. The intermediate substrate 7 of FIG. 8 is a β ceramic sub-core portion 1 of the wiring substrate 200 of FIG. 3 is further expanded in the plane direction, and corresponds to the first side signal terminals of the first terminal array 5 5 s, and an example in which the sub core conductor 5 1 s ′ for a signal that is conducted to the second side signal terminal 7 s of the second terminal array 7 is formed in the thickness direction of the sub core portion 1. In the above embodiments, the sub core portion 1 is formed to have a larger area than the semiconductor integrated circuit element 1. However, the projection area of the sub core portion 1 and the semiconductor integrated circuit element 1 may be formed to have approximately the same area. Further, as in the intermediate substrate 800 of FIG. 9, the entire first terminal array 5 is housed in the area of the sub core portion Φ 1, and the sub core portion 1 may be configured to have a smaller area than the semiconductor integrated circuit element 1. . In addition, in the case where the influence of the connection state of the solder pad connection portion 6 in the terminal which is more peripheral than the semiconductor integrated circuit element 1 is not so concerned, as in the intermediate substrate 900 in FIG. 10, it is not impossible to compare with the first substrate The area of the terminal array 5 configures the sub core portion 1 to a smaller area. [Brief description of the drawing] Figure 1 is a side view showing an example of the use form of the intermediate substrate of the present invention. -26- 200539202 *... Fig. 2 is a plan view showing an example of an arrangement form of a first terminal array of the intermediate substrate of Fig. 1; Fig. 3 is a schematic sectional view showing a first embodiment of the intermediate substrate of the present invention. Fig. 4 is a schematic sectional view showing the second embodiment. Fig. 5 is a schematic sectional view showing the third embodiment. Fig. 6 is a schematic sectional view showing the fourth embodiment. Fig. 7 is a schematic sectional view showing the fifth embodiment. Fig. 8 is a schematic sectional view showing the same sixth embodiment. Fig. 9 is a schematic sectional view showing a seventh embodiment of the intermediate substrate of the present invention. Fig. 10 is a schematic sectional view showing an eighth embodiment of the intermediate substrate of the present invention. Fig. 11 is a schematic sectional view showing a ninth embodiment of the intermediate substrate of the present invention. [Description of component symbols] ® 1 ... ceramic sub-core 5 ... first terminal array 5 a ... first side first terminal 5b ... first side second terminal 7 ... second terminal array 7a ... second side First type terminal 7b ... Second type second terminal-27- 200539202 5 la ... First type of sub core conductor 5 lb ... Second type of sub core conductor 5 Is ... Sub beam conductor 6 for signal 1 ... first wiring stacking section 100 ... substrate core 100h ... sub-core receiving section 100m ... core body section 102 ... dielectric layer
107…穿孔導體 108...第一側信號用配線 109a...第一種貫通孔導體 109b…第二種貫通孔導體 l〇9s...信號用貫通孔導體 11 la...第一側第一種面導體 11 lb...第一側第二種面導體 200、300、400、500、600、700、800、900、1000 …中間基板107 ... through-hole conductor 108 ... first side signal wiring 109a ... first type through-hole conductor 109b ... second type through-hole conductor 109s ... signal through-hole conductor 11 la ... first 1st type surface conductor on the side 11 lb ... 2nd type surface conductor on the first side 200, 300, 400, 500, 600, 700, 800, 900, 1000 ... intermediate substrate
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