200537642 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種半導體製程方法，尤指一種在溝渠電容動態唯讀記憶 體(Trench-DRAM)製程中，使用犧牲多晶矽層以及旋塗玻璃(sphw)nglass， SOG)層，於兩閘極導體堆疊結構間製作位元線接觸洞之方法。 【先前技術】 如該行業者所知，溝渠電容動態唯讀記憶體其係在半導體基材中挖深溝 渠，再以繁複的半導體製程於深溝渠内製成溝渠電容元件◦而隨著電子產 品朝體積小型化的高積集度方向發展，高密度溝渠電容動態唯讀記憶體的 設計使得記憶體陣列中的元件與元件之間的距離以及導線與導線之間的距 離越來越靠近，密度增加的結果不但造成相鄰導線之間的電容耦合(c〇upKng) 情形惡化，在微影製程上，亦增加微小圖案，如位元線接觸洞等，進行轉 移時的困難度。 圖一至圖五顯示習知技藝於兩閘極導體結構12與14之間製作位元線接 觸洞之方法。如圖一所示，在半導體基底1〇的主表面u上形成有至少兩 閘極導體(GateConductor，GC)堆疊結構12與14。一般，閘極導體堆疊結 構12與14皆包含有一閘極氧化層22、導電層24以及氮化矽蓋層％。在 基底10表面上可大致區分為位元線接觸洞區域42以及非位元線接觸洞區 域44其中位元線接觸洞區域42在閘極導體堆疊結構12與μ之間的上方。 形成閘極導體堆疊結構12與14之後，接著於基底1〇表面上沈積一氮化矽 襯墊層^隨後再沈積一硼磷矽玻璃作⑽沖沉沖⑽出咖典^別抑層 36 ° 如圖一所示，進行一化學機械研磨(CMp)製程，將硼麟石夕玻璃層36平 坦化至氮化;5夕襯墊層32。如圖三所示，接著於硼磷矽玻璃層36以及氮化矽 10 200537642 襯墊層32上沈積-四乙氧基矽烷(TE〇s)石夕氧層3 烧石夕氧層38上以黃光製程形成光阻圖案幻H四乙^夕 露問極導體堆疊、_與14之壯㈣位元、區=，恰好暴 、/^ 進订―非等向性乾綱製裎，彻光闕案52為一蝕刻 遮罩，經由開口 54敍刻四乙氧基魏石夕氧層38、_石夕玻璃声3 ^ 於位元線接觸洞區域42形成—位元線接觸洞62。同時鼠 ==堆$、纟_與14 _上形成氮化補壁子w。_去除光 啸=Γ6Γ Γ再於位元線接觸洞62填人金屬輸料，形成位元 、、泉接觸插基64。-m雜觸隸64從基底1G社表面η 麵埃左右的高度。四乙氧基魏魏層38的厚賴為3_埃左右。 十抽=丨則述之白知技藝部存有下列缺點。由於位元線接觸洞區域42尺 Τ越來越小的結果，例如當賴到9G奈米技術節點，要以傳統的普光 ==精準地曝出位元線接觸洞圖案十分困難，有時候需要搭配成像補 mentTechnoIogy，IET)才能曝出所要的圖案，因而造 谷斗度(processwmdow)偏低，況且，以目前傳統乾姓刻製程經由如 *米尺寸的接觸酿壯前述刪埃左右深度的四乙氧基魏魏層、 删磷矽，璃層36以及氮化矽襯墊層32亦可能有清除不完全之情形^生。 此外4述之t知技藝的另—缺‘點是位元線接觸插塞64與間極導體堆疊結 構’、14的導^•層24之間為氮化石夕側壁子64，因此在操作時產生的寄生 電容較高，並有RC延遲效應之顧慮。 【發明内容】 因此’本發明之主要目的在提供—種在溝渠電容誠唯讀記憶體 (Trench-DRAM)製程中’使用犧牲多晶砍層以及旋塗玻璃(spin〇n抑ss，s〇g) 11 200537642 ，而可解決前述習知技 f於兩卩雜導體結構間製作位元線接觸洞之方法 藝的問題。 包人如 1之較佳實施例，本發明提供一種製作位元線接觸洞之方法， 體:疊結構，其^^一主表面’於該主表面上形成有相鄰兩閘極導 二士二二“土 &區分有一位元線接觸洞區域設於相鄰兩閘極導體堆 :口構之關上方，射各該導體堆疊結構具有—上表面以及垂直側 二卞於刻鱗體轉賴上表㈣及餘麵上沈積二氧切概塾層； 見墊層上沈積一犧牲層；進行一第一化學_^ ^義牲層研料坦導體堆疊賴社絲停止；於該齡層以及 Τ閑極導，堆登結構的上表面上形成—旋塗玻璃(so⑺層，·於該旋塗玻璃層 ，形成-光阻B案，其遮蓋雜元線接觸願域；該光阻圖案為餘 刻硬，罩，侧未被該光阻圖賴蓋區域的該旋塗玻璃層、該犧牲層以及 。亥-氧化⑨她層，去除該光關案，留下位於該相鄰兩閘等體堆疊结 構之間上方該位元線接觸洞區_之該旋塗玻璃層、該犧牲層以及該二氧 化石夕襯墊層；於該旋塗玻璃層上以及制極導體堆疊結構上表面以及垂直 側土上沈積IU匕石夕層，於該氮化石夕層上沈積一介電層；進行一第二化學 機械磨製程，將該介電層研磨平坦至該旋塗玻璃層停止；以及去除該旋 塗玻璃層以及該犧牲層，形成一接觸洞。 為讓本發明之上述目的、特徵、和優點能更明顯易懂，下文特舉較佳實 施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與 圖式僅供參考與說明用，並非用來對本發明加以限制者。 【實施方式】 明參閱圖/、至圖十二，圖六至圖十三顯示本發明較佳實施例一種在溝渠 電容動態唯f胃記憶體製財，使賤牲？㈣層以及缝玻璃(spin_〇n glass，SOG)層，於兩閘極導體堆疊結構間製作位元線接觸洞之方法。其中， 12 200537642 圖 中相同之元件或區域部分仍·相同之符號來表示 所不’在半導縣底1G的絲面^上形成有至少兩間極導體 ι/=^Γί〇Γ ’沈)堆豐結構12與14。一般，閘極導體堆疊結構12與 ’氧化層22、導電層24錢氮切絲26。導電層24可 ♦二夕Βθ夕以及孟私化層或金屬層。根據本發明讀佳實施例，間極導 二(⑽㈤如价，GC)堆疊結構U與W距離主表面㈣高度約為 埃左右，其中氮化矽蓋層26的厚度約為2000埃。 、在基底ίο表面上可區分為位元線接觸、洞區域42以及非位元線接觸洞區 域44,其中位元線接觸洞區域42在閘極導體堆疊結構以與^之間的上方。 根據本發以較佳實施例，位元線接觸通域42之尺寸大小約為9 但不限於此。 ” 形成閘極導體堆疊結構12與14之後，接著以化學氣相沈積製程於基底 10,面上沈積二氧化矽襯墊層102。二氧化矽襯墊層1〇2並覆蓋閘極導體 隹$、、、口構12與14之上表面以及側壁。隨後，再於二氧化石夕概塾層舰上 沈積-犧牲多晶碎層104。根據本發明之較佳實施例，犧牲多晶销1〇 厚度約為4000埃左右。 如圖七所示，進行第一次的化學機械研磨(CMp)製程，將多晶矽層 平坦化至閘極導體堆疊結構12肖14的氮僻蓋層26彳亭止。由於此次的化 學機械研磨製程係利用氮化石夕蓋層％為研磨停止層，因此可以準確的偵測 研磨終點。在研磨終點之後，可以再進行過度研幻。另外， 本發明利賴切蓋層26為研磨停止層的另—優點在於由魏切蓋層％ 同層所形成的晶圓對準結構(alignment mark)亦同時被暴露出來，而不合 破多晶矽層覆蓋住，如此，即可以精確地進行晶圓對準步驟，提升製程的 精在度。在圖七中，在完成第一次的CMp製程後，於非位元線接觸洞區域 44的犧牲多晶矽層104表面上可能有下凹的現象(dishing)。 13 200537642 如圖=所示，接著於基底10上形成一旋塗玻璃層106,其厚度約為3000 埃並伋盍閘極導體堆疊結構12與14的氮化矽蓋層26、該經過CMp研磨 的犧牲多晶碎層104以及部分的二氧化物墊層撤。織，再以習知的黃 光^程於旋塗玻璃層舰上形成光阻圖案舰，其遮蔽在閘極導體堆疊結構 12與14之間上方的位元線接觸洞區域似，而暴露出非位元線接觸洞區域 44。本發明由於使用旋塗玻璃層1〇6，因此可以補償先前cMp造成在非位 元線接觸洞區域44的犧牲多晶秒層綱表面上的下凹處，而獲得絕佳的晶 圓平坦度。 如圖九所不，進行一乾蝕刻製程，利用光阻圖案1〇8以及閘極導體堆疊 結構I2與Μ的氣化石夕蓋層26作為钱刻遮罩，將未被光阻圖案娜遮蓋到 區域内的旋塗玻璃層106、犧牲多晶秒層腦以及二氧切襯墊層1〇2儀 除。僅留下在位元線接觸洞區域42内的旋塗玻璃& 1〇6、犧牲多晶石夕層辦 以及二氧化矽襯墊層102。 如圖十所示，接著於基底1()上沈積一薄氮化梦層加，其覆蓋部分的 基底10的主表面11、部分的閘極導體堆疊結構12與14的側壁以及上表面， 以及剩下的旋塗玻璃層1〇6表面。然後，進行一化學氣相沈積製程，於薄 110 ^^^~^^Wi^^(borophosphosilicate glass^PSG)^ 120^ 其厚度約為4000至8000埃左右。 如圖十一所示，進行第二次的化學機械研磨(CMp)製程，將硼磷矽玻璃 層120研磨平坦^至旋塗玻璃们06停止。需注意在此階段，位元線接觸 洞區域42 _薄氮化石夕層11〇已經被研磨去除，而暴露出其下的旋塗玻璃 層 106 〇 如圖十二所示，進行-侧製程，將位元線接觸洞區域似内的旋塗玻 璃層106以及剩下的多晶矽層1〇4去除，形成接觸洞13〇。 14 200537642 域42内的二氧化麵層1G2=_區 氏—的主表面1]。取後’於接觸洞13〇内填入導電材料，形成位元線接觸 結;：==:。容_記憶體製程中，於 之岣 等：明申請專利範圍所做 【圖式簡單說明】 圖式之簡單說明 圖五顯示習知技藝於兩相鄰閘極導體結構之間製作也元線接觸洞之 圖圖十二顯示本發明較佳實施例一種在溝渠電容動態唯讀記情 T，使用犧牲多晶矽層以及旋塗玻璃層，於兩閘極導體堆聶程 作位元線接觸洞之方法。 且、、口傅間製 圖式之符號說明 基底 11 主表面 閘極導體堆疊結構 14 閘極導體堆疊結構 閘極氧化層 24 導電層 氮化石夕蓋層 32 氮化矽襯墊層 硼磷矽玻璃層 42 位元線接觸洞區域 非位元線接觸洞區域 52 光阻圖案 開口 62 接觸洞 氡化秒側壁子 66 位元線接觸插塞 —氧化石夕襯墊層 104 犧牲多晶石夕層 ^塗玻璃層 108 光阻圖案 鼠化秒層 120 硼填矽玻璃層 接觸洞 位元線接觸插塞 142 二氧化矽侧壁子 10 12 22 26 36 44 54 64 102 106 110 130 150 15200537642 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a semiconductor manufacturing method, and more particularly to a method for using trench-capacitor dynamic read-only memory (Trench-DRAM) process using a sacrificial polycrystalline silicon layer and spin-on-glass ( sphw) nglass (SOG) layer, a method for making a bit line contact hole between two gate conductor stack structures. [Previous technology] As the industry knows, trench capacitor dynamic read-only memory is to dig deep trenches in semiconductor substrates, and then use complex semiconductor processes to make trench capacitor elements in deep trenches. Developed in the direction of small size and high accumulation, the design of high-density trench capacitor dynamic read-only memory makes the distance between components in the memory array and the distance between the conductors closer and closer, the density The increased result not only worsens the situation of capacitive coupling (coupKng) between adjacent wires, but also increases the difficulty in transferring micropatterns, such as bit line contact holes, in the lithography process. Figures 1 to 5 show the method of making bit line contact holes between the two gate conductor structures 12 and 14 by the conventional technique. As shown in FIG. 1, at least two gate conductor (GC) stacked structures 12 and 14 are formed on the main surface u of the semiconductor substrate 10. Generally, the gate conductor stack structures 12 and 14 each include a gate oxide layer 22, a conductive layer 24, and a silicon nitride cap layer. On the surface of the substrate 10, a bit line contact hole region 42 and a non-bit line contact hole region 44 can be roughly distinguished. The bit line contact hole region 42 is above the gate conductor stack structure 12 and µ. After the gate conductor stack structures 12 and 14 are formed, a silicon nitride liner layer is then deposited on the surface of the substrate 10, and then a borophosphosilicate glass is deposited for washing and washing to produce a caffeine layer. 36 ° As shown in FIG. 1, a chemical mechanical polishing (CMp) process is performed to planarize the boronite glass layer 36 to nitride; and the liner layer 32. As shown in FIG. 3, on the borophosphosilicate glass layer 36 and the silicon nitride 10 200537642 liner layer 32, a tetraethoxysilane (TEOs) stone oxide layer 3 is deposited on the stone oxide layer 38 to The photoresist pattern is formed by the yellow light process, and the four-layer lithography conductor stack, _ and 14 are the strongest bit, and the area is =, which is exactly violent. / ^ Ordering-anisotropic dry-gang system, Toruko Case 52 is an etch mask, and through the opening 54, the tetraethoxyweishixi oxygen layer 38, _Shixi glass sound 3 is formed in the bit line contact hole area 42 -bit line contact hole 62. At the same time, nitriding murals w were formed on the rat == piles $, 纟 _ and 14_. _ Remove light Xiao = Γ6 Γ Γ then fill the metal line in the bit line contact hole 62 to form a bit, spring contact insert 64. The height of -m miscellaneous contact 64 from the surface η plane of the base 1G company. The thickness of the tetraethoxy weir layer 38 is about 3 mm. Ten pumps = 丨 The white knowledge technology department has the following shortcomings. As the result of the bit line contact hole area 42 feet T getting smaller and smaller, for example, when the 9G nanometer technology node is used, it is very difficult to accurately expose the bit line contact hole pattern with the traditional universal light ==, sometimes it is necessary to In order to expose the desired pattern with imaging supplement (Technology Iogy, IET), the processwmdow is low. Moreover, the current traditional dry name engraving process is used to strengthen the above-mentioned four-dimensional depth of the left and right through the contact with the size of * meters. Incomplete removal may also occur in the oxy-Wei layer, phosphor-depleted silicon, glass layer 36, and silicon nitride liner layer 32. In addition, the other point of the know-how described in 4 is that the bit line contact plug 64 and the interlayer conductor stacking structure 14 and the conductive layer 24 of the 14 are nitride nitride side walls 64. Therefore, during operation, The resulting parasitic capacitance is high and there are concerns about the RC delay effect. [Summary of the Invention] Therefore, 'the main purpose of the present invention is to provide a kind of trench-capacitor read-only memory (Trench-DRAM) process' using a sacrificial polycrystalline layer and spin-on glass (spinon, ss, s〇). g) 11 200537642, which can solve the problem of the method of making a bit line contact hole between two hybrid conductor structures. According to a preferred embodiment of Baoren 1, the present invention provides a method for making a bit line contact hole, a body: a stacked structure, and a main surface of which has two adjacent gate conductors formed on the main surface. There is a one-element line contact hole area located on the adjacent two gate conductor stacks: above the gate of the gate structure, each of the conductor stack structures has an upper surface and a vertical side. Lay on the surface and the rest of the surface to deposit a layer of dioxygenation; see a layer of sacrificial deposited on the cushion layer; perform a first chemical And T-pole electrodes, a spin-coated glass layer is formed on the top surface of the stacked structure, and a photo-resistance B is formed on the spin-coated glass layer, which covers the impurity element contacting the desired region; the photo-resist pattern For the remainder of the hard cover, the spin-coated glass layer, the sacrificial layer, and the .H-oxide layer are not covered by the photoresist area, and the light-off case is removed, leaving the two adjacent gates. The spin-coated glass layer, the sacrificial layer, and the dioxide A liner layer; depositing an IU dagger layer on the spin-coated glass layer, the upper surface of the stacked conductor structure and the vertical lateral soil; depositing a dielectric layer on the nitride layer; performing a second chemical machinery The grinding process flattens the dielectric layer until the spin-on glass layer stops; and removes the spin-on glass layer and the sacrificial layer to form a contact hole. In order to make the foregoing objects, features, and advantages of the present invention more obvious It is easy to understand that the following describes in detail the preferred embodiments and the accompanying drawings in detail. However, the following preferred embodiments and drawings are for reference and explanation only, and are not intended to limit the present invention. Embodiment] Referring to FIG. 12 to FIG. 12, FIG. 6 to FIG. 13 show a preferred embodiment of the present invention, which is a dynamic memory system in a trench capacitor, so that the base layer and the slit glass (spin_ 〇n glass (SOG) layer, a method for making a bit line contact hole between two gate conductor stack structures. Among them, the same element or area part in the figure 2005200542 is still the same symbol to indicate that it is not in the semiconductor County bottom 1G wire surface ^ is formed with at least two pole conductors ι / = ^ Γί〇Γ 'sink) stack structure 12 and 14. Generally, the gate conductor stack structure 12 and' oxide layer 22, conductive layer 24, and nitrogen cut The wire 26. The conductive layer 24 may be a layer of Bθ and a layer of metallization or a metal layer. According to the preferred embodiment of the present invention, the height of the stacked structure U and W from the main surface ㈣ The thickness of the silicon nitride cap layer 26 is about 2000 angstroms. On the surface of the substrate, it can be divided into bit line contact, hole region 42 and non-bit line contact hole region 44, where the bit line The contact hole area 42 is above the gate conductor stacking structure. According to a preferred embodiment of the present invention, the size of the bit line contact pass area 42 is about 9 but is not limited thereto. ”Forming the gate conductor After the stacked structures 12 and 14 are deposited on the substrate 10 by a chemical vapor deposition process, a silicon dioxide liner layer 102 is deposited on the surface. The silicon dioxide liner layer 102 covers the upper surfaces and the sidewalls of the gate conductors 12 and 14 and the gate conductors 12 and 14. Subsequently, a polycrystalline debris layer 104 is deposited-sacrificed on the osmium dioxide ship. According to a preferred embodiment of the present invention, the thickness of the sacrificial polycrystalline pin 10 is about 4000 angstroms. As shown in FIG. 7, the first chemical mechanical polishing (CMp) process is performed to planarize the polycrystalline silicon layer to the nitrogen blanket cap layer 26 of the gate conductor stack structure 12 and 14. Since the chemical mechanical polishing process uses the nitrided cap layer as the polishing stop layer, the polishing end point can be accurately detected. After the grinding end point, over-spinning can be performed. In addition, another advantage of the Li Li cut cap layer 26 of the present invention is that the polishing stop layer is an advantage that the wafer alignment mark formed by the Wei cut cap layer and the same layer is also exposed at the same time, without breaking the polycrystalline silicon layer. Cover, so that the wafer alignment step can be performed accurately and the precision of the process can be improved. In FIG. 7, after the first CMP process is completed, the surface of the sacrificial polycrystalline silicon layer 104 in the non-bit line contact hole region 44 may have a sinking phenomenon. 13 200537642 As shown in the figure, a spin-coated glass layer 106 is formed on the substrate 10 with a thickness of about 3000 angstroms and the silicon nitride capping layer 26 of the gate conductor stacked structures 12 and 14 is polished by CMP. The sacrificial polycrystalline debris layer 104 and a portion of the dioxide cushion layer are removed. Weaving, and then forming a photoresist pattern on the spin-coated glass layer ship with the conventional yellow light process, which masks the bit line contact hole area above the gate conductor stacking structure 12 and 14 and exposes The non-bit line touches the hole area 44. Since the present invention uses a spin-coated glass layer 106, it can compensate the previous depression caused by the sacrificial polycrystalline second layer surface of the non-bit line contact hole region 44 caused by the previous cMp, and obtain excellent wafer flatness. . As shown in FIG. 9, a dry etching process is performed. The photoresist pattern 108 and the vaporized stone cover layer 26 of the gate conductor stacking structure I2 and M are used as a mask to cover money, and the area not covered by the photoresist pattern is covered by the photoresist pattern. The spin-coated glass layer 106, the sacrificial polycrystalline second layer brain, and the dioxin pad layer 102 were removed. Only the spin-on glass & 106, sacrificial polycrystalline silicon layer and the silicon dioxide liner layer 102 in the bit line contact hole area 42 are left. As shown in FIG. 10, a thin nitride layer is then deposited on the substrate 1 (), which covers part of the main surface 11 of the substrate 10, part of the side walls and upper surfaces of the gate conductor stack structures 12 and 14, and The remaining surface of the spin-coated glass layer 106. Then, a chemical vapor deposition process is performed, and the thickness is 110 ^^^ ~ ^^ Wi ^^ (borophosphosilicate glass ^ PSG) ^ 120 ^ and the thickness is about 4000 to 8000 angstroms. As shown in FIG. 11, a second chemical mechanical polishing (CMp) process is performed, and the borophosphosilicate glass layer 120 is polished flat until the spin-on glass 06 is stopped. It should be noted that at this stage, the bit line contact hole area 42 _ the thin nitride stone layer 11 〇 has been removed by grinding, and the spin-coated glass layer 106 under it is exposed. As shown in FIG. 12, a side process is performed. The spin-on-glass layer 106 and the remaining polycrystalline silicon layer 104 that are within the bit line contact hole region are removed to form a contact hole 13. 14 200537642 The dioxide surface layer 1G2 in the domain 42 = the main surface 1 of the _Area. After taking out ', a conductive material is filled in the contact hole 13 to form a bit line contact junction;: == :. Content_memory system, Yu Zhiyi, et al .: The scope of patent application [Simplified illustration of the diagram] Simple illustration of the diagram Figure 5 shows the conventional technique of making a line contact between two adjacent gate conductor structures Figure of hole Figure 12 shows a preferred embodiment of the present invention. A method for dynamically reading the memory T in a trench capacitor, using a sacrificial polycrystalline silicon layer and a spin-on glass layer, to make a bit line contact hole in the two gate conductor stacks Nie Cheng. . And, the symbols of the drawings show the base 11 main surface gate conductor stacking structure 14 gate conductor stacking structure gate oxide layer 24 conductive layer nitride nitride cover layer 32 silicon nitride liner layer borophosphosilicate glass layer 42-bit line contact hole area Non-bit-line contact hole area 52 Photoresist pattern openings 62 Contact holes 氡 Second side wall 66 Bit line contact plugs—Stone oxide liner layer 104 Sacrifice polycrystal layer Glass layer 108 Photoresist pattern mouse-second layer 120 Boron-filled silicon glass layer Contact hole Bit line contact plug 142 Silicon dioxide sidewall 10 12 22 26 36 44 54 64 102 106 110 130 150 15