200535999 玖、發明說明： 【發明所屬之技術領域】 本發明係與半導體有關’尤指一種半導體晶圓及其 程’其中該端子塾（termianl pad)係沿一半導體晶圓之一 割道（scribe line)置放，以擴大該類比積體電= (integrated circuit ; 1C)晶片的使用面積。 【先前技術】 一傳統半導體晶圓包括一晶圓主體與在該晶圓主體 上間隔形成的複數個晶片，用於定義作為每兩個晶片之間 一界限的一切割道。因此，每一該等晶片（亦稱為一類比 1C晶片）為基於石夕基板所組成的一積體電路。 在將每一該等晶片切割成一單獨組件之前，必須執行 一晶圓測試，以確保每一該等晶片係在一最佳條件下發揮 作用。一般而言，每一該等晶片包括在該晶片内部間隔形 成的複數個焊墊（bond pad)與複數個端子墊，其中該等端子 墊可為測試墊（test pad)，用於經由諸如探針卡或剪切塾 (trim pad)之一測量工具來測量該晶片的電壓，以調整該晶 片的參考電壓及其參考功能。 因此，通常採用雷射切割與電調整兩種調整方法來調 整该專晶片。執行雷射切割來切割保險絲，使得一旦保險 絲受到切割，晶片的性能會相應改變。然而，雷射切割操 作既昂貴又複雜，以致會大幅增加晶片的製造成本。此外， 在操作雷射切割過程中，不能預測每一晶片的電壓，以致 不能使每一晶片的品質標準化。 200535999 另-調整方法係藉由電剪切方式來執行，丨 該等晶片上施加一電流來剪切該保險絲。由於可 控制該電流，故可有選擇地將保險絲從該等晶除， 便產生該晶片的參考電壓及其參考功能。 夕承 人 此外，傳統I導體晶圓具有數個缺點。由於端 置放於每-該等晶片内部，故該晶片之尺寸必須足夠大:、 =便，該等焊墊、端子墊以及絲絲 此，每-該等晶片尺寸有限，則晶片上僅能；； 的焊墊或是端子墊。換言之，位於每一 積體電路會受限於該等晶片之尺寸，的複雜 體晶圓的製造成本。 以致大幅增加該半導 此外，當將該等晶片從丰導栌曰圓^ 子墊會保留在I 一姑笙日u導體日日圓切除時，該等端 、1曰二 以等曰日片之上。然而，端子墊係僅用於 測篁相應晶片之電壓吱可采彳 它你惶用於 後，端子墊便盎剪切該保險絲。測量結束 晶片的有限空間。 買母这寺 【發明内容】 本發月的主要目的係提供一種半導體曰# . 電連接，以便擴大ff 切割道置放’並與該晶片 M使擴大晶片的使用面積。 本發明的另一目的從担 仏… 電配置係從該切割道向；曰：：f半導體晶圓，其中-導 k向”亥B曰片延伸，以使該端子墊與該晶 200535999200535999 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to semiconductors, especially a semiconductor wafer and its processes, wherein the termianl pad is cut along a scribe line of a semiconductor wafer (scribe line) to increase the use area of the analog integrated circuit = (integrated circuit; 1C) chip. [Prior Art] A conventional semiconductor wafer includes a wafer body and a plurality of wafers formed at intervals on the wafer body, and is used to define a scribe line as a boundary between every two wafers. Therefore, each of these chips (also referred to as an analog 1C chip) is an integrated circuit based on the Shixi substrate. Before each of these wafers is cut into a separate component, a wafer test must be performed to ensure that each of these wafers function under optimal conditions. Generally speaking, each of these wafers includes a plurality of bond pads and a plurality of terminal pads formed at intervals inside the wafer, wherein the terminal pads can be test pads, and are used for One of a pin card or a trim pad measurement tool measures the voltage of the wafer to adjust the reference voltage of the wafer and its reference function. Therefore, laser cutting and electrical adjustment are usually used to adjust the special chip. Laser cutting is performed to cut the fuse so that once the fuse is cut, the performance of the wafer changes accordingly. However, the laser cutting operation is expensive and complicated, so that the manufacturing cost of the wafer is greatly increased. In addition, during the operation of laser cutting, the voltage of each wafer cannot be predicted, so that the quality of each wafer cannot be standardized. 200535999 Another-adjustment method is performed by an electric shearing method, and a current is applied to the chips to cut the fuse. Because the current can be controlled, the fuse can be selectively removed from the crystals to generate a reference voltage for the chip and its reference function. Xi Chengren In addition, traditional I-conductor wafers have several disadvantages. Because the end is placed inside each of these wafers, the size of the wafer must be large enough :, ..., the pads, terminal pads, and wires. Since each of these wafers has a limited size, only ;; The solder pad or terminal pad. In other words, each integrated circuit is limited by the size of the wafers, and the manufacturing cost of the complex wafers. So that the semiconductor is greatly increased. In addition, when the wafers are removed from the Fengdao 栌 Yuan ^ sub-pad will be cut off at the I-Yu Sheng day u conductor Yen Yen, the ends, 1 y, y, y, etc. on. However, the terminal pad is only used to measure the voltage of the corresponding chip. After you use it, the terminal pad will cut the fuse. End of measurement. Limited space on wafer. Temple of Buying Mother [Summary of the Invention] The main purpose of this month is to provide a semiconductor electrical connection, so as to expand the ff dicing track placement 'and expand the use area of the wafer with the wafer M. Another object of the present invention is to support the electrical configuration from the dicing path; said: f semiconductor wafer, where -conductor k extends to "Hai B" wafer, so that the terminal pad and the crystal 200535999
片電連接，使得當將晶片從該晶圓主體切除後，僅藉由八 該切割道切除該導電配置即可將端子墊從晶片上移除3。/Q 本發明的另一目的係提供一種半導體晶圓，盆中該端 子墊係製作為一梳型形成，使一切割工具沿該切割道：除 該晶片時，其可將保留在該切割工具切割尖端上的殘渣減 至最少’從而加強晶片的切割操作。The chip is electrically connected, so that when the wafer is cut from the wafer body, the terminal pad can be removed from the wafer only by cutting the conductive configuration through the eight scribe lines3. / Q Another object of the present invention is to provide a semiconductor wafer. The terminal pad in the pot is formed in a comb shape, so that a cutting tool is along the cutting track: when the wafer is removed, it can be retained in the cutting tool. The residue on the cutting tip is minimized, thereby enhancing the cutting operation of the wafer.
子的另—目的係提供—種半導體晶圓，其中制 2= 片移至晶圓主體之切割道，使得晶片的可孩 片的功?擴大且晶片中可加入更多積體電路以加強晶 改㈣曰= 係提供一種半導體晶圓，其中並; 八來収該+導體晶圓，將本發明的製造成本減至最少。 圓，ί:::另一目的係提供一種剪切保險絲半導體1 位為沿日日《ιί程較簡單’即將該端子墊從該晶片内重新突Another purpose of the sub-system is to provide a kind of semiconductor wafer, in which 2 = wafers are moved to the dicing path of the wafer body, so that the power of the wafer can be expanded and more integrated circuits can be added to the wafer to strengthen the crystal. The reform is to provide a semiconductor wafer, wherein the + conductor wafer is received to reduce the manufacturing cost of the present invention to a minimum. Yuan, ί ::: Another purpose is to provide a cut-off fuse semiconductor 1 bit, which is "simple and easy" to re-project the terminal pad from the chip.
該晶片ί連接切割道來置放，並經由導電配置將端子墊病 一步降低本發明因此，本發明中不需要額外的組件，可造 降低本發明的製造成本。 從而9兔香：日, 其包括··"、、 上述目的，本發明提供一種半導體晶圓， 晶圓主體； 8 200535999 複數個^類比1c晶片，其間隔且對齊地形成於該晶圓 f 上’每兩個晶片間之-區域定義為-切割道，其中 母曰曰片具有在其内部形成的内部電路以及沿該切割道形 成的至少一端子墊；以及 —一導電配置，其包括形成於晶圓主體之上的至少一導 電凡件，將端子墊與該晶片之内部電路電連接，使得當沿 :割道將晶片從晶圓主體上切除後，可將端子墊從該晶片 中切除’而該内部電路保留在晶片中。 本案得藉由以下列圖示與詳細說明，俾得一更深入之 了解。 【實施方式】 參f該等圖式之第一圖，其係本案較佳具體實施例之 、體晶圓的上視圖。其中，該半導體晶圓包括一晶圓主 1 0 ’以及間隔並對齊地形成於晶圓主體1 〇之上的複數 =類比1C晶片20，每兩個晶片2〇間之一區域定義為一切 二道」1。其中，每一該等晶片2〇具有在晶片内部形成的 一内部電路21以及沿切割道11形成的至少一端子墊22。 、曰該半導體晶圓進一步包括一導電配置3〇,其包括形成 於阳圓主體10之上的至少一導電元件31，以便將端子墊 n與内部電路21電連接，使得當沿切割道1 1將晶片2 0 從曰曰圓主體10上切除後，可將端子墊22從晶片20中切 除’使内部電路21保留在晶片20中。 200535999 以4:明進一步提供-製造該半導體晶圓程序，其包括 曰二主曰V〇上間隔並對齊地形成該等類比1c s曰片 母兩個曰曰片20間之一區域定義為—切割道u。 (2) 沿著在鄰近個別晶月2〇之 11上安置排列該端子墊22。 目篮10的切割道 (3) 於晶圓主體1〇上形成導電元件31，以 墊22與該晶片20的内部電路21電連接。 ， 便將：子：^V曰1將晶片2〇從晶圓主體10上切除，以 ίΠ。中 片2〇移除’使該内部電路2"呆留在 =該較佳具體實施例，每—該等晶片Μ均可提供精 可乂：破一類比IC。因此’每一該等晶片20的電壓測量 同樣，每一該等晶片2〇均得到剪切以可程式化 该晶片2。’以產生一參考電壓與一參考功能。 式化 片Τ個Λ體電路來構造每—該等晶 开“ Λ 其中，端子墊22係經由導電 來/、個別晶片20的内部電路21電連接。 =墊22係作為從該晶片2〇之積體電 :::塾而具體化。從而，每-該等晶片2。另外具 入於心22處：延伸的一保險絲23 ’以使個別晶片20均適 合於剪切以產生該晶片2G的參考電壓及參考功能。然^ 10 200535999 子墊22可為一測試墊，用於與該測量工具電耦合 該晶片20的電壓 一 如第三圖所示，具有-梳狀的端子墊22，定義複 端子齒22 1 ’其間隔地形成於晶圓主體1 〇之切割道u 其中，導電元件31係從晶圓主體10之切割道伸 晶片20，以使端子墊22的端子齒221與晶片2〇的 = 路21電連接。 σ丨电 值得一提的是為將晶片20從晶圓主體1〇上切除，可 採用一切割工具（如具有鑽石頭的一切割裝置）沿晶圓L 體10之切割道11來切割，以便單獨將晶片2〇從^曰^主體 10上分開。然而，當該切割工具之切割尖端沿晶圓主體 之切割道11滑動切割時，端子墊22的殘渣會保留在具有 据齒狀邊緣的切割工具之切割尖端上。因此，為防止^子 墊22的殘渣會殘留在具有鋸齒狀邊緣的切割工具之切割 尖端上，將端子墊22作為一梳狀結構。當切割工具之切割 尖端沿端子墊22的端子齒221滑動切割時，使殘留在該切 割工具之切割尖端上的殘渣減至最少。 由金屬層製成的該導電元件31從晶圓主體10之切割 道11延伸至晶片20，以使端子墊22與晶片2〇的内部電 路21電連接。另外，導電元件31可由多晶層（p〇1y丨叮^) 製成’使端子墊22與晶片20的内部電路21電連接。 因此’當將端子塾22做為剪切墊時，該導電配置3〇 更包括從導電元件3 1向保險絲23電延伸的一辅助導電元 件32 ’使保險絲23適合於透過該辅助導電元件32藉由端 11 200535999 示將端子墊二二切= 2〇剪切後，如 片20處移除。 第三圖所 以便在將曰提的，保險絲23係置放於晶片20内部， 可保留在：片從晶圓主體1〇上切除之後，該保險絲23 割道11將曰曰曰# ,:部。此外，由於已沿晶圓主體10之切 1〇之切判、Γ η從晶圓主體10上切除，故可將晶圓主體 除。°、 上的導電元件31之一部分從晶片20中移The wafer is placed in connection with the dicing track, and the terminal pad is diseased by the conductive configuration. The invention is therefore further reduced. Therefore, the invention does not require additional components, which can reduce the manufacturing cost of the invention. Thus 9 rabbit incense: Japan, which includes the above purpose, the present invention provides a semiconductor wafer, the wafer body; 8 200535999 a plurality of ^ analog 1c wafers, which are formed on the wafer f spaced and aligned The area between every two wafers is defined as a dicing track, wherein the mother chip has an internal circuit formed therein and at least one terminal pad formed along the dicing track; and a conductive configuration including forming At least one conductive element on the wafer body electrically connects the terminal pad to the internal circuit of the wafer, so that when the wafer is cut from the wafer body along a scribe line, the terminal pad can be cut from the wafer 'And the internal circuit remains in the wafer. The case has to be understood in more detail by the following icons and detailed explanations. [Embodiment] Refer to the first figure of the drawings, which is a top view of a bulk wafer in a preferred embodiment of the present application. Wherein, the semiconductor wafer includes a wafer master 10 ′ and a plurality of wafers 10 aligned on the wafer main body and being aligned and aligned = analog 1C wafer 20. One area between every two wafers is defined as all two.道 "1. Each of these wafers 20 has an internal circuit 21 formed inside the wafer and at least one terminal pad 22 formed along the scribe line 11. The semiconductor wafer further includes a conductive arrangement 30 including at least one conductive element 31 formed on the male body 10 so as to electrically connect the terminal pad n with the internal circuit 21 so that when along the scribe line 1 1 After the wafer 20 is cut out from the circular body 10, the terminal pad 22 can be cut out from the wafer 20 so that the internal circuit 21 remains in the wafer 20. 200535999 4: Ming further provided-the process of manufacturing the semiconductor wafer, which includes the two masters V0 spaced and aligned to form such analogs 1c s film mother two two film 20 area is defined as- Cutting road u. (2) Arrange the terminal pads 22 along 11-10 adjacent to individual crystal moons. The dicing path (3) of the eye basket 10 forms a conductive element 31 on the wafer body 10, and the pad 22 is electrically connected to the internal circuit 21 of the wafer 20. Then, it will be: Sub: ^ V said that the wafer 20 is cut from the wafer main body 10 to Π. Removal of the mid-chip 20 causes the internal circuit 2 to stay in the preferred embodiment. Each of these chips M can provide precision. Breaking an analog IC. Therefore, the voltage measurement of each of these wafers 20 is the same, and each of these wafers 20 is cut to program the wafer 2. 'To generate a reference voltage and a reference function. To form each piece of Λ body circuit to form each of these crystal openings, Λ, the terminal pad 22 is electrically connected to the internal circuit 21 of the individual chip 20. = The pad 22 is used as Integral electricity ::: 塾 and concrete. Therefore, each-such wafers 2. In addition to the heart 22: an extended fuse 23 'to make individual wafers 20 suitable for cutting to produce the wafer 2G Reference voltage and reference function. Then ^ 10 200535999 The sub-pad 22 can be a test pad for electrically coupling the voltage of the chip 20 with the measurement tool. As shown in the third figure, it has a -comb-shaped terminal pad 22, defined The plurality of terminal teeth 22 1 ′ are formed at intervals on the dicing path u of the wafer body 10, wherein the conductive element 31 extends the wafer 20 from the dicing path of the wafer main body 10 so that the terminal teeth 221 of the terminal pad 22 and the wafer 2 〇 = Electrical connection of circuit 21. σ 丨 It is worth mentioning that in order to cut wafer 20 from wafer body 10, a cutting tool (such as a cutting device with a diamond head) can be used along wafer L body 10 The dicing track 11 is used to separate the wafer 20 from the main body 10 separately. However, when the cutting tip of the cutting tool slides and cuts along the cutting path 11 of the wafer body, the residue of the terminal pad 22 will remain on the cutting tip of the cutting tool with a toothed edge. Therefore, in order to prevent the sub-pad 22 The residue will remain on the cutting tip of the cutting tool with a jagged edge, using the terminal pad 22 as a comb-like structure. When the cutting tip of the cutting tool slides and cuts along the terminal teeth 221 of the terminal pad 22, it will remain on the cutting The residue on the cutting tip of the tool is minimized. The conductive element 31 made of a metal layer extends from the cutting track 11 of the wafer body 10 to the wafer 20 so that the terminal pad 22 is electrically connected to the internal circuit 21 of the wafer 20 In addition, the conductive element 31 may be made of a polycrystalline layer (p0y 丨), so that the terminal pad 22 is electrically connected to the internal circuit 21 of the chip 20. Therefore, when the terminal 塾 22 is used as a cutting pad, the The conductive configuration 30 also includes an auxiliary conductive element 32 'extending electrically from the conductive element 31 to the fuse 23. The fuse 23 is adapted to pass through the auxiliary conductive element 32 and cut the terminal pad in two by the terminal 11 200535999. After that, it is removed as shown in the piece 20. In the third figure, the fuse 23 is placed inside the wafer 20, and it can be retained: After the piece is cut from the wafer body 10, the fuse 23 is cut off. 11 将 说 midday # ,: 部. In addition, since the wafer body 10 has been cut along the cut of 10, Γ η is cut from the wafer body 10, the wafer body can be removed. Part of element 31 is moved from wafer 20
田將鳊子墊22作為測試墊來具體化時，晶 保險絲23。將導電元陶晶圓主體H)之切割道: ，至該晶片20,使做為測試墊的端子墊22與晶片2〇合 ^電路21電連接。因此，在測出晶片2〇的電壓後，崩 做為測試墊的端子墊22從晶片20移除。 由於知子墊22係沿晶圓主體10之切割道11置放，實 承上擴大了晶片20的使用面積，從而可向晶片2〇中加入 多積體電路。與端子墊係設置於晶片内部的傳統晶片相 1，此一配置可提高晶片之功能。此外，當將端子墊22作 為測試墊來具體化時、或為剪切晶片2〇,當端子墊22做 為剪切墊來具體化時，可用端子墊22來測試晶片2〇。因 此，在調整或測試晶片20之後，端子墊22不會再為晶片 =執行任何功能，因而可將端子墊22從晶片2〇移除，而 僅在晶片20中保留内部電路21，以用於操作。 12 200535999 上述本發明之具體實施例與圖示係使熟知此技術之人 士所能瞭解，然而本專利之權利範圍並不侷限在上述實施 例。 因而可以看見，本發明之該等目的已經完全且有效實 現。基於解說本發明之功能與結構原理之目的而顯示及說 明本發明之具體實施例，並且可對該等具體實施例進行均 等變化，而不致脫離此類原理。因此，本發明專利範圍包 括涵蓋於以下申請專利範圍之精神與範圍内之所有均等變 化。 · 【圖式簡單說明】 第一圖為本發明之一較佳具體實施例之半導體晶圓的 上視圖。 第一圖為本發明之上述較佳具體實施例之一端子塾電 連接類比ic晶片之半導體晶圓透視圖。 ， 第二圖為依據本發明之上述較佳具體實施例之該半導 體晶圓上一端子墊電連接的類比Ic晶片的剖面透視圖。 圖示符號說明 11切割道 21内部電路 23保險絲 10晶圓主體 20類比1C晶片 221端子齒 22端子墊 13 200535999 30導電配置 31導電元件 32辅助導電元件When Tian uses the ladle pad 22 as a test pad, the crystal fuse 23 is used. Cut the conductive element ceramic wafer main body H) to the wafer 20, so that the terminal pad 22, which is a test pad, is electrically connected to the wafer 20 and the circuit 21. Therefore, after the voltage of the wafer 20 is measured, the terminal pad 22, which serves as a test pad, is removed from the wafer 20. Since the sub-pad 22 is placed along the dicing path 11 of the wafer body 10, the area of the wafer 20 is enlarged, so that a multi-integrated circuit can be added to the wafer 20. Compared with the conventional wafers in which the terminal pads are arranged inside the wafer, this configuration can improve the function of the wafer. In addition, when the terminal pad 22 is embodied as a test pad or the wafer 20 is cut, and when the terminal pad 22 is embodied as a cut pad, the terminal pad 22 can be used to test the wafer 20. Therefore, after the wafer 20 is adjusted or tested, the terminal pad 22 will no longer perform any function for the wafer =, so the terminal pad 22 can be removed from the wafer 20, and only the internal circuit 21 is retained in the wafer 20 for use in operating. 12 200535999 The above specific embodiments and illustrations of the present invention are understood by those skilled in the art, but the scope of rights of this patent is not limited to the above embodiments. It can thus be seen that the objects of the present invention have been fully and effectively achieved. The specific embodiments of the present invention are shown and explained for the purpose of explaining the functional and structural principles of the present invention, and the specific embodiments can be changed equally without departing from such principles. Therefore, the scope of patents of the present invention includes all equal variations encompassed within the spirit and scope of the scope of patent application below. [Brief description of the drawings] The first figure is a top view of a semiconductor wafer according to a preferred embodiment of the present invention. The first figure is a perspective view of a semiconductor wafer with a terminal-connected analog IC chip, which is one of the preferred embodiments of the present invention. The second figure is a cross-sectional perspective view of an analog IC chip electrically connected to a terminal pad on the semiconductor wafer according to the above-mentioned preferred embodiment of the present invention. Explanation of Symbols 11 Cutting Road 21 Internal Circuit 23 Fuse 10 Wafer Body 20 Analog 1C Chip 221 Terminal Teeth 22 Terminal Pad 13 200535999 30 Conductive Configuration 31 Conductive Element 32 Auxiliary Conductive Element
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