TW200532300A - Driving voltage generation device and method for controlling driving voltage generation device - Google Patents

Driving voltage generation device and method for controlling driving voltage generation device Download PDF

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Publication number
TW200532300A
TW200532300A TW094107686A TW94107686A TW200532300A TW 200532300 A TW200532300 A TW 200532300A TW 094107686 A TW094107686 A TW 094107686A TW 94107686 A TW94107686 A TW 94107686A TW 200532300 A TW200532300 A TW 200532300A
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Taiwan
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voltage
supply
transistor
node
aforementioned
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TW094107686A
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Chinese (zh)
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Tomokazu Kojima
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Matsushita Electric Ind Co Ltd
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Publication of TW200532300A publication Critical patent/TW200532300A/en

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    • BPERFORMING OPERATIONS; TRANSPORTING
    • B63SHIPS OR OTHER WATERBORNE VESSELS; RELATED EQUIPMENT
    • B63HMARINE PROPULSION OR STEERING
    • B63H23/00Transmitting power from propulsion power plant to propulsive elements
    • B63H23/32Other parts
    • B63H23/36Shaft tubes
    • FMECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
    • F16ENGINEERING ELEMENTS AND UNITS; GENERAL MEASURES FOR PRODUCING AND MAINTAINING EFFECTIVE FUNCTIONING OF MACHINES OR INSTALLATIONS; THERMAL INSULATION IN GENERAL
    • F16JPISTONS; CYLINDERS; SEALINGS
    • F16J15/00Sealings
    • F16J15/002Sealings comprising at least two sealings in succession

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Combustion & Propulsion (AREA)
  • Ocean & Marine Engineering (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Electronic Switches (AREA)

Abstract

A driving voltage generation device includes: a first selector section for receiving a plurality of first supply voltages and outputting one of the first supply voltages; a second selector section for receiving a plurality of second supply voltages and outputting one of the second supply voltages; first to fourth switches connected in series between the first selector section and the second selector section; a first specified voltage supply section for supplying a first specified voltage to a first interconnection node between the first switch and the second switch; and a second specified voltage supply section for supplying a second specified voltage to a second interconnection node between the third switch and the fourth switch. The first specified voltage supply section does not supply the first specified voltage when the first switch is on. The second specified voltage supply section does not supply the second specified voltage when the fourth switch is on. An output of the first specified voltage supply section has a lower impedance than that of the second selector section. An output of the second specified voltage supply section has a lower impedance than that of the first selector section.

Description

200532300 九、發明說明: 一、 【發明所屬之技術領域】 本發明係關於以交流(AC)驅動方法驅動液晶顯示面板等之 負載之驅動電壓之控制裝置及該裝置之控制方法,進一步詳細來 說為關於以低耐壓電路構成之驅動電壓產生裝置及該裝置之控制 方法。 二、 【先前技術】 為了以交流驅動方法(例如線性反轉驅動方法line Φ inversion driving method)驅動攜帶型機器(例如行動電話等) 之液晶顯示面板’現有之液晶驅動裝置具備用於控制供應到液晶 顯示面板之相對電極(counter electrode)之驅動電壓之驅動電壓 產生裝置。該驅動電壓產生裝置因應規定時間反轉驅動電壓之極 性。 (現有技術之驅動電壓產生裝置8) 〈結構與動作〉 圖12表示現有之驅動電壓產生裝置8之整體結構。該裝置8 包括:時間控制部81、VC0M電壓產生部82、VC0M用運算放^大器 φ 83、平滑電容C84、以及輸出端子85。該裝置8向液晶顯示面^ 之相對電極(圖略)輪流輸出驅動電壓VC0MH、VC0ML。 時間控制部81使用控制信號Sa、Sb控制由VC0M電壓產生部 82所產生之驅動電壓VC0MH、VC0ML之電壓值。 ° • VC〇M電壓產生部82包括:階梯電阻801H、801L,選擇部 802H、802L,以及開關電晶體SW3、SW4。 、。 &quot; 階梯電阻801H及選擇部802H具有如圖2(A)所示之結構。階 梯電阻801H產生不同電壓值之複數供給電壓。選擇部由複 數選擇電晶體所構成。並且,選擇部802Η因應來自時間控制部81 之控制信號Sa,選擇由階梯電阻801Η所產生之複數供給^壓&quot;之其 5 200532300200532300 IX. Description of the invention: 1. [Technical field to which the invention belongs] The present invention relates to a control device for driving voltage of a load such as a liquid crystal display panel by an alternating current (AC) driving method and a control method for the device, in further detail. The invention relates to a driving voltage generating device constituted by a low withstand voltage circuit and a control method of the device. 2. [Prior art] In order to drive a liquid crystal display panel of a portable device (such as a mobile phone, etc.) by an AC driving method (such as a linear inversion driving method line Φ inversion driving method), an existing liquid crystal driving device is provided for controlling supply to A driving voltage generating device for a driving voltage of a counter electrode of a liquid crystal display panel. This driving voltage generating device reverses the polarity of the driving voltage in response to a predetermined time. (Conventional Drive Voltage Generation Device 8) <Structure and Operation> FIG. 12 shows the overall structure of a conventional drive voltage generation device 8. The device 8 includes a time control section 81, a VC0M voltage generating section 82, a VC0M arithmetic amplifier φ83, a smoothing capacitor C84, and an output terminal 85. The device 8 outputs drive voltages VC0MH and VC0ML to the opposite electrodes (not shown) of the liquid crystal display surface ^ in turn. The time control unit 81 controls the voltage values of the driving voltages VC0MH and VC0ML generated by the VC0M voltage generating unit 82 using the control signals Sa and Sb. ° VCOM voltage generating section 82 includes step resistors 801H and 801L, selection sections 802H and 802L, and switching transistors SW3 and SW4. . &quot; The ladder resistor 801H and the selection section 802H have a structure as shown in Fig. 2 (A). The step resistor 801H generates a plurality of supply voltages with different voltage values. The selection section is composed of a plurality of selection transistors. In addition, the selection unit 802Η selects the complex voltage generated by the step resistor 801Η in response to the control signal Sa from the time control unit 81. 5 200532300

中之一。另外’控制信號Sa具有箄於失去γ科MQnilJ ,ns〇1H-2 ((4ίί v™ - ;) 由選㈣_所選擇之供給電壓,被輸出作為驅動i ,階梯電阻觀及選擇部·具有例如圖2⑻所示之 ίϊίϊ:上 值“由 8中選擇由階梯電阻所“之複Si: =L動由選擇部_所選擇之供給 開關電晶體SW3、SW4串聯連接到選擇部_與選擇部· t V(〇X 81 ^ TIMING ^ ^ 圖‘ί )„ )使控制信號S3、S4輪流為“高位準,,。告 之ΐ^,二』ίΓ”信? %、以為使開關電晶體SW3、SW4導ί SW4斷門:雷I * Λ,控制信號%、別為使開關電晶體SW3、 SW4斷開之電屋。由此,將來自選擇部隨之驅動電麼則腿盥 來自選擇部802L樣動電壓VC0ML輪流供應到 ^ 開關電晶體SW4之間之互連節點NC。 』爛电曰曰㈣3與 都運算放大11 83向輸出端子85輸出由髓電塵產生One of them. In addition, the control signal Sa has the following characteristics: the loss of the γ family MQnilJ, ns〇1H-2 ((4ίv ™-;)) The supply voltage selected by the selection unit _ is output as the driving i, the step resistance view and the selection unit. For example, as shown in Figure 2⑻, the upper value "selected by 8 by the step resistor" is the complex Si: = L is driven by the selection unit _ and the selection of the switching transistors SW3 and SW4 is connected in series to the selection unit _ and the selection unit · T V (〇X 81 ^ TIMING ^ ^ Figure 'ί) „) makes the control signals S3 and S4 turn to“ high level, ”. Tell me ^^ The letter "%" thought that the switching transistors SW3 and SW4 would lead SW4 to open the door: Thunder I * Λ, the control signal%, not to switch off the switching transistors SW3, SW4. Therefore, the driving voltage from the selection unit is followed by the 802L-like dynamic voltage VC0ML supplied from the selection unit to the switching node NC between the switching transistors SW4 in turn. 11 83 output to output terminal 85

It ff之驅動電壓職H、VC〇ML。平滑電容C84為為了平滑 姑士83之輸出變動而設,連接到位於VC0M用運算 放大盗83與輸出端子85之間之節點_以及接地節點之間。 輸出端子85向液晶顯㈣板之相龍極(於此將面板負 ΐ i不為液晶顯示面板之負載電容)供應VC0M用運算放大 裔W所輸出之驅動電壓VC0MH、VC0ML。 並且,此時滿足於·· (參考電壓VREFL ) ^ (參考電壓VSSH) $ (參考電壓VREFH); 200532300 以及 t ^壓VREFL) $ (茶考電壓VSSL) (參考電壓VREFH)。 (參考電壓VREFH之電壓值)二“+5V” (參考電壓VSSH、VSSL之電壓值)=“〇v” , (參考電壓VREFL之電壓值)=‘‘―5V”。 〈供給電壓之電壓值〉 點N80由ΐίΤίί產生之供給電壓之最大電壓值以參考節 ΪΓυγομΙ 1 VREFH= &lt;ί+5Γ ° 壓值為“+5ν”。並且,由階梯電阻隱所 電壓νΐ “ ί,敢、小本電壓值以參考節‘點腦1L_2之電位(參考 )表7F。因此,驅動電壓TOML之最小電壓值 局一t) V 〇It ff drive voltage H, VCOM. The smoothing capacitor C84 is provided for smoothing the output variation of the prince 83, and is connected between the node _ and the ground node between the VC0M operational amplifier 83 and the output terminal 85. The output terminal 85 supplies the driving voltages VC0MH and VC0ML output by the operational amplifier VC0M to the phase dragon pole of the liquid crystal display panel (here, the panel negative ΐi is not the load capacitance of the liquid crystal display panel). And, at this time, it is satisfied that (reference voltage VREFL) ^ (reference voltage VSSH) $ (reference voltage VREFH); 200532300 and t ^ voltage VREFL) $ (tea test voltage VSSL) (reference voltage VREFH). (The voltage value of the reference voltage VREFH) Two "+ 5V" (the voltage value of the reference voltage VSSH, VSSL) = "0v", (the voltage value of the reference voltage VREFL) = "-5V". <Voltage value of the supply voltage 〉 The maximum voltage value of the supply voltage generated by ΐίΤί at point N80 is based on the reference section ΪΓυγομΙ 1 VREFH = &lt; ί + 5Γ ° The voltage value is “+ 5ν”. And, the voltage νΐ is hidden by the step resistance ί, dare, small For the voltage value, refer to Table 7F for the potential (reference) of the reference point 'point brain 1L_2'. Therefore, the minimum voltage value of the driving voltage TOML is a t) V 〇

〈開關電晶體SW3、SW4之财壓〉 =電晶體SW3兩端之最大電位差為1〇v((參考電壓霞酔 參考電壓VREFL= —5V”))。另一方面,與開關電晶 冋樣的,開關電晶體SW4兩端之最大電位差也為1GV ((參 考電壓VREFH: “+5Γ )-(參考電壓VREFm。因此, 開關電晶體SW3、SW4需要具有ίον之耐壓。 (現有之驅動電壓產生裝置9) 〈結構與動作〉 圖13表示另一種現有之驅動電壓產生裝置9之整體結構。該 衷置9具備時間控制部91與vc〇M電壓產生部92,取代圖12所示 之時^控制部81與VC0M電壓產生部82。其他結構與圖12相同。 時間控制部91使用控制信號Sa及振幅情報Sc來控制由vc〇M $壓產生部92所產生之驅動電壓vc〇MH、vc〇ML之電壓值。振幅 情報Sc為具有對應驅動電壓vc〇MH與驅動電壓vc〇ML 幅)之電壓值之電壓(振幅電壓概FM)。 VC0M電壓產生部92包括供給用運算放大器901、選擇用運算 7 200532300 放大器902、供給用電晶體T903-1至Τ903_4以及電阻R9〇4與 R905,取代圖12所示之階梯電阻801L與選擇部802L。選擇用運 算放大器902、供給用電晶體Τ903-1及電阻R904構成電壓電流轉 換電路。因此,具有對應振幅情報Sc (振幅電壓VREFM)之電壓 值之電流值之供給電流流過供給用電晶體T903-1及電阻R9〇4。由 於供給用電晶體T903-1、T903-2構成電流鏡電路,並且由於供給 用電晶體T903-3、T903-4構成另一個電流鏡電路,因此,流過供 • 給用電晶體T903-1之供給電流流過電阻R905與供給用電晶^ . T903—4。因此,在電阻R905與供給用電晶體T903-4之間之互連 節點N905L產生驅動電壓VC0ML。 鲁 (驅動電壓VC0ML)=(驅動電壓VC0MH)-(振幅電壓VREFM) X (電阻 R905) / (電阻 R904) 其次’經由使開關電晶體SW3、SW4輪流導通,將來自供給用 運算放大器901之驅動電壓VC0MH與在節點N905L所產生之驅動 電壓VC0ML輪流供應到節點NC。 並且,於此滿足: (參考電壓VREFL)^(參考電壓VSSH)$(參考電壓VREFH)· 以及 (參考電壓VREFL ) S (參考電壓VSS) $ (參考電壓vrefH )。 φ 具體而言, (參考電壓VREFH之電壓值)=“+5V”, (參考電壓VSSH、VSS之電壓值)=“〇V” , (參考電壓VREFL之電壓值)=“-5V”。 . 〈供給電壓之電壓值〉 ^ 由階梯電阻別1Η所產生之供給電壓之最大電壓值以參考節 點Ν801Η-1之電位(參考電壓VREFEh “+5Γ )表示。因此%區動 電壓VC0MH之最大電壓值為“+5V”。另外,節點N905L所產生之 驅動電壓VC0ML之最小電壓值以參考節點N901L-5之電位(參考 電壓VREFL= “-5V”)表示。因此,與圖12所示之驅動電壓^生 8 200532300 裝置同=,_電晶體SW3、SW4必須具有i 〇v之耐壓。 【專利文獻1】特開2003-216256號公報 三、【發明内容】 一發明所欲解決之課題— 然而,在® 12所示之現有驅動電壓產生裝 位可成會降低到驅動電麼V(XML之雷懕信,,ni 2 電 ,之複數之選擇電差二擇(:: ί ™v} (((+fvt^ \REFL) ΗΛ' ϊ f值,5V ((+5V) - (〇V)),在選擇部_所含之複數 5V))(即其絕對最大額定ί ΐ51ϋν)°另—方面’當開關電晶體SW4從斷開切換為導通祐 導通切換為斷開時,位於選擇部“與開關 ΐ點_2L之電位可能會增加到鶴電㈣〇冊 + φ,/、選擇部802H同樣,在選擇部80乩所含之選 ίίίΐί需+ί具有雨之耐慶。如這般,選擇部麵、別2L Ϊ 要具有同度耐壓之電路結構(高耐壓電路)。 而 而古3二气電晶體之面^於低耐㈣晶體之面積。具體 i為〇V之電晶體之面積大約是耐壓為“5V,,之電 ΐί ’假設驅動賴職H、觀L具有64個不同電 時與圖12所不之選擇部_為由耐麗5v之選擇電晶 ^籌成情況相較之下,圖12所示之選擇部_之面=^曰 需東古匕二卜^’在5動電話等對液晶顯示面板之高精細化之 屬ΐ者液晶顯#面板之高精細化,必須更為提高驅動電 1#Αβ、Γ·να)Μί之電壓位準(即由階梯電阻801Η與801L所產生 之t、給電壓個數)。進而隨著供給電壓個數之增加,獅部8斤咖生 9 200532300 802L所含之選擇電晶體之個數也增加。如這般,.隨著液晶顯示面 板之高精細化,驅動電壓產生裝置之電路規模也增加,因此,降 低驅動電壓產生裝置之電路規模為重要。牛 在圖13所示之驅動電壓產生裝置9中,節點N9〇5L之電位可 能會增加到“+5V” 。因此,供給用電晶體T9〇3—4需要具有l〇v 之耐壓((+5V) - (-5V))。此外,供給用電晶體T9〇3-2、T9〇3—3 兩端之電位差可能會變成“(參考電壓VREFH)—(參考♦ VREFU ” ,因此供給用電晶體一2、τ_—3必須具士 1(^之 耐壓((+5V) —(-5V))。進而,在由供給用電晶體T9〇3—j盥 給用電晶體Τ903-2所構成之電流鏡電路中,由於最好是供给用 晶體Τ903-1與供給用電晶體Τ9〇3—2具有相同之電流特性、因: 供給用電晶體Τ903-1需要具有ιον之耐壓((+5V) — (―5V》。 5步匕由於供給用運算放大器9G1兩端之_差也有可能變 成(多考電壓VREFH)-(參考電壓VREFL),,;因此,佴仏 ίΐΐ2901必須由具有lov之耐壓之電晶體構成。如這i, j 2H、供給用放大器9〇1與供給電流產生部(選擇用 ί ΐίί &amp; 902、供給用電晶體T903_1至T903_4、以及電阻腿 ,、R905)&amp;必須為咼耐壓之電路結構(高耐壓電路 η 5,電晶體之耐壓越高,電晶體之反應速度越慢。並 電壓電曰:曰體在製程中之偏差(製程偏差)大於低耐壓 显Γ於^+1’由高耐壓電晶體構成之電流鏡電路之電流特性差 體形成之電流鏡電路。因此,在圖13所示之驅 之驅動電懕’難以精確產生對應控制信號Sa及振幅情報Sc 。因此,有關運算放大器方面,使用高 壓電晶體之驅動能力(反應速度)低於使用低耐 電壓本發明之目的在於··提供具有低耐壓電路之驅動 〜解決問題之手段— 200532300 按照本發明之_ 部、第2選擇部、第ϋ驅動產生裝置包括:第i選擇 規定電壓供給部。第 開關、第】規定電壓供給部、第2 第1供給電壓中之其部,接收複數第ί供給電壓並輸出該 ί接該第2供給電 連接到弟】選擇部盥繁 …弟】至弟4開闕串聯 第】開關與第2第1規定電壓供給部,向 規定電壓供給部,向M 連即點供應第i規定電壓。第2 給第2規定電^。向弟3開關與第4開關之間之第2互連節點供 到第= 2 _之間。第2開關連接 關之間。第4開關二連接到第2開關與第4開 關為導通時,· 1規定^部之間。當第1開 開關為導通時,第2 不供應第1規定_。當第4 5定_給部之輸㈣抗_。第1 之第3互連節點所產生之‘崖供庫到後p壯,關與第3開關之間 關與第3開關輪流導通,能夠將f/f冗。例如若使第2開 定電壓供給部之輸出 之^或第i規 之輸出或第2規定電壓供給部之輸外,,2選擇部 之輸㈣第2 部之輸^於此,裝置H弟 I,導通並使第2開關為斷開之狀態(將4開 ίί T換為使第2開關導通並使^二 先、刖,事先斷開第1開關,則能夠在第2 T之狀 前’將第1規定電壓供給部之輸出供應到第丨為導通 規定電壓供給部之輸出阻抗低於第2選擇部之輪抗:因= 200532300 互連節點處之電位穩定在第丨規定電壓之電壓 使第1及第2 _為導通並使第3開關為斷開 ^ = 部之輸出供應到第3互連節點之狀能)切拖发心(弟1 &amp;擇 並使第2 _為_之狀態前,事&amp;開第4開關 電壓供給部之輸恤抗低於第1選 擇。P之輪its阻抗’所叫2互連節點之顿穩 ίΐ壓Ϊ i=’經由將第1規定電壓之電壓值設為適當值I例 能夠以低耐壓電晶體構成)。同樣的,經 ί r^rriir ^ 弟擇邛各自之耐壓,從而縮減電路規模。 盘第2最?ί雷產生裝置進—步包括:第1階梯電阻 1 ΪΪΪ :弟階梯電阻,串聯連接到接收第1參考賴 Ϊΐίί,之N飾為自然數)第1供給電ί第”2階梯電阻 ίΪίΪΪί2 3參考電壓之第3參考節點與接收第4參考電 第2二二即=^產生不同電塵位準之Μ個(Μ為自然數) 個第=壓以Γ部,由第1階梯電阻所產生之Ν ί二 供:電壓中之其中之-。前述第1規忒 之第了輸人節i與Ξ第尸 於入ί 開關連接到接收前述第2規定電壓之第2 輸入即點與第2互連節點之間。當前述第丨_導通時,第52 200532300 關斷開二當前述第4開關導通時,第6開關斷開。 f前述驅動電壓產生裴置中,若在從將第2選 到連節點之狀態切換為使第2卿導通並使第3 f:;關“ 先導通第5開關,則能夠在第2開關從斷開切換 第丄互連節點供應第1規定電壓。同樣地以 ίί、=: ΐ應到第3互連節點之狀態切換為使第ί開 在G開;狀態前,事先導通第 ^。3開關攸斷開切換為導通前,向第2互連節點供應第2規定 前述卿之導通電阻小於前述第2階梯電阻。 月J述弟6開關之導通電阻小於前述第丨階梯電阻。 第i 區ί?ί控制裝置中,能夠使供應到第1互連節點之 使供库到第低於第2選擇部之輸出阻抗。同樣的,能夠 輸出ίίί第㈣之第2規定電壓之阻抗低於第1選擇部之 前述第1參考賴高於前述第2參考輕。前述第 2 ΐίίΐ?於前述第4參考電壓。前述第1規定電壓滿足:(第 招壓)^ (第1規定電壓)$ (第1參考電壓)。前述第2 考iif滿足:(第4參考電壓)$ (第2規定電壓)$ (第3參 如前述驅動電壓產生裝置中,能夠使得在第1選擇部之輪入 、里if出側之電位差比現有技術中還小。同樣的,能夠使得第2 k擇j之巧入側與輸出側之電位差比現有技術中還小。 個筮ftf,前述第1階梯電阻包含N個第1分接頭(ΐ_〇Ν 個ΐ ί t接頭輸出前述Ν個供給電壓。前述第2階梯電阻包含Μ =Ζ为接頭。Μ個第2分接頭輸出前述Μ個供給電壓。前述 笛9 ^梯電阻所含個第1分接頭。前述第2選擇部包含Μ個 k擇電晶體。Μ個第2選擇電晶體,對應前述第2 Ρ皆梯電阻所 13 200532300 Γί接 接”個第1選擇電晶體分別連制所對應之第 具有ΐΓ;第riTi?產生裝置進-步包括控制部。控制部 模式中,控制部1、4第第6開關電晶體^ ^ 述第卜Κίΐ°在第2模式中’控制部使前 開關電晶體導通2 斷f,並使前述第2、第4及第5 開關電晶體導通,ίί前,^制部使前述第卜第2及第6 第4模式中,控制部SSI㈡= 使前述第2、第4及第5開關電晶體斷開弟6開關電曰曰體導通,並 擇部產^裝編:第1選 以及輸出第2規定糕之第2規定電祕^1規疋部’ ί?Ϊί^&quot;ίίίί^ 1 〇 #ϊ 線連接到供給電流產生部與第4關。第丨電阻, 配 節點與位於第2配線之第2節點之間。鉗位電路么 =1配線’將該第丨配線之電位限制在規定範圍内 ^ 電f供給部向第1開關與第2開關之間之第!互連節點幹笛) 2定電壓供給部,向第3開關與第4開關;之第2 ΐΐ 職。第1開關連接到第1選擇雜ί 2 開關之巧。弟2開關連接到第】開關與第3開關之間 、 連接到第2開關與第4開關之間。第4開關連接 = 給電流產生部之間。當第1開關導通時,第: 14 200532300 規定電壓。當第4賴導通時’第2規定電壓供給部不 =弟2規定賴。第丨規定縣供給部之輸出阻抗低於供給電 j生部輸出之阻抗。第2規定電壓供給部之輸纽抗低 選擇部之輸出阻抗。 力 前述驅動電壓產生裝置中,由於能夠使供給電流產生部中之 ^入側與輸出侧之間之電位差小於現有技術中之電位差(例如能 =低耐魏晶體構成供給電流產生部)。經由此,能夠縮減電路 規模。<Financial voltage of the switching transistors SW3 and SW4> = The maximum potential difference between the terminals of the transistor SW3 is 10v ((reference voltage Xia reference voltage VREFL = -5V "). On the other hand, it is the same as the switching transistor The maximum potential difference across the switching transistor SW4 is also 1GV ((reference voltage VREFH: "+ 5Γ)-(reference voltage VREFm. Therefore, the switching transistors SW3 and SW4 need to have a withstand voltage of ίον. (Existing driving voltage Generating device 9) <Structure and operation> Fig. 13 shows the overall structure of another conventional driving voltage generating device 9. The device 9 includes a time control section 91 and a vcOM voltage generating section 92 instead of the time shown in Fig. 12 The control unit 81 is the same as the VC0M voltage generating unit 82. The other structures are the same as those of FIG. 12. The time control unit 91 uses the control signal Sa and the amplitude information Sc to control the driving voltage vcoMH generated by the vcoM $ voltage generating unit 92, The voltage value of vcOM. The amplitude information Sc is a voltage (amplitude voltage approximate FM) having a voltage value corresponding to the driving voltage vcOM and the amplitude of the driving voltage vcOM. The VC0M voltage generating unit 92 includes a supply operational amplifier 901, Selection for operation 7 200532300 The device 902, the supply transistors T903-1 to T903_4, and the resistors R904 and R905 replace the ladder resistor 801L and the selection unit 802L shown in FIG. 12. The selection operational amplifier 902, the supply transistor T903-1, and the resistor R904 A voltage-current conversion circuit is configured. Therefore, a supply current having a current value corresponding to the voltage value of the amplitude information Sc (amplitude voltage VREFM) flows through the supply transistor T903-1 and the resistor R904. Since the supply transistor T903-1 And T903-2 constitute a current mirror circuit, and since the supply transistors T903-3 and T903-4 form another current mirror circuit, the supply current flowing through the supply transistor T903-1 flows through the resistor R905 and Supply transistor ^. T903-4. Therefore, the driving node VC0ML is generated at the interconnection node N905L between the resistor R905 and the supply transistor T903-4. Lu (driving voltage VC0ML) = (driving voltage VC0MH)-(amplitude) Voltage VREFM) X (resistance R905) / (resistance R904) Next, by turning on the switching transistors SW3 and SW4 alternately, the driving voltage VC0MH from the supply operational amplifier 901 and the driving voltage VC0ML generated at the node N905L are alternately supplied. And the node NC, thereto satisfied: (reference voltage VREFL) ^ (reference voltage VSSH) $ (reference voltage VREFH) · and (a reference voltage VREFL) S (refer to the VSS voltage) $ (reference voltage VREFH). φ Specifically, (the voltage value of the reference voltage VREFH) = "+ 5V", (the voltage value of the reference voltage VSSH, VSS) = "0V", (the voltage value of the reference voltage VREFL) = "-5V". <Voltage value of the supply voltage> ^ The maximum voltage value of the supply voltage generated by the step resistor 1Η is represented by the potential of the reference node N801Η-1 (reference voltage VREFEh "+ 5Γ). Therefore, the maximum voltage of the dynamic voltage VC0MH in the% zone The value is “+ 5V”. In addition, the minimum voltage value of the driving voltage VC0ML generated by the node N905L is represented by the potential of the reference node N901L-5 (reference voltage VREFL = “-5V”). The voltage is the same as that of 200532300. The transistors SW3 and SW4 must have a withstand voltage of i OV. [Patent Document 1] JP 2003-216256 III. [Content of the Invention] A problem to be solved by the invention— However, the existing driving voltage generation device shown in ® 12 can be reduced to the driving voltage V (XML Thunder Letter, ni 2 power, the plural choice of the difference between the two options (:: ί ™ v) (((+ fvt ^ \ REFL) ΗΛ 'ϊ f value, 5V ((+ 5V)-(〇V)), 5V included in the selection section)) (that is, its absolute maximum rating, ΐ51ϋν) ° other —Aspect 'When the switching transistor SW4 is switched from off to on The potential of the guanxi point _2L may increase to Hedian ㈣ 册 0 + φ, /, the selection section 802H Similarly, the selection included in the selection section 80 乩 ίίΐ ί + + has the ability to bear rain. As such, select The surface and other 2L L must have the same voltage withstand voltage circuit structure (high withstand voltage circuit). And the surface of the ancient 3.2 gas crystal ^ is the area of the low withstand voltage crystal. The specific i is 0V of the transistor The area is about 5V, and the electric power is' assumed that the driver Lai H and Guan L have 64 different power hours and the selection part that is not shown in Figure 12 _ The situation is caused by the selection of the Nai Li 5v transistor ^ In contrast, the face of the selection section shown in FIG. 12 = ^ said the need for the ancient ancient sword ^ ^ '5 mobile phones and other high-definition liquid crystal display panel belongs to those who LCD display # panel of high-definition To increase the voltage level of the driving power 1 # Αβ, Γ · να) Μί (that is, the number of t and voltages generated by the step resistors 801Η and 801L). As the number of supply voltages increases, The number of selective transistors included in the Lion Department 8 catties 9 200532300 802L has also increased. As such, with the high definition of LCD panels, The circuit scale of the dynamic voltage generating device also increases, so it is important to reduce the circuit scale of the driving voltage generating device. In the driving voltage generating device 9 shown in FIG. 13, the potential of the node N9055L may increase to "+ 5V ". Therefore, the supply transistor T90-3-4 needs to have a withstand voltage ((+ 5V)-(-5V)) of 10v. In addition, the supply transistor T90-0-2, T90-03-3 The potential difference between the two ends may become "(reference voltage VREFH)-(reference ♦ VREFU", so the supply transistor 1-2, τ_-3 must have a withstand voltage of 1 (^ ((+ 5V)-(-5V) ). Furthermore, in the current mirror circuit composed of the supply transistor T903-j and the supply transistor T903-2, it is preferable that the supply transistor T903-1 and the supply transistor T903-2 have The same current characteristics and reasons: The supply transistor T903-1 needs to have a withstand voltage of ιον ((+ 5V) — (-5V). The 5-step dagger may also become (multiple) due to the difference between the two ends of the supply operational amplifier 9G1. (Reference voltage VREFH)-(reference voltage VREFL) ,; therefore, 佴 仏 ΐΐ 2901 must be composed of a transistor with lov voltage. For example, i, j 2H, supply amplifier 901 and supply current generator (select With ί ΐ ί &amp; 902, supply transistors T903_1 to T903_4, and resistance legs, R905) &amp; must be a circuit structure with high voltage resistance (high voltage circuit η 5, the higher the voltage resistance of the transistor, the transistor The slower the reaction speed. The voltage difference is: the deviation of the body in the manufacturing process (process deviation) is greater than the low withstand voltage. Γ ^ + 1 'is formed by the current characteristic difference of the current mirror circuit composed of a high withstand piezoelectric crystal. The current mirror circuit. Therefore, the drive 'It is difficult to accurately generate the corresponding control signal Sa and amplitude information Sc. Therefore, with regard to the operational amplifier, the driving ability (response speed) using a high-voltage transistor is lower than using a low withstand voltage. The object of the present invention is to provide a low withstand voltage. Circuit driving ~ means for solving problems — 200532300 According to the present invention, the _ part, the second selection part, and the third drive generation device include: the i-th selection predetermined voltage supply part. The first switch, the first] predetermined voltage supply part, and the second 1 part of the supply voltage, receiving a plurality of supply voltages and outputting the connection to the second supply power] Selecting the department to wash the fan ... brother] to the brother 4 opening and closing in series the first] switch and the second first regulation The voltage supply unit supplies the i-th specified voltage to the M-connected point. The second provides the second specified voltage ^. The second interconnection node between the third switch and the fourth switch is supplied to the second = 2 _. The second switch is connected between the off. When the second switch is connected to the second switch and the fourth switch is on, · 1 is specified between the two parts. When the first on switch is on, the second is not Supply No. 1 _. When No. 4 5 _ give The input and output of the ministry are _. The 'suppliers' generated by the 1st and 3rd interconnection nodes will be strong, and the switches between the 3rd and 3rd switches will be turned on in turn, which can make f / f redundant. For example, If the output of the second on-set voltage supply unit or the output of the i-th regulation or the output of the second prescribed voltage supply unit is made, the input of the 2 selection unit and the output of the second unit are here. Turn on and turn the second switch off (change 4 to open T to turn on the second switch and turn ^ two first, 刖, turn off the first switch in advance, you can The output impedance of the first specified voltage supply section is supplied to the output impedance of the first specified voltage supply section. The impedance of the second selection section is lower than the round reactance of the second selection section: = 200532300 The potential at the interconnection node is stabilized at the voltage of the first specified voltage, making the first 1 and 2 _ are turned on and the 3rd switch is turned off ^ = the state of the output of the part is supplied to the 3 interconnect node. Previously, the switching impedance of the fourth switching voltage supply unit was lower than that of the first option. The stability of the P-wheel's impedance ′ called 2 interconnected nodes ΐ ΐ Ϊ i = ′ By setting the voltage value of the first predetermined voltage to an appropriate value (for example, it can be composed of a low-withstand piezoelectric crystal). In the same way, the 邛 r ^ rriir ^ brothers choose their respective withstand voltage, thereby reducing the circuit scale. The second step of the thunder generation device further includes: the first step resistor 1 ΪΪΪ: the step ladder resistor, connected in series to receive the first reference Lai Ϊΐ ί, where N is a natural number) the first power supply ″ the second ″ Step resistance ίΪίΪΪί 2 The 3rd reference node of the 3rd reference voltage and the 2nd 22nd receiving the 4th reference voltage = ^ produces M pieces of different electric dust levels (M is a natural number) The two resistances generated by the ladder resistance: one of the voltages.-The first input section i and the first input section of the first regulation above are connected to the second input that receives the aforementioned second specified voltage. Between the point and the second interconnection node. When the aforementioned 丨 _ is turned on, the 52nd 200532300 is turned off. When the aforementioned 4th switch is turned on, the 6th switch is turned off. From switching the state from the second selection to the connected node to turning on the second node and turning on the 3rd f :; off, if the 5th switch is turned on first, the second interconnection node can be switched from off when the 2nd switch is switched off. Specified voltage. Similarly, with ί, =: 互连 should be switched to the state of the third interconnected node so that the first open, before the G open; state, turn on ^ in advance. 3 Before the switch is turned off and switched on, the second regulation is supplied to the second interconnection node. The on-resistance of the aforementioned transistor is smaller than the aforementioned second step resistance. The on-resistance of the switch 6 is smaller than the aforementioned step resistance. In the control device of the i-th region, the output impedance of the supply to the first interconnection node can be lower than that of the second selection part. Similarly, the impedance capable of outputting the second specified voltage of the second one is lower than the aforementioned first reference which is higher than the aforementioned second reference. The second reference voltage is the fourth reference voltage. The aforementioned first specified voltage satisfies: (No. 1 voltage) ^ (No. 1 specified voltage) $ (No. 1 reference voltage). The aforementioned second test iif satisfies: (the fourth reference voltage) $ (the second prescribed voltage) $ (the third parameter is the same as the driving voltage generating device described above, which can make the potential difference between the turn-in and the if-out side of the first selection section). It is smaller than that in the prior art. Similarly, the potential difference between the input side and the output side of the 2 kth option can be made smaller than that in the prior art. One ftf, the aforementioned first step resistor includes N first taps ( ΐ_〇Ν ΐ 接头 t connector outputs the aforementioned N supply voltages. The aforementioned second step resistor includes M = Z as a connector. The M second tap connector outputs the aforementioned M supply voltages. The aforementioned flute 9 ^ ladder resistor contains a The first tap. The aforementioned second selection section includes M k-selective transistors. The M second-selective transistors correspond to the aforementioned second PJT resistors. 13 200532300 Γ ”The first selectable transistors are connected in series. Correspondingly, ΐΓ; riTi? Generating device further includes a control section. In the control section mode, the control section 1, 4 and the 6th switching transistor ^ ^ Said in the second mode 'Control section' Turn on the front switch transistor 2 and turn off f, and enable the second, fourth, and fifth switch transistors Turn on, before the control unit makes the aforementioned second, second, and sixth fourth modes, the control unit SSI㈡ = turns off the second, fourth, and fifth switching transistors, and the six switches are turned on. And select the Ministry of Production ^ assembly and editing: the first selection and output of the second regulation of the second regulation of the second regulation ^ 1 regulation of the Ministry 'ί? Ϊί ^ &quot; ίίίί ^ 1 〇 # ϊ The line is connected to the supply current generation unit and the first 4 off. The first resistance, the matching node is located between the second node of the second wiring. The clamp circuit = 1 wiring 'limits the potential of the first wiring to a specified range ^ The power supply unit to the first switch And the second switch! Interconnect node dry flute) 2 constant voltage supply unit, to the third switch and the fourth switch; the second job. The first switch is connected to the first selection miscellaneous 2 switch The second switch is connected between the first and third switches, and between the second and fourth switches. The fourth switch is connected between the current generator. When the first switch is on, the first: 14 200532300 specified voltage. When the 4th Lai is turned on, the 2nd specified voltage supply unit is not equal to the 2nd specified Lai. The output impedance of the first county supply unit is lower than the supply. The impedance of the output section. The output impedance of the second specified voltage supply section and the output impedance of the low-selection section. In the aforementioned driving voltage generating device, the voltage between the input side and the output side of the supply current generating section can be adjusted. The potential difference is smaller than the potential difference in the prior art (for example, a low current-resistant crystal can constitute a supply current generating unit). By this, the circuit scale can be reduced.

★最好是,前述驅動電壓產生裝置進一步包括第j差動放大電 第、1差動放大電路連接到位於前述第1配線之第Ϊ節點與前 ^ 1選擇部之間。前述供給電流產生部包括:第1及第2供給 一^曰曰體’第2電阻,第2差動放大電路,第1及第2鉗位電晶 二^1供給用電晶體及第2電阻串聯連接到第丨參考節點與第2 j節點之間。第2差動放大電路在其-方輸人端子連接第i供 晶體與第2電阻之互連節點,在另一輸入端子接收前述振 號,f輸出端子連接第1供給用電晶體之閘極。第2供給用 =曰體、第1鉗位用電晶體及第2钳位用電晶體串聯連接到位於 ί曰1己線之第2節點與前述第1參考節點之間。前述第2供給用 楚曰曰體連_第1參考節賴第丨綠電晶體之間,在閘極接收 f巧給用電晶體之,所產生之閘極電壓。第1練電晶體連 =第i供給用電晶體與第2鉗位電晶體之間,在閘極接收第1 垄。第2钳位電晶體連接到位於第2配線之第2節點與第i钳 位電晶體之間,在閘極接收第2偏壓。 月》j述驅動電壓產生裝置中,能夠使得第丄及第2供給用電 =曰ί耐?比現有技術中還低。因此,由於能夠降低第1供給用 =體及第2供給用電晶體之製程偏差,所以能夠降低第i供給 電J體及,2供給用電晶體之電流特性之差異。進而由於能夠 从!4第、1及第2供給用電晶體之各自之汲極電壓之變動 ,因此能 夠緩和絲電壓依存性之辟。經由此,能夠高鮮確產生具有 15 200532300 對應振幅情報之電壓值之驅動電壓。 最好是,前述第1偏壓之電壓絲示前述第丨錄 之閘極-源極間電壓相等於前述振幅情報之電廢值。 最好疋,前述第2偏壓之電壓值相等於前述第2鉗 體之閘極-源極間電壓。 甘仅用電日日 取好(,進-步具備第1絲放大電路。第丨差動放大電路 連接到位於前述第1配線之第1節點與前述第丨選擇部之間。 給電流產生部包括第1到第4供給用電晶體,第2電阻,第 動放大電路、以及第1到第3钳位用電晶體。第1供給 及第2電阻串聯連接到第i參考節點與第2參考節點之間。第2 _差動放大電路,其一方之輸入端子連接到第】供給用電晶體與第2 電阻之互連節點,在另-輸人端子接收前述振幅錢,並在輸出 ,子連接第1供給用電晶體之閘極。第2供給用電晶體、第1及 第2鉗位電晶體、以及第3供給用電晶體串聯連接到第丨參考節 點與第3參考節點之間。第3钳位用電晶體及第4供給用電晶體 ^聯連接到位於前述第2配線之第2節點與第3參考節點之間。 第2供給用電晶體連接到第丨參考節點與第丨鉗位用電晶體之間, 在閘極接收第1供給用電晶體之閘極所產生之閘極電壓。第1鉗 位電晶體連接到第1供給用電晶體與第2鉗位電晶體之間,在閘 馨極接收第1偏壓。第2鉗位電晶體連接到第1鉗位電晶體與第3 供給用電晶體之間,在閘極接收第2偏壓。第3供給用電晶體連 ,到第2鉗位電晶體與第3參考節點之間,其閘極連接到其汲極。 第3鉗位電晶體連接到位於前述第2配線之第2節點與第4供給 • 用電晶體之間,在閘極接收第3偏壓。第4供給用電晶體連接到 第3鉗位電晶體與第3參考節點之間,在閘極接收第3供給用電 &quot; 晶體之閘極所產生之閘極電壓。 在前述驅動電壓產生裝置中能夠使第1到第4供給用電晶體 之耐壓比現有技術還低。因此,能夠降低流過第1供給用電晶體 之電流之電流值與流過第4供給用電晶體之電流之電流值之差異。 16 200532300 敢子疋鈉述弟2甜位用電晶體之閘極-源極間電壓等於前十 源極間之電壓。前述第2及第^ 體之問Μ極tit難-祕麵及/或箱3甜位電晶 電路賴產生裝置進—步包括:第1差動放大 第1差動放大電路連接到前述第1選 選擇部與_ Γ開第2差滅_ ’連制前述第2 電路電壓赶裝置進—步包括:第1差動放大 配線^第n盥·^路。第1差動放大電路連接到位於前述第1 到第1選擇部之間。第2差動放大電路連接 置。驅動電壓^生萝“種狀況’控制方法控制驅動電壓產生裝 第6開關電晶體。Hί選擇部、第2選擇部、第1到 第i供給電壓中之其中J:擇輸出該 連接中之其中之-。第1至第4開關,串聯 ί=;=ΐ;ί:=。;5開關,連接到第1互 點與接收第2規定i間。第6關’連接到第2互連節 於第&quot;關*第4 2輸人節點之間,該第2互連節點位 壓之阻抗“第2 由第5開關所供應之第1規定電 規定電壓之阻抗低於以之登=阻t經由第6,所供應之第2 行步驟(a)、步驟(b)、。則述控制方法中執 第卜第2及第6開關斷與步驟(D)。在步驟(A),使 Ϊ二f第6開關斷開並使第3、第4及第5開ί ία):« 3 (B) ^ ^ 弟開關導通並使第2 關導通,其次使第1及第6 17 200532300 &amp;⑴^4及第5賴斷開。當從步驟(B)切換到步 第3( ^關If订^)。在步驟(D) ’使第2開關導通同時使 關斷開^ ” 人使4 4及第6開關導通同時使第1及第6開 在錢驅動龍產线置之控制方法巾, ll3(^3 )2 rnl^ :於第1規二雷互連節點供應第1規定電壓。在步驟⑹中, ^拉ϊ 1,疋電壓正被供應到第1互連節點,第1互連節點之雷 穩疋在第1規定電壓之電壓值。在步驟(β)中, ^ =應第1選擇部之輸出。此外,向第2互連節點= % (所f 2⑼中’由於第2規定電壓正被供給到第2互連節 ΐ’m連節點之電位穩定在第2規找壓之電壓值於 liiH1規定龍(第2規定電壓)之電壓值設成適當值, = 之電位差。因此’能夠降低第1選擇部與第2 壓34般,由於能夠降低第1及第2選擇部之各自 之耐壓,從而能夠縮減驅動電壓產生裝置之電路規模。 如上所述,由於能夠使第1選擇部(第2選擇部)中 側與輪出側之間之電位差小於現有技術巾電 :★ Preferably, the driving voltage generating device further includes a j-th differential amplifier circuit and a first differential amplifier circuit connected between the first node of the first wiring and the first ^ selection section. The supply current generating unit includes a first and a second supply resistor, a second resistor, a second differential amplifier circuit, first and second clamp transistors, and a second resistor and a second resistor. Connected in series between the 丨 reference node and the 2j node. The second differential amplifier circuit is connected to the interconnection node between the i-th crystal and the second resistor at the input terminal of the second differential amplifier, receives the aforementioned vibration signal at the other input terminal, and the f-output terminal is connected to the gate of the first supply transistor. . The second supply transistor, the first clamp transistor, and the second clamp transistor are connected in series between the second node on the first line and the aforementioned first reference node. The above-mentioned second supply device Chu Yuyue Tilian _ the first reference section depends on the gate voltage between the green transistor and the gate electrode. The first transistor is connected between the i-th supply transistor and the second clamp transistor, and receives the first ridge at the gate. The second clamp transistor is connected between the second node located on the second wiring and the i-th clamp transistor, and receives a second bias voltage at the gate. In the above-mentioned "j" drive voltage generating device, the first and second supply power can be made equal to 耐? Lower than in the prior art. Therefore, since the process deviation of the first supply transistor and the second supply transistor can be reduced, the difference in current characteristics between the i-th supply transistor and the second supply transistor can be reduced. Furthermore, since it is possible to change the respective drain voltages of! 4th, 1st, and 2nd supply transistors, it is possible to ease the dependence of the wire voltage. As a result, a driving voltage having a voltage value corresponding to the amplitude information of 15 200532300 can be generated with high accuracy. Preferably, the voltage wire of the first bias voltage indicates that the voltage between the gate and the source of the first record is equal to the electrical waste value of the amplitude information. Preferably, the voltage value of the second bias voltage is equal to the gate-source voltage of the second clamp body. Gan only use electricity every day (the first step is equipped with the first wire amplifier circuit. The first differential amplifier circuit is connected between the first node of the first wiring and the first selection section. The current generating section It includes the first to fourth supply transistors, the second resistor, the first amplifier circuit, and the first to third clamp transistors. The first supply and the second resistor are connected in series to the i-th reference node and the second reference. Between the nodes. 2nd_differential amplifier circuit, one of its input terminals is connected to the interconnecting node of the supply transistor and the 2nd resistor, and the other input terminal receives the aforementioned amplitude, and at the output, the The gate of the first supply transistor is connected. The second supply transistor, the first and second clamp transistors, and the third supply transistor are connected in series between the reference node and the third reference node. The third clamp transistor and the fourth supply transistor are connected between the second node and the third reference node located in the aforementioned second wiring. The second supply transistor is connected to the 丨 reference node and the 丨Between the clamping transistor, the gate receiving the first supply transistor at the gate The generated gate voltage. The first clamp transistor is connected between the first supply transistor and the second clamp transistor, and receives the first bias voltage at the gate. The second clamp transistor is connected to the first Between the clamp transistor and the third supply transistor, a second bias voltage is received at the gate. The third supply transistor is connected between the second clamp transistor and the third reference node. It is connected to its drain. The third clamp transistor is connected between the second node and the fourth supply / use transistor located in the aforementioned second wiring, and receives a third bias voltage at the gate. The fourth supply transistor is connected Between the third clamp transistor and the third reference node, the gate receives the gate voltage generated by the gate of the third supply &quot; crystal. The aforementioned driving voltage generator can make the first to the first The voltage resistance of the 4 supply transistor is lower than that of the conventional technology. Therefore, the difference between the current value of the current flowing through the first supply transistor and the current value of the current flowing through the fourth supply transistor can be reduced. 16 200532300 The voltage between the gate and the source of the sweet-bit transistor is equal to the voltage between the top ten sources The above-mentioned second and third body of the M pole are difficult to retighten-the secret face and / or the box 3 sweet-bit transistor circuit depends on the generation device-further includes: a first differential amplifier, a first differential amplifier circuit connected to the foregoing The first selection unit and _ Γ open the second differential circuit _ 'connect the aforementioned second circuit voltage driving device further-including: the first differential amplifier wiring ^ nth ^ circuit. The first differential amplifier circuit connection It is located between the first to the first selection section. The second differential amplifier circuit is connected. The driving voltage is controlled by a "state" control method. The driving voltage is generated by a sixth switching transistor. The selection section, the second Selection section, among the first to i-th supply voltages, J: Select output of one of the connections-. 1st to 4th switches, connected in series ί =; = ΐ; ί: = .; 5 switches, connected to the first 1 mutual point and receiving the second rule i. Level 6 'is connected to the second interconnecting section between the &quot; Gate * and the 4th input node. The impedance of the bit voltage of the second interconnecting node is "the second specified power supplied by the fifth switch. The impedance of the specified voltage is lower than the impedance = resistance t via step 6, step 2 (a), step (b), which is supplied in the second line. Then, the control method of the second and sixth switch off and step ( D). In step (A), the second switch 6 is turned off and the 3rd, 4th, and 5th switches are opened. Ία): «3 (B) ^ ^ The switch is turned on and the second switch is turned on. Next, turn off the 1st and 6th 17 200532300 &amp; ⑴ ^ 4 and 5th Lai. When switching from step (B) to step 3 (^ 关 IfIf ^). In step (D) 'make the second switch The control method turns on and off at the same time ^ ”The control method of the person who makes the 4 4 and the 6 switch simultaneously makes the 1 and 6 switches on the money driving dragon production line, ll3 (^ 3) 2 rnl ^: In the first regulation Erlei Interconnection Node supplies the first specified voltage. In step (1), the voltage is being supplied to the first interconnection node, and the lightning of the first interconnection node is stabilized at the voltage value of the first specified voltage. In step (β), ^ = should be the output of the first selection section. In addition, to the second interconnection node =% (all f 2 ⑼ ', because the second prescribed voltage is being supplied to the second interconnection section ΐ' m, the potential of the connection node is stabilized at the second regulation voltage, and the voltage value is specified in liH1 The voltage value of the dragon (second prescribed voltage) is set to an appropriate value, = potential difference. Therefore, 'the first selection portion and the second voltage 34 can be reduced, and since the respective withstand voltage of the first and second selection portions can be reduced, As a result, the circuit scale of the driving voltage generating device can be reduced. As described above, since the potential difference between the middle side and the wheel exit side of the first selection section (second selection section) can be made smaller than that of the conventional technology:

^ 1 2 〇, ,b :Z g擇权各自之耐壓,從而能_減驅動賴產生裝置之電路規 四、【實施方式】 以下參考附目,詳細說明本發明之實施形態。在各 用相同符號表示同一或相當部分,並且不重複說明。 (第1實施形態) &lt;整體結構〉 圖1表示本發明第1實施形態之驅動電壓產生裝置1之整體 200532300 結構。裝置1包括:時間控制部11、VC0M電壓產生部12、vc〇M 用運算放大器13、平滑電容C14以及輸出端子15。該裝置丨控制 用於以父&gt;謎動方法(線性反轉麟方法)驅動液晶顯示面板之 驅動電壓W:0MH、VC0ML。換言之,該裝置1因應時間信號TmiNG, 向液晶顯示面板之相對電極(圖略)輸出驅動電壓或vc〇ML。 時間控制部11使用控制信號Sa來控制由vc〇M電壓產生部 12所輸出之驅動電壓VC0MH之電壓值。並且,時間控制部u使用 控制信號Sb來控制由·Μ電壓產生部12所輸出之驅動電壓 VC0ML之電壓值。並且,時間控制部Π因應來自 頂哪,輸出控制信號S1至S6。時間信號TIMING表示 晶顯示面板之相對電極之驅動電壓從驅動電壓vc〇順切 電壓VC0ML(或從驅動電壓VC0Ml切換為驅動電壓 之^ 画電壓產生職因應從__部η所輸 Sa、Sb,產生驅動電壓VC0MH、VC0ML。並且vc〇M電壓產 11所輸出之控制信號S1至S6,輸出驅動電壓 疆用運算放大器13向輸出端子15輪出由聰 部12所供應之驅動電壓VC0MH、VC0ML。 十為了平滑VC0M用運算放大器13之輪出變動,設置了平滑電 谷C14 ’並連接到位於VC0M用運算放大器13與輸出 之節點N14與接地節點之間。 子15之間 於出Ic=運ΐί ί3所輸出之驅動賴職、舰經由 晶顯示面板之相魏極(於此面板負載 C (LC)不為液晶顯示面板之負載電容)。 、 &lt; VC0M電壓產生部12之内部結構&gt; 部12包括:階梯電阻1G1H、101L, 選擇部102H、102L,以及開關電晶體SW1到泖6。 階梯電阻101H連接到接收參考電壓丽 刚ΠΜ無收參考電壓VSSH之參考節點眶H—2之 19 200532300 生複數不同電壓值之供給電壓。選擇部102H因應來自時 11之控制信號Sa,選擇由階梯電阻1〇1H所產纟之複數二= 中之其中一個電壓。 ^…冤壓 階梯電阻101L連接到接收參考電壓VSSL之表 N101L-1與接收參考電壓丽FL之參考節點刪L_2之間= 生複數不同賴值之供給電壓。選擇部·因應來自時 ^ 11之控制信^ Sb,選擇由階梯電阻祖所產生之複數供^= 中之其中之。 之間 開關電晶體SW1至SW4串聯連接到選擇部丨〇2{{與選擇部〗n 。由選擇冑麵所選擇之供給電壓作為鶴賴νω 應到開關電晶體SW卜由選擇部職所選擇之供給電壓 = 電壓VC0ML被供應到開關電晶體SW2。開關電晶體測連接&amp;選 部102H與開關電晶體SW3之間,在間極接收來自時間控制 之控條5虎S1。開關電晶體SW3連接到開關電晶體SW1與開關 晶體SW4之間,在閘極接收來自時間控制部u之控制信^ 關電曰曰體SW4連接到開關電晶體SW3與開關電晶體撕之間 閘極接收來自時間控制部U之控制信號S4。^ 1 2 0,, b: Z g selects the respective withstand voltage, so that the circuit specification for driving the Lai generator can be reduced. [Embodiment] The following describes the embodiment of the present invention in detail with reference to the appended items. In each case, the same or equivalent parts are denoted by the same symbols, and descriptions are not repeated. (First Embodiment) &lt; Overall Structure> Fig. 1 shows the overall 200532300 structure of a driving voltage generating device 1 according to a first embodiment of the present invention. The device 1 includes a time control section 11, a VC0M voltage generating section 12, an operation amplifier 13 for vcOM, a smoothing capacitor C14, and an output terminal 15. This device controls the driving voltage W: 0MH, VC0ML for driving the liquid crystal display panel by the parent &gt; mystery method (linear inversion method). In other words, the device 1 outputs a driving voltage or vCOML to the opposite electrode (not shown) of the liquid crystal display panel in response to the time signal TmiNG. The time control section 11 uses the control signal Sa to control the voltage value of the driving voltage VCOMH output by the vcom voltage generating section 12. Further, the time control unit u uses the control signal Sb to control the voltage value of the driving voltage VC0ML output from the Μ voltage generating unit 12. In addition, the time control unit Π outputs control signals S1 to S6 in response to the source. The timing signal TIMING indicates that the driving voltage of the opposite electrode of the crystal display panel is switched from the driving voltage vc0 to the tangential voltage VC0ML (or switched from the driving voltage VC0M1 to the driving voltage ^) The voltage generation function is based on the Sa and Sb input from the __ Department η, The driving voltages VC0MH and VC0ML are generated, and the control signals S1 to S6 output by the vcOM voltage output 11 are output. The operational voltage 13 is used by the operational amplifier 13 to output the driving voltages VC0MH and VC0ML supplied by the smart unit 12 to the output terminal 15. In order to smooth the rotation of the VC0M op amp 13, the smoothing valley C14 'is set and connected between the VC0M op amp 13 and the output node N14 and the ground node. Between the sub 15 and the output Ic = 运 ΐί The output of 3 is driven by the driver, the phase of the crystal display panel, Wei Ji (here the panel load C (LC) is not the load capacitance of the liquid crystal display panel), &lt; the internal structure of the VC0M voltage generating section 12 &gt; section 12 includes: step resistors 1G1H, 101L, selection sections 102H, 102L, and switching transistors SW1 to 泖 6. The ladder resistor 101H is connected to the reference voltage receiving reference voltage Ligang Π M reference voltage VSSH The orbital H-2 of 19 200532300 generates a plurality of supply voltages with different voltage values. The selection section 102H selects one of the plural numbers of two produced by the step resistor 1010H in response to the control signal Sa from time 11. ^ ... The step resistor 101L is connected to the table N101L-1 that receives the reference voltage VSSL and the reference node L_2 that receives the reference voltage L1 = the supply voltage with different complex values. The selection department responds from time ^ 11 of The control signal ^ Sb selects one of the complex numbers ^ = generated by the step resistor. The switching transistors SW1 to SW4 are connected in series to the selection section 丨 〇2 {{and the selection section} n. By the selection surface The selected supply voltage should be switched to the switching transistor SW. The supply voltage selected by the selection department = the voltage VC0ML is supplied to the switching transistor SW2. The switching transistor is connected &amp; the selection unit 102H and the switching transistor Between SW3, the control strip 5 tiger S1 from the time control is received at the pole. The switching transistor SW3 is connected between the switching transistor SW1 and the switching crystal SW4, and the control signal from the time control unit u is received at the gate. Said body SW4 Connected between the switching transistor SW3 and the switching transistor, the gate receives a control signal S4 from the time control unit U.

=關電晶體SW4與選擇部職之間,在閘極接收來: 部Π之控制信號S2。 町]佐市J 開關電晶體SW5連接到開關電晶體SW1與開關 ,節點Μ以及規定電壓供給節點_之間 =控制部11之控制信號S5。規定電壓供給節點刪 ί關21 ΐ置)之規定電壓徹H °開關電 ii開關ί ί體SW2之互連節點NL以及規定電壓供 ,,口即點N103L之間’亚在其閘極接收來自時間控 a莫ί控為“高位準”時’開關電晶體謝至例6 為導通,並且备控制#號S1至S6為“低位準”時,開關電晶體 200532300 SW1至SW6斷開。 於此,各個參考電壓之電壓值滿足: (參考電壓VREFL) $ (參考電壓VSSH、VSSL) S (參考電 壓 VREFH)。 此外,規定電壓VSETH、VSETL之電壓值也滿足: (參考電壓VSSH)^(規定電壓VSETH)$(參考電壓VREFH); (參考電壓VREFL)S(規定電壓VSETL)$(參考電壓VSSL)。 〈階梯電阻101H及選擇部102H之構成例〉 圖2(A)表示階梯電阻101H及選擇部102H之構成例。階梯電 阻101H包括N (N為自然數)個電阻RlllH-1至R111H-N。電阻 • R111H—1至RlllH-N串聯連接到參考節點N101H-1與參考節點 N101H-2之間。在階梯電阻ιοίΗ之N個分接頭TAPH-1至TAPH-N 分別產生N個供給電壓VdivHl至VdivHN。選擇部102H包括N個 選擇電晶體ΤΙ 12H-1至ΤΙ 12H-N。選擇電晶體ΤΙ 12H-1至ΤΙ 12H-N 連接到分接頭TAPH-1至TAPH-N與開關電晶體SW1之間。並且, 時間控制部11向選擇電晶體T112H-1至T112H-N之其中之一之閘 極供應控制信號Sa。控制信號Sa之電壓值表示“(參考電壓 VREFH)-(參考電壓VSSH) ”。經由使選擇電晶體T112IH至 ΤΙ 12H-N之其中一個電晶體導通,將N個供給電壓VdivHl至VdiνΗΝ 之其中一個,作為驅動電壓VC0MH供應到開關電晶體SW1。經由 此,產生隶大值為參考電壓VREFH之具有N個不同位準之驅動電 壓 VCCMH。 〈階梯電阻101L及選擇部l〇2L之構成例〉 • 圖2(β)表示階梯電阻101L及選擇部102L之構成例。階梯電 阻 101L 包括Ν個電阻RlllL-1 至R111L-Ν。電阻R111L-1 至R111L-N - 串聯連接到參考節點N101L-1與參考節點N101L-2之間。在階梯 電阻101L之Ν個分接頭TAPL-1至TAPL-N分別產生Ν個供給電壓 VdivLl至VdivLN。選擇部102L包括Ν個選擇電晶體T112L-1至 T112L-N。選擇電晶體T112L-1至T112L-N連接到分接頭ttaPL-1 21 200532300 至TAPL-N與開關電晶體SW2之間。時間控制部n向選擇電晶體 T112L-1。至T112L-N之其中之一閘極供應控制信號Sb。控制信號 之電壓值表示“(參考電壓VSSL)-(參考電壓VREFL),,。經 由使選擇電晶體T112L-1至T112L-N中之其中之一為導通,將N 個供給電壓VdivLl至VdivLN中之其中一個電壓作為驅動電壓 VC0ML供應到開關電晶體SW2。經由此,產生最低位準為參考電壓 VREFL之具有N個不同位準之驅動電壓vc〇ML。 〈電阻值〉 、通常在驅動電壓產生裝置中,階梯電阻具有較高之電阻值, 以便減少流過階梯電阻之電流。例如,階梯電阻101H之電阻值大 Φ約為幾百ΚΩ至約幾ΜΩ (兆歐)。另-方面,開關電晶體SW5之 導通電阻可以顯著地小於階梯電阻1〇比之電阻值。例如,開關電 晶體SW5之導通電阻大約為50Ω。另外,與開關電晶體SW5相同 的,開關電晶體SW6之導通電阻顯著地小於階梯電阻1〇1H之電阻 值。 &lt; VC0M電壓產生部12之動作〉 其次,參照圖3、圖4,說明圖1所示之VC0M電壓產生部12 之,作。並且,於此,參考電壓VREFH之電壓值為“+5V”,參考 電壓VSSH、VSSL之電壓值為“〇v”,參考電壓VREFL之電壓值為 參 〜5V”。此外,規定電壓VSETH之電壓值為“+4V”,規定電壓 、^L之電壓值為“一4Γ。另外,選擇部刪接收控制信號如 ^擇具有“+5V”電壓值之供給電壓,並且選擇部狐接收控制 ^號Sb選擇具有“-5V”電壓值之供給電壓。換言之,將且有 , “+f ”之電壓值之驅動電壓VC0MH供應到節點N1〇2H,並且^具 有“-5V”之電壓值之驅動電壓VC0ML供應到節點姒吼。 八 - “在時間t0—1:1中,時間控制部11使控制信號S1、S3、S6為 低位準’’,並且使控制信號S2、S4、S5為“高位準”。由於 關電晶體SW2、SW4為導通,所以將驅動電壓vc〇ML (―5V)經由 點N102L與NL從選擇部i〇2L供應到節點NC。因此,節點ni〇2L、 200532300 NL與NC之電位均為“—5V” (圖4(B)與圖4(C))。另一方面,由 於開關電晶體SW5為導通,所以將規定電壓VSETH從規定電壓供 給節點N103H供應到節點NH。因此,節點仙之電位為“+4V”(圖 4(A))。並且’由於將驅動電壓vc〇MH從選擇部1〇2H供應到節點 N102H,所以節點N102H之電位為“+5V”。 在時間ti,時間控制部n使控制信號S3為“高位準,,,並 ,控制佗號S4為‘低位準”。由於開關電晶體別5導通,開關電 晶,SW3也為導通,所以經由節點NH,節點NC連接到規定電壓供 給節點N103H。因此,節點NC之電位從“一5V”變為“+4V” (圖 4(B))並且,郎點nh之電位也發生改變。但是,由於從規定電 壓供給節點N103H供應到節點NH之規定電壓VSETH之阻抗低於從 選擇部102L供應到節點NC之驅動電壓vc〇ML之阻抗,所以節點 電位變化小於節點【之電位變化。換言之,節點NH之電位 1定在規定電壓VSETH之電壓值(+4V)(圖4(A))。另外,由於開 關‘電晶體SW1為斷開狀態,所以節點N腿之電位也 °另一方面,開關電晶體SW2為導通並斷開開關^晶體 ^W4,所以驅動電壓vc〇ML (―5V)經由節點N1〇lL從選擇部1〇乩 仏應到節點NL。因此,節點N102L與虬之電位均穩定在“―5V”。 在時間t2,時間控制部n使控制信號S1、S6為“高位 , 佶^i^S2、S5為“低位準”。由於開關電晶體SW3導通並 、*二』ί晶體SW1導通,所以經由節點N1·、NH,選擇部聰 22)與圖4⑻)。紳由於從選擇部_共應H : μ勒WH壓VC〇匪之阻抗鬲於從規定電壓供給節點N103H供應到 作日之气定電M VSETH之阻抗,所以節點N1㈣之電位可ί改 值’喊點Ν1〇2Η之電位將不會低於規定電壓VSETH之電壓 没jjp。另一方面,由於開關電晶體SW6為導通,所以規定雷 Ϊ變'Ϊ郎點刚3L連接到節點NL。因此,節點NL之電位從“-5V, ’、、'省(圖4(C))。並且,由於開關電晶體測為斷開, 23 200532300 所以節點N102L之電位穩定在“_5V”。 ’時間控制部11使控制信號S3為“低位準,,,並 門“高位準’’。由於使開關電晶體娜導通並使 =t ^ rf ’所以㈣節點NH,節點NC連接到規定電壓 點N103L。因此,節點NC之電位從“+5V,,變為“_4v,,(圖 ())。並且,節點NL之電位也發生改變。但是,由於從規定電 ,到節點见之規定電壓職之阻抗低於從 、應到點NC之驅動電麼VC0MH之阻抗,所以節點 穩—/招立於節點NC之電位變化。換言之,節點NL之電位 知疋在規疋電壓VSETL之電壓值(-4V)(圖4(〇)。另一方面,由 SW1 ί導通並且斷開開關電晶體SW3,所以鷄電廢 0MI|J:+5V)經由節點·1H,從選擇部1〇2H供應到節點腿。因 此,卽點N102H、NH之電位均穩定為“+5V”。 、在時間t4,時間控制部11使控制信號si、S6為“低位準,,-, 為“高位準”。由於使開關電晶體SW4導通 並使開^電晶體SW2導通,所以選擇部·經由節點N1肌、见, 連接到節點NC。因此,節點nl與NC之電位均從“一4Γ變為 二ίν_ί&gt;Γ4⑻與圖4(c))。此時,由於從選擇部i〇2L供應i 即,.沾N102L之驅動電壓VC0ML之阻抗高於從規定電壓供哈節點 _3L供應到節點NL之規定電壓霞TL之阻抗,所以節點 之電位可能會改變。但是’節點_L之電 匕電壓值(-奶。另-方面,由於開關電晶體SW5為=壓 所以規疋電壓供給節點N103H與節點NH相連。因此,節點NH之 電位從“+5V”改變為“碰”(圖4(A))。另外,由於開關電晶體 SW3為斷開,所以節點ni〇2H之電位穩定在“+5V”。 在時間t5,執行與在時間ti相同之動作。 如上所述,由於當開關電晶體SW3從斷開切換為導通時, 低阻抗之,定電壓VSETH從規定電壓供給節點N1〇3H供應到節點 NH,所以節點NH之電位能穩定在規定電壓VSETH之電壓值。並且, 24 200532300 由於當開關電晶體SW4從斷開切換為_時 壓飄從規定電壓供給節點醜供應到節點几電= Between the switch transistor SW4 and the selected ministry, the control signal S2 of the ministry is received at the gate. ]] Saichi J. The switching transistor SW5 is connected between the switching transistor SW1 and the switch, between the node M and a predetermined voltage supply node _ = the control signal S5 of the control unit 11. The specified voltage supply node is removed (the gate is set at 21), the specified voltage is set to H °, the switch is turned on and off, and the interconnected node NL of the body SW2 is connected to the specified voltage, and the point between the points N103L is received at its gate. When the time control mode is “high level”, the switching transistor Xie is turned on, and when the spare control ## S1 to S6 are “low level”, the switching transistors 200532300 SW1 to SW6 are turned off. Here, the voltage value of each reference voltage satisfies: (reference voltage VREFL) $ (reference voltage VSSH, VSSL) S (reference voltage VREFH). In addition, the voltage values of the specified voltages VSETH and VSETL also satisfy: (reference voltage VSSH) ^ (specified voltage VSETH) $ (reference voltage VREFH); (reference voltage VREFL) S (specified voltage VSETL) $ (reference voltage VSSL). <Configuration Example of Step Resistor 101H and Selector 102H> FIG. 2 (A) shows a configuration example of the step resistor 101H and the selector 102H. The ladder resistor 101H includes N (N is a natural number) resistors R111H-1 to R111H-N. Resistance • R111H-1 to RllH-N are connected in series between reference node N101H-1 and reference node N101H-2. The N taps TAPH-1 to TAPH-N of the step resistor ι generate N supply voltages VdivH1 to VdivHN, respectively. The selection section 102H includes N selection transistors TI 12H-1 to TI 12H-N. The selection transistors TI 12H-1 to TI 12H-N are connected between the taps TAPH-1 to TAPH-N and the switching transistor SW1. Further, the time control section 11 supplies a control signal Sa to a gate of one of the selection transistors T112H-1 to T112H-N. The voltage value of the control signal Sa indicates “(reference voltage VREFH)-(reference voltage VSSH)”. By turning on one of the selection transistors T112IH to TI 12H-N, one of the N supply voltages VdivH1 to VdiνΗN is supplied to the switching transistor SW1 as the driving voltage VC0MH. As a result, a driving voltage VCCMH having N different levels with a large reference value VREFH is generated. <Configuration Example of Step Resistor 101L and Selector 102L> • FIG. 2 (β) shows a configuration example of the step resistor 101L and the selector 102L. The ladder resistor 101L includes N resistors R111L-1 to R111L-N. The resistors R111L-1 to R111L-N-are connected in series between the reference node N101L-1 and the reference node N101L-2. The N taps TAPL-1 to TAPL-N of the step resistor 101L generate N supply voltages VdivL1 to VdivLN, respectively. The selection section 102L includes N selection transistors T112L-1 to T112L-N. Select transistors T112L-1 to T112L-N are connected to the tap ttaPL-1 21 200532300 to TAPL-N and the switching transistor SW2. The time control unit n selects the transistor T112L-1. One of the gates to T112L-N supplies the control signal Sb. The voltage value of the control signal indicates "(reference voltage VSSL)-(reference voltage VREFL). By turning on one of the selection transistors T112L-1 to T112L-N, the N supply voltages VdivL1 to VdivLN are turned on. One of the voltages is supplied to the switching transistor SW2 as the driving voltage VC0ML. Through this, the driving voltage vc0ML having N different levels with the lowest level being the reference voltage VREFL is generated. <Resistance value> is usually generated at the driving voltage In the device, the step resistor has a higher resistance value in order to reduce the current flowing through the step resistor. For example, the resistance value of the step resistor 101H is large from about several hundred KΩ to about several MΩ (Megohm). In addition, the switch The on-resistance of the transistor SW5 can be significantly smaller than the resistance value of the step resistance by a ratio of 10. For example, the on-resistance of the switching transistor SW5 is about 50Ω. In addition, the on-resistance of the switching transistor SW6 is significantly the same as that of the switching transistor SW5 The ground value is less than the resistance value of the step resistance 101H. &Lt; The operation of the VC0M voltage generating section 12> Next, the VC0M voltage generating section 12 shown in FIG. 1 will be described with reference to FIGS. 3 and 4. Further, thereto, a voltage value of the reference voltage VREFH "+ 5V", the reference voltage VSSH, VSSL the voltage value is "〇v", the reference value of the reference voltage VREFL ~5V ". In addition, the voltage value of the predetermined voltage VSETH is “+ 4V”, and the voltage value of the predetermined voltage and ^ L is “−4Γ. In addition, the selection unit deletes the receiving control signal such as ^ selects a supply voltage having a voltage value of“ + 5V ”, and The selection control unit receives a control voltage Sb to select a supply voltage having a voltage value of "-5V". In other words, a driving voltage VC0MH having a voltage value of "+ f" is supplied to the node N102H, and ^ has "-5V The driving voltage VC0ML of the voltage value is supplied to the node howl. Eight-"At time t0-1: 1, the time control section 11 sets the control signals S1, S3, and S6 to a low level", and sets the control signals S2 and S2. S4 and S5 are "high level". Since the power-off crystals SW2 and SW4 are on, the driving voltage vcoML (−5V) is supplied from the selection unit i02L to the node NC via the points N102L and NL. Therefore, the potentials of the nodes ni02L, 200532300 NL, and NC are all "-5V" (Fig. 4 (B) and Fig. 4 (C)). On the other hand, since the switching transistor SW5 is on, the predetermined voltage VSETH is supplied from the predetermined voltage to the node N103H to the node NH. Therefore, the potential of the node cent is "+ 4V" (Fig. 4 (A)). Further, since the driving voltage vcoMH is supplied from the selection section 102H to the node N102H, the potential of the node N102H is "+ 5V". At time ti, the time control unit n sets the control signal S3 to "high level," and the control signal S4 to "low level". Since the switching transistor 5 is turned on, and the switching transistor and SW3 are also turned on, the node NC and the node NC are connected to a predetermined voltage and supplied to the node N103H via the node NH. Therefore, the potential of the node NC is changed from "-5V" to "+ 4V" (Fig. 4 (B)) and the potential of the Lang point nh is also changed. However, since the impedance of the predetermined voltage VSETH supplied from the predetermined voltage supply node N103H to the node NH is lower than the impedance of the driving voltage vcoML supplied from the selection section 102L to the node NC, the change in the node potential is smaller than that in the node [. In other words, the potential 1 of the node NH is set to the voltage value (+ 4V) of the predetermined voltage VSETH (Fig. 4 (A)). In addition, since the switch transistor SW1 is in an off state, the potential of the node N leg is also on the other hand. On the other hand, the switch transistor SW2 is turned on and off the switch ^ crystal ^ W4, so the driving voltage vc〇ML (−5V) The selection unit 100 should reach the node NL via the node N101L. Therefore, the potentials of nodes N102L and 虬 are both stable at "-5V". At time t2, the time control unit n sets the control signals S1 and S6 to “high level,” ii ^ S2, S5 to “low level”. Since the switching transistor SW3 is turned on and * 2, the crystal SW1 is turned on, so via the node N1 ·, NH, Selection Department Satoshi 22) and Figure 4⑻). Because of the impedance from the Selection Department_Total H: μL WH Voltage VC0 Bandwidth The resistance is fixed from the specified voltage supply node N103H to the day of the fixed electricity M VSETH impedance, so the potential of the node N1 改 can be changed to 'the potential of the shout point N1〇2 不会 will not be lower than the voltage of the specified voltage VSETH without jjp. On the other hand, since the switching transistor SW6 is on, the thunder is specified Ϊ Transformer 'Langlang point just 3L is connected to the node NL. Therefore, the potential of the node NL from "-5V,' ,, 'province (Figure 4 (C)). And, because the switching transistor is measured to be off, the potential of node N102L is stable at "_5V". The 'time control unit 11 sets the control signal S3 to the "low level, and the gate" high level "'. Since the switching transistor Na is turned on and = t ^ rf ′, the node NH and the node NC are connected to a predetermined voltage point N103L. Therefore, the potential of the node NC changes from "+ 5V," to "_4v," (Figure ()). In addition, the potential of the node NL also changes. However, because the impedance of the specified voltage from the specified voltage to the node is lower than the impedance of the drive voltage VC0MH from, to the point NC, the node is stable— / the potential change at the node NC is initiated. In other words, the potential of the node NL is known as the voltage value of the set voltage VSETL (-4V) (Fig. 4 (〇). On the other hand, the switch transistor SW3 is turned on and off by SW1, so the chicken power wastes 0MI | J : + 5V) is supplied from the selection unit 102H to the node leg via the node · 1H. Therefore, the potentials of the N102H and NH points at the puppet point are both stabilized at "+ 5V". At time t4, the time control unit 11 sets the control signals si and S6 to "low level,-," to "high level". Since the switching transistor SW4 is turned on and the switching transistor SW2 is turned on, the selection unit via The node N1 is connected to the node NC. Therefore, the potentials of the nodes nl and NC are both changed from "one 4Γ to two ίν_ί &gt; Γ4⑻ and Fig. 4 (c)). At this time, since the impedance i is supplied from the selection unit i02L, that is, the impedance of the driving voltage VC0ML of the N102L is higher than the impedance of the predetermined voltage Xia TL supplied from the specified voltage for the node _3L to the node NL, the potential of the node may Will change. However, the voltage value of the electric voltage of the node_L (-milk. On the other hand, since the switching transistor SW5 is = voltage, the regulated voltage supply node N103H is connected to the node NH. Therefore, the potential of the node NH changes from "+ 5V" It is "touch" (Fig. 4 (A)). In addition, since the switching transistor SW3 is turned off, the potential of the node ni0H is stabilized at "+ 5V". At time t5, the same operation as at time ti is performed. As described above, when the switching transistor SW3 is switched from off to on, the low-impedance voltage VSETH is supplied from the predetermined voltage supply node N103H to the node NH, so the potential of the node NH can be stabilized at the predetermined voltage VSETH. The voltage value. And, 24 200532300 Because when the switching transistor SW4 is switched from off to _, the voltage drifts from the specified voltage supply node to the node and supplies a few electricity.

之電位能穩定在規定電壓VSETL之電壓值。 所乂即J NL 進一步的,規定電壓VSETH滿足: (參考電壓VSSH) ^ (規定頓VSETH) ^ ( 所以也能夠使選擇部咖所含之選擇電 差小於“(參考電壓刪〇 -(參考電壓Hf)體之叫之電位 同樣的,由於規定電壓VSETL滿足: (參考電壓V,L)$(蚊賴VSETL)g(參 ^以能夠使選擇部胤所含之選擇電晶體之兩端 ^ 小於(參考電壓VREFH)-(參考電壓vrefl),,。 〈電晶體之耐壓〉 % 在前述動作中,節點NH與節點NC之電位差,以 與節點NC ^最大電位差大約為9V。另外,節點_h與節點腿 之電位差、節點N102L與節點NL之電位差、規壓供认節 及規定電壓供給節點瞧 NL之最大電位差大約為IV。因此’能夠使開關 SW5、SW6之耐壓低於開關電晶體SW3、測之 ^ SW2 電晶體SW1、SW2、SW5、SW6之絕對最大額定值)。^多勺降低開關 由於節點NH之電位能穩定在“+5Γ,所以選擇部聰 之(選參擇考電4體:===== 可。換§之,能夠降低選擇部102Η之選擇電晶體之耐壓。 同樣地,由於能夠使節點NL之電位穩定在‘‘—5V”, 選擇部1G2L所含之選擇電晶體之絕對最大額定值叙須高於 。((參考電壓VREFH)-(參考電壓丽L)),只要高於5V (控制信 號Sb之電壓值)即可。換言之,能夠降低選擇部1〇乩之 ; 晶體之耐壓。 〈效果〉 25 200532300 太杏12所示之現有麟雜產生裝置她下,在 麵壓產生裝置1中,能夠使選擇部1G2I^選i ΐ路規模。t ^體為低_電晶體°經由此’能夠縮ί 、進而,由使選擇部聰(選擇部102L)中所含之選 動電壓聰H (轉電壓麵L)之電位達到穩定為 (第2實施形態) 〈整體結構〉 心士f 5ΐίί發明之第2實施形態之驅動電壓產生裝置2之整 體、U冓。裝置2包括:圖!所示之時間控制部u、輸出端子15 及開關電晶體SW1爿SW6,蘭電壓產生部22,VC0MH用運瞀放 大,·L _放大器23L,以及平_ = 放 VC0M電麗產生部22產生對應時間控制部u所輸出之控制作 號Sa、Sb之驅動電壓VC0MH、VC0ML。 &quot; VC0MH用運算放大器23H將由VC0M電壓產生部22所產生之 驅動電壓VC0MH輸出到開關電晶體SW卜vc〇ML用運算放大器23l ΐί Ξ?1電壓產生部22所產生之驅動電壓vcoml ^出到^關電 晶體SW2。The potential can be stabilized at the voltage value of the specified voltage VSETL. That is, J NL further, the specified voltage VSETH satisfies: (reference voltage VSSH) ^ (specification VSETH) ^ (so it can also make the selection difference included in the selection department less than "(reference voltage delete 0-(reference voltage Hf) The potential of the body is the same, because the specified voltage VSETL satisfies: (reference voltage V, L) $ (mosquito ly VSETL) g (refer to ^ to enable both ends of the selection transistor included in the selection unit ^) to be less than (Reference voltage VREFH)-(Reference voltage vrefl) ,. <Withstand voltage of the transistor>% In the aforementioned action, the potential difference between the node NH and the node NC is about 9V. The maximum potential difference between the node NC and the node NC is about 9V. In addition, the node_ The potential difference between h and the node leg, the potential difference between node N102L and node NL, the maximum voltage difference between the voltage confession section and the specified voltage supply node. NL is about IV. Therefore, 'the voltage resistance of switches SW5 and SW6 can be lower than that of switching transistor SW3. ^ Measured ^ SW2 absolute maximum ratings of transistors SW1, SW2, SW5, SW6). ^ Multi-spoon reduction switch Since the potential of the node NH can be stabilized at "+ 5Γ", so choose the Ministry of Congzhi (selection Body 4: ===== Yes. In other words, it can reduce The withstand voltage of the selection transistor of the selection unit 102Η is similar. Since the potential of the node NL can be stabilized at "-5V", the absolute maximum rating of the selection transistor included in the selection unit 1G2L must be higher than that. (( The reference voltage VREFH)-(reference voltage L)) is only required to be higher than 5V (the voltage value of the control signal Sb). In other words, it is possible to reduce the voltage of the selection section 10 °; the withstand voltage of the crystal. <Effect> 25 200532300 too Under the existing linoleum generating device shown in FIG. 12, in the face pressure generating device 1, the selection unit 1G2I ^ can be selected to be the size of the circuit. The body is low_transistor. Through this, it can be reduced and further In order to stabilize the potential of the selection voltage Satoshi H (transition voltage surface L) contained in the selection section Satoshi (selection section 102L) to (second embodiment) <overall structure> the second embodiment of the inventor f 5ΐίί invention The overall form of the driving voltage generating device 2, U 冓. The device 2 includes: the time control unit u, the output terminal 15 and the switching transistor SW1 爿 SW6 shown in the figure! The blue voltage generating unit 22, VC0MH is amplified by the operation. · L _ amplifier 23L, and flat _ = VC0M power generation unit 22 The driving voltages VC0MH and VC0ML output by the control signals Sa and Sb output by the corresponding time control unit u are output from the VC0MH operational amplifier 23H to the switching voltage SW vc by the operational amplifier 23H. The operational amplifier 23l for the ML is driven by the driving voltage vcoml generated by the voltage generating unit 22 to the switching transistor SW2.

為了平滑VC0MH用運异放大器23H之輸出變動,設置平滑電 容C24H’並使其連接到VC0MH用運算放大器23H與開關電晶體謝 ^間之節點N24H以及接地節點之間。為了平滑vc〇ML用運算放大 器23L之輸出變動,設置平滑電容C24L,並且使其連接到vc〇ML 用運算放大器23L與開關電晶體SW2之間之節點N24L以及接地節 點之間。 開關電晶體SW1至SW4串聯連接到節點N24H盥節點N24L之 間。.開關電晶體SW1至SW6之連接關係如圖1所示 26 200532300 μ點=出端子15連接到開關電晶體SW3與開關電晶體SW4之互連 &lt; VC0M電壓產生部22之内部結構〉 圖5所示之VC0M電壓產生部22包括:圖丨所示之階梯電阻 101H、101L,以及選擇部i〇2H、i〇2L。階梯電阻loin與選擇部 102H之連接關係以及階梯電阻1〇1L與選擇部1〇2L之連接關係如 圖1所示。將由選擇部102H所選擇之供給電壓作為驅動電壓vc〇mh 供應到VC0MH用運算放大器23H。將由選擇部i〇2L所選擇之供給 電壓作為驅動電壓VC0ML供應到VC0ML用運算放大器23L。 〈動作〉In order to smooth the output variation of the op amp 23H for VC0MH, a smoothing capacitor C24H 'is provided and connected between the node N24H and the ground node between the VC0MH operational amplifier 23H and the switching transistor. In order to smooth the output variation of the vcOM operational amplifier 23L, a smoothing capacitor C24L is provided and connected to the node N24L and the ground node between the vcOM operational amplifier 23L and the switching transistor SW2. The switching transistors SW1 to SW4 are connected in series between the node N24H and the node N24L. The connection relationship of the switching transistors SW1 to SW6 is shown in Figure 1. 26 200532300 μpoint = output terminal 15 is connected to the interconnection of the switching transistor SW3 and the switching transistor SW4 &lt; Internal structure of the VC0M voltage generating section 22> FIG. 5 The VC0M voltage generating section 22 shown includes: the step resistors 101H and 101L shown in FIG. 丨, and the selection sections io2H and io2L. The connection relationship between the ladder resistor loin and the selection section 102H and the connection relationship between the step resistor 101L and the selection section 102L are shown in Fig. 1. The supply voltage selected by the selection section 102H is supplied as the driving voltage vcomh to the operational amplifier 23H for VC0MH. The supply voltage selected by the selection unit 102L is supplied to the operational amplifier 23L for VC0ML as the driving voltage VC0ML. <action>

以下說明圖5所示之驅動電壓產生裝置2之動作。 首先,與第1實施形態同樣的,時間控制部η輸出控制信穿 Sa、Sb 〇 ° 〜 其-人,與在苐1貫施形態相同,在VC〇M電壓產生部22,因 應來自時間控制部11之控制信號Sa,選擇部1〇2H選擇由階梯電 阻101H所產生之複數供給電壓中之其中一個。將選擇部1〇2H所 選擇之供給電壓,輸出作為驅動電壓VC0MH。並且,與在第1實施 形態一樣,,選擇部102L因應來自時間控制部u之控制信號&amp;, 選擇由階梯電阻101L所產生之複數供給電壓中之其中之一。將由 選擇部102L所選擇之供給電壓輸出作為驅動電壓vcqml。 其次,VC0MH用運算放大器23H將選擇部102H所供應之驅動 電壓VC0MH輸出到開關電晶體SW1。另外,vc〇ML用運算放大器2乩 將選擇部102L所供應之驅動電壓VC0ML輸出到開關電晶體^。 其次,開關電晶體SW1至SW6執行與第i實施形態相同之動 作。經由此,從VC0MH用運算放大器23H輸出到開關電晶體淝 之驅動電壓VC0MH以及從VC0ML用運算放大器23L輸出到開關電 晶體SW2之驅動電壓VC0ML輪流供應到輸出端子15。 〈效果〉 如上所述’由於能夠使節點N24H之電位穩定在“+5V”,所 27 200532300 以能夠以低耐壓電晶體構成VC0MH用運算放大器23H。另外,由於 能夠使節點N24L之電位穩定在“—5V” ,所以能夠以低耐壓電晶 體構成VC0ML用運算放大器23L。因此,能夠縮減電路規模。此外, 可以提高VC0MH用運算放大器23H、VC0ML用運算放大器23L之驅 動能力(反應速度)。 (第3實施形態) 〈整體結構〉 圖6表示本發明之第3實施形態之驅動電壓產生裝置3之整 體結構。裝置3具備時間控制部31與vc〇M電壓產生部32,取代 圖1所不之時間控制部11與vc〇M電壓產生部12。除此之豆 φ 他結構與圖1相同。 ’、The operation of the driving voltage generating device 2 shown in FIG. 5 will be described below. First, as in the first embodiment, the time control unit η outputs the control signals Sa, Sb 〇 ° ~ Its -person, the same as in the first embodiment, the VCM voltage generation unit 22 responds to time control. In the control signal Sa of the section 11, the selection section 102H selects one of the plural supply voltages generated by the step resistor 101H. The supply voltage selected by the selection section 102H is output as the driving voltage VC0MH. Further, as in the first embodiment, the selection unit 102L selects one of the plural supply voltages generated by the step resistor 101L in response to the control signal &amp; from the time control unit u. The supply voltage output selected by the selection section 102L is used as the drive voltage vcqml. Next, the operational amplifier 23H for VC0MH outputs the driving voltage VC0MH supplied from the selection section 102H to the switching transistor SW1. In addition, the VCOM operational amplifier 2 乩 outputs the driving voltage VC0ML supplied by the selection section 102L to the switching transistor ^. Next, the switching transistors SW1 to SW6 perform the same operations as those in the i-th embodiment. As a result, the driving voltage VC0MH output from the operational amplifier 23H for VC0MH to the switching transistor 以及 and the driving voltage VC0ML output from the operational amplifier 23L for VC0ML to the switching transistor SW2 are alternately supplied to the output terminal 15. <Effect> As described above, since the potential of the node N24H can be stabilized at "+ 5V", the operation amplifier 23H for VC0MH can be constituted by a low-withstand voltage crystal. In addition, since the potential of the node N24L can be stabilized at "-5V", the operational amplifier 23L for VC0ML can be constituted by a low withstand piezoelectric crystal. Therefore, the circuit scale can be reduced. In addition, the driving ability (response speed) of the operational amplifier 23H for VC0MH and the operational amplifier 23L for VC0ML can be improved. (Third embodiment) <Overall structure> Fig. 6 shows the overall structure of a driving voltage generating device 3 according to a third embodiment of the present invention. The device 3 includes a time control section 31 and a vcOM voltage generating section 32, instead of the time control section 11 and the vcOM voltage generating section 12 shown in FIG. Other than that, the structure of φ φ is the same as that in FIG. 1. ’,

間控制部31使用控制信號Sa及振幅情報&amp;來控制由vc〇M 電壓產生部32所輸出之驅動電壓vc_、vc〇ML之電壓值。振幅 隋報Sc為具有對應vc〇M電壓產生部32戶斤產生之驅動電壓vc〇MH 之電位差之電舰之雜(振幅㈣刪〇。 S sr= 1因絲自外部之時間信號簡ng,輸出控制 及射 32目糾間㈣部31所輸$之㈣!1信號Sa 及振巾田if報Sc,產生驅動電壓vc_、vc〇M。^ ^ 生部32因應時間控制部31輸 ^ 壓產 籲電塵VC0MH或VC0ML。 哺出之控號S1至S6,輸出驅動 &lt; VC0M電壓產生部32之内部結構〉 102Η與開關電晶體SW1之間。淨°。電路並連接到選擇部 28 200532300 選擇用運算放大器302、供給用電晶體T3.〇3—j及電 構成電壓電流轉換電路。選擇用運算放大器3〇2,其輸 到供給用電晶體T303-1之閘極,其-方輸入端 = 晶體T303-1與電阻R3〇4之間之互連節點N3〇3,在另一 接收來自牯間控制部31之振幅情報Sc (振幅電壓。供a 用電晶體T303-1及電阻R304串聯連接到接收參考電塵聰^ 參考節點1與接收參考電壓VSS之參考節點麵—2 供給用電晶體T303-2、甜位電晶體T311-1與T311-2、以及 供給用電晶體T303-3,串聯連接到接收參考電壓之表々 點N301-3與接收參考電壓VREFL之參考節點]V301-4之間。供上 用電晶體T303-2連接到參考節點N301 -3與鉗位電晶I# πn = 間,其閘極連接到供給用電晶體之閘極。甜位電^ T311-1連接到供給用電晶體T303-2與鉗位電晶體T311-2之間, 並且其閘極連接到接收偏壓Vbiasl之偏壓供給節點N311—丨。钳位 電晶體T31卜2連接到鉗位電晶體T311—!與供給用電晶體Τ3〇3_3 之間,並且其閘極連接到接收偏壓Vbias2之偏壓供給節點 N311-2。供給用電晶體T303-3連接到鉗位電晶體T311—2與束考 節點Ν301-4之間,其閘極與其沒極相連。 、電阻R305、鉗位電晶體Τ311-3及供給用電晶體Τ303-4串聯 連接到位於供給用運算放大器3〇1與開關電晶體SW1之間之節點 N305H,以及接收參考電壓VREFL之參考節點N3〇1—5之間。電阻 R305連接到節點N305H與钳位電晶體T311-3之間。钳位電晶體 T311-3連接到電阻R3〇5與供給用電晶體T3〇3—4之間,其閘極連 接到接收偏壓Vbias3之偏壓供給節點Ν311—3。供給用電晶體 Τ303-4連接到鉗位電晶體T31丨―3與接收參考電壓VREFL之參考節 點N301-5之間,其閘極與供給用電晶體T3〇3—3之閘極相連。 尸^關電晶體SW1至SW4串聯連接到節點Ν305Η與節點N305L 之間。節點N305L為電阻R305與鉗位電晶體Τ311 -3之互連節點。 開關電晶體SW1至SW6之連接關係如圖丨所示。 29 200532300 之老制節點N3〇5H之電位高於參考節點2 管二女:〜q )所投之鉗位電路,並連接到位於供給用運 #放大态301與開關電晶體SW1之間之 電屢VSS之節點腫-2之間。 錢接收翏考 並^ ^此,參考電壓vss之電壓值與振幅s (振幅電壓VREFM)滿足: (參考電壓VREFL) $ (參考電壓vss) ^ (參考電壓VREFH); (參考電壓VSS)$ (振幅電壓(參考電壓VREFH)。 〈動作〉The inter-control unit 31 uses the control signal Sa and the amplitude information &amp; to control the voltage values of the drive voltages vc_ and vcOM that are output from the vcOM voltage generator 32. Amplitude report Sc is a miscellaneous electric ship with a potential difference corresponding to the driving voltage vc〇MH generated by 32 kg of vcom voltage generating unit (amplitude deleted. S sr = 1 due to the time signal of the wire from the outside, ng, The output control and firing of the 32 mesh correction unit 31 loses $ 1! 1 signal Sa and the vibration field if report Sc, and generates the driving voltages vc_, vcOM. ^ ^ The production unit 32 responds to the time control unit 31. Call for electric dust VC0MH or VC0ML. Feed out control numbers S1 to S6, output drive &lt; internal structure of VC0M voltage generating section 32> 102Η and switching transistor SW1. Net °. Circuit and connect to selection section 28 200532300 Select The operational amplifier 302, the supply transistor T3. 03-j, and electricity constitute a voltage-current conversion circuit. The selection of the operation amplifier 302 is input to the gate of the supply transistor T303-1, and the square input end thereof = Interconnect node N3〇3 between crystal T303-1 and resistor R304, and receive the amplitude information Sc (amplitude voltage) from the control unit 31 in the other. The transistor T303-1 and resistor R304 are connected in series. Connected to the reference node of the receiving reference Dust ^ reference node 1 and the receiving reference voltage VSS-2 The supply transistor T303-2, the sweet bit transistors T311-1 and T311-2, and the supply transistor T303-3 are connected in series to the reference node N301-3 receiving the reference voltage and the reference node receiving the reference voltage VREFL ] V301-4. The supply transistor T303-2 is connected to the reference node N301 -3 and the clamp transistor I # πn =, and its gate is connected to the gate of the supply transistor. Sweet bit ^ T311-1 is connected between the supply transistor T303-2 and the clamp transistor T311-2, and its gate is connected to the bias supply node N311- 丨 which receives the bias voltage Vbiasl. The clamp transistor T31b 2 is connected To the clamp transistor T311—! And the supply transistor T3〇3_3, and its gate is connected to the bias supply node N311-2 that receives the bias voltage Vbias2. The supply transistor T303-3 is connected to the clamp transistor Between the crystal T311-2 and the beam test node N301-4, its gate is connected to its non-pole. The resistor R305, the clamp transistor T311-3 and the supply transistor T303-4 are connected in series to the supply operational amplifier 3 〇1 node N305H between switching transistor SW1 and reference node N3 0-5 that receives reference voltage VREFL The resistor R305 is connected between the node N305H and the clamp transistor T311-3. The clamp transistor T311-3 is connected between the resistor R305 and the supply transistor T303-3-4, and its gate is connected to The bias supply node N311-3 receiving the bias voltage Vbias3. The supply transistor T303-4 is connected between the clamp transistor T31 丨 -3 and the reference node N301-5 receiving the reference voltage VREFL, and its gate is connected to the gate of the supply transistor T303-3. The transistors SW1 to SW4 are connected in series between the node N305 and the node N305L. The node N305L is an interconnection node between the resistor R305 and the clamp transistor T311-3. The connection relationship between the switching transistors SW1 to SW6 is shown in Figure 丨. 29 200532300 The potential of the old node N305H is higher than that of the reference node 2. The second tube: ~ q) The clamped circuit is connected to the power supply between the amplifier # 301 and the switching transistor SW1. Repeated VSS node swelling between -2. The money received and studied ^ ^ Here, the voltage value and amplitude s (amplitude voltage VREFM) of the reference voltage vss satisfy: (reference voltage VREFL) $ (reference voltage vss) ^ (reference voltage VREFH); (reference voltage VSS) $ ( Amplitude voltage (reference voltage VREFH).

其次,說明圖7所示之VC0M電塵產生部32之動作。並且, 參考,壓VREFH之電壓值為“+5v”,參考電壓VSSH、vss之電壓 值為0V ,參考電壓VREFL之電壓值為“-5V”。 ,選擇部102Η因應來自時間控制部31之控制信號义,選擇由 階,電阻101H所產生之複數供給電壓中之其中一個電壓。供給用 運算放大斋301將選擇部i〇2H所選擇之驅動電壓%〇]^輸出到開 關電晶體SW1。 另一方面,選擇用運算放大器3Q2接收來自時間控制部31 之振幅情報Sc。具有對應振幅情報&amp; (振幅電壓vrEFM)之電壓 值之電流值之供給電流IrefM流過供給用電晶體T303-1與電阻 R304。供給電流IrefM滿足下述(式1)。 ^ (供給電流IrefM)=(振幅電壓VREFM) / (電阻R304) (式1) 其次,供給用電晶體T303-2在其閘極接收在供給用電晶體 T303-1之閘極所產生之閘極電壓。因此,供給電流irefM流過供 給用電晶體T303-2、钳位電晶體T311-1與T311 -2、以及供給用 電晶體T303-3。 ° 其次’由於流過供給用電晶體T303-3之供給電流IrefM經由 供給用電晶體T303-3、T303-4所構成之電流鏡電路,流過供給用 電晶體Τ303-4。因此,在節點_5L產生驅動電壓VC0ML。該驅 30 200532300 動電壓VC0ML滿足下述(式2)。 ^壓聰Ο =(驅動電壓VCQMH)—(供給電流IrefM) x(電阻 R305) (式2) 默上^厂(式υ與(式2),在節點祕1所產生之驅動電 壓VC0ML之電壓值如下述(式3)。 (驅動電壓VGGML)=(驅動電壓VGGMH)-(振幅電壓VREFM) X (電阻 R305) / (電阻 R3〇4) (式 3)Next, the operation of the VCOMM dust generator 32 shown in FIG. 7 will be described. And, for reference, the voltage value of the voltage VREFH is "+ 5v", the voltage value of the reference voltages VSSH, vss is 0V, and the voltage value of the reference voltage VREFL is "-5V". In response to the control signal from the time control section 31, the selection section 102 selects one of the plural supply voltages generated by the step and the resistance 101H. The supply operational amplifier 301 outputs the driving voltage% 0] ^ selected by the selection unit 102a to the switching transistor SW1. On the other hand, the selection operational amplifier 3Q2 receives amplitude information Sc from the time control unit 31. A supply current IrefM having a current value corresponding to the voltage value of the amplitude information &amp; (amplitude voltage vrefFM) flows through the supply transistor T303-1 and the resistor R304. The supply current IrefM satisfies the following (Equation 1). ^ (Supply current IrefM) = (Amplitude voltage VREFM) / (Resistance R304) (Equation 1) Second, the supply transistor T303-2 receives the gate generated by the gate of the supply transistor T303-1 at its gate. Pole voltage. Therefore, the supply current irefM flows through the supply transistor T303-2, the clamp transistors T311-1 and T311-2, and the supply transistor T303-3. ° Secondly, because the supply current IrefM flowing through the supply transistor T303-3 passes through a current mirror circuit formed by the supply transistors T303-3 and T303-4, it flows through the supply transistor T303-4. Therefore, the driving voltage VC0ML is generated at the node_5L. The driver 30 200532300 dynamic voltage VC0ML satisfies the following (Equation 2). ^ Voltage 0 = (driving voltage VCQMH)-(supply current IrefM) x (resistance R305) (Equation 2) ^ Factory (Equation υ and (Equation 2), the voltage of the driving voltage VC0ML generated at node 1 The values are as follows (Expression 3). (Drive voltage VGGML) = (Drive voltage VGMMH)-(Amplitude voltage VREFM) X (Resistor R305) / (Resistor R304) (Expression 3)

^這般’將對應控制信號Sa之驅動電壓%從供給用運算 301供應到開關電晶體SW卜並且將對應控制信號知與振 幅情報Sc之驅動電壓VC0ML供應到開關電晶體抓2。 其次」開關電晶體SW1至SW6執行與在第i實施形態中相同 之動作。經由此’將從供給用運算放大n 3〇1輸出到節點腦5H ^驅動電壓TO)MH與在節點腦5L產生之驅動電壓VCqML輪流輸 出到VC0M用運算放大器13 (參照圖6)。 〈钳位電晶體之機能〉 經由汉置钳位電晶體T311-1,能夠調節供給用電晶體T3〇3-2 之^極電壓。換言之,能夠將供給用電晶體T3〇3-2之汲極電壓設 為(偏壓Vbiasl) + (電晶體T311-1之閘極-源極間電壓),,。 因此,能夠使供給用電晶體T303-2之汲極電壓之電壓值高於參考 電壓VREFL之電壓值。此外,由於能使供給用電晶體Bog—2之没 極電壓之、菱動小於現有技術中,所以能夠緩和汲極電壓依存性 來之影響。 於此’最好是,偏壓Vbiasl為“0V”,並且钳位電晶體 之閘極-極源電壓等於、或幾乎等於“振幅電壓vrefm”。如此一 來,由於能夠使供給用電晶體T303-2之汲極電壓等於供給用電晶 體T303-1之汲極電壓,因此能夠進一步緩和汲極電壓^性之^ 響。 ’、 此外,經由設置鉗位電晶體Τ311-2、Τ311-3,能夠調節供給 用電晶體Τ303-3、Τ31卜4之汲極電壓。換言之,供給用電^ 31 200532300 丁303-3之汲極電壓將不會高於“(偏壓VMas2)—(電晶體1311一2 之閘,-源極間電壓} ”,並且供給用電晶體τ·—4之汲極電壓 不會,高於“(偏壓Vbias3)-(電晶體Τ311-3之閘極—源極間電 壓)/。因此,能使供給用電晶體Τ3〇3-3、Τ3〇3—4之汲極電壓低 於參考電壓VREFH。此外,與供給用電晶體Τ3〇3_2同樣,能夠緩 和供給用電晶體Τ303-3、Τ303-4之汲極電壓依存性之影響。 於此,最好是鉗位電晶體Τ311—3之閘極-源極間電^等於、 或幾乎等於鉗位電晶體Τ311—2之閘極-源極間電壓,並且偏壓 Vbias2、偏壓Vbias3等於,或基本上等於“钳位電晶體Τ311-2 (Τ311 3)之閘極-源極間電壓。如此一來,能夠使得供給用電 φ晶體Τ3〇3-3、Τ3〇3-4之;;及極電壓不會高於“〇ν”。 〈效果〉 斤如上所述,由於經由開關SW1至開關SW6之適當動作,能夠 使節點N305L之電位穩定在“-5V” ,所以能夠使供給用電晶體 T303-4 ,兩端之電位差小於“(參考電壓VREFH)—(參考電壓 V^EFL)。另外,還能使每個供給用電晶體T303-2、T303-3兩 、之電位差小於“(參考電壓则EFH)-(參考電塵VREFL),,。 進而還能使鉗位電晶體T311-1至T311-3之各自兩端之電位差小 於“(參考電壓VREFH)-(參考電壓VREFL),,。經由此,與如 鲁圖13所示之現有驅動電壓產生裝置相較,能夠降低供給用電^體 T303-1至T303-4之耐壓,從而能夠縮減電路規模。 此外,經由使供給用電晶體T303-1至T303-4與鉗位電晶體 T311-1至T311-3低耐壓化,因此能夠降低各個電晶體之製程偏 差。因此能夠降低由供給用電晶體T303-1、T303-2所構成之電流 鏡電路之電流特性差異,以及由供給用電晶體Τ303-3、Τ303-4所 構成之電流鏡電路之電流特性差異。此外,能夠緩和供給用電晶 體Τ303-1至Τ303-4與鉗位電晶體Τ311-1至Τ311-3之汲極電壓 依存性之影響。經由此,能夠精確產生具有對應控制信號Sa與振 幅情報Sc之電壓值之驅動電壓VC0ML。 〃 32 200532300 並且,偏麗Vbiasl之電壓值可以是任意適當值,以便 與供給用電晶體T3G3~2在飽與區中動作;鉗位電 曰曰體T31H之閘極-源極間碰Vgs、沒極 = 間電㈣s中之每一個賴為钳位電晶體T3ii—k= V 下;以及供給用電晶體T303'2之閘極-源極間· 、沒極-源極電壓Vds與後閘極—源極間輕心之每一個 為供給用電晶體T303-2之絕對最大額定值以下。如此一來 =钳位電晶體T311-1及供給用電晶體則_2遭到偏麼·如 破壞。 =Vbias2之電麗值可以是任意適當值以便:鉗位電晶體 ™ 給用電晶體T3〇3_3在飽與區中動作;鉗位電晶體 Μΐ+ίνί極^極f ΐϊ細、沒極—源極電麼Vds與後閉極一源 ,間祕Vbs之母一個電壓為鉗位電晶體T3u_2之絕對最大 ^下,以及供給用電晶體T303_3之閘極_源極間電壓細、没極 與後_,源極間電壓Vbs之每—個電壓為供給用 電日日體T303-3之絕對最大額定值以下。 削=Lbif之龍值可以是任意適當值,以便:鉗位電晶體 電晶體T303-4在飽與區中動作;鉗位電晶體 朽p旧^極―^極間電壓VgS、没極—源極電壓Vds與後閘極—源 極間電堡Vbs之母-個電壓為钳位電晶體Τ311_3之絕對最大額定 值以下,以及供給用電晶體T303-4之閘極-源極間電壓Vgs、沒極^ This' supplies the driving voltage% corresponding to the control signal Sa from the supply calculation 301 to the switching transistor SWb and supplies the driving voltage VC0ML corresponding to the control signal and amplitude information Sc to the switching transistor 2. The "next" switching transistors SW1 to SW6 perform the same operations as in the i-th embodiment. As a result, the operational amplifier n 301 from the supply is output to the node brain 5H (the driving voltage TO) MH and the driving voltage VCqML generated at the node brain 5L are alternately output to the VCOM operation amplifier 13 (see FIG. 6). <Functions of Clamping Transistor> Via the clamp transistor T311-1, the voltage of the supply transistor T3 03-2 can be adjusted. In other words, the drain voltage of the supply transistor T303-3 can be set to (bias Vbiasl) + (gate-source voltage of the transistor T311-1). Therefore, the voltage value of the drain voltage of the supply transistor T303-2 can be made higher than the voltage value of the reference voltage VREFL. In addition, since the electrode voltage of the supply transistor Bog-2 can be made smaller than that in the prior art, the influence from the dependency of the drain voltage can be reduced. Here, it is preferable that the bias voltage Vbiasl is "0V" and the gate-to-source voltage of the clamping transistor is equal to or almost equal to the "amplitude voltage vrefm". In this way, since the drain voltage of the supply transistor T303-2 can be made equal to the drain voltage of the supply transistor T303-1, the influence of the drain voltage can be further alleviated. In addition, by setting the clamp transistors T311-2 and T311-3, the drain voltages of the supply transistors T303-3 and T31b 4 can be adjusted. In other words, the drain voltage of the power supply ^ 31 200532300 ding 303-3 will not be higher than "(bias VMas2)-(the gate of the transistor 1311-2, voltage between the sources}", and the power supply transistor The drain voltage of τ · -4 will not be higher than "(bias Vbias3)-(gate-source voltage of transistor T311-3) /. Therefore, the supply transistor T3〇3-3 The drain voltage of T3403--4 is lower than the reference voltage VREFH. In addition, similar to the supply transistor T303_2, the influence of the dependency of the drain voltage of the supply transistors T303-3 and T303-4 can be reduced. Here, it is preferable that the gate-source voltage of the clamp transistor T311-3 is equal to, or almost equal to the gate-source voltage of the clamp transistor T311-2, and the bias voltage is Vbias2 and the bias voltage. Vbias3 is equal to, or substantially equal to, the gate-source voltage of the clamp transistor T311-2 (T311 3). In this way, the power supply φ crystals T303-3, T3〇3-4 And; and the pole voltage will not be higher than "〇ν". <Effect> As described above, due to the proper operation of switch SW1 to switch SW6, the node N305L can be The bit is stable at "-5V", so the supply transistor T303-4 can make the potential difference between the two terminals less than "(reference voltage VREFH)-(reference voltage V ^ EFL). In addition, each supply transistor can also be made The potential difference between T303-2 and T303-3 is less than "(reference voltage is EFH)-(reference electric dust VREFL), and the potential difference between the two ends of the clamping transistors T311-1 to T311-3 can be made. Less than "(reference voltage VREFH)-(reference voltage VREFL). Through this, compared with the conventional driving voltage generating device shown in Fig. 13, it is possible to reduce the supply power T303-1 to T303-4. Withstand voltage, it is possible to reduce the circuit scale. In addition, the supply transistors T303-1 to T303-4 and clamp transistors T311-1 to T311-3 have a lower withstand voltage, so that the process deviation of each transistor can be reduced. Therefore, it is possible to reduce the difference in current characteristics of the current mirror circuit formed by the supply transistors T303-1 and T303-2, and the difference in the current characteristics of the current mirror circuit formed by the supply transistors T303-3 and T303-4. In addition, supply transistors T303-1 to T303-4 and clamp power can be alleviated The influence of the drain voltage dependency of the crystals T311-1 to T311-3. Through this, it is possible to accurately generate a driving voltage VCOML having a voltage value corresponding to the control signal Sa and the amplitude information Sc. 2005 32 200532300 And, the voltage of the beautiful Vbiasl The value can be any appropriate value so as to act in the saturated region with the supply transistor T3G3 ~ 2; clamp the gate electrode T31H between the gate and source of Vgs, each pole = each of the voltages 间 s Lai is the clamp transistor T3ii—k = V; and each of the gate-to-source ·, non-source-to-source voltage Vds and the back gate-to-source between the supply transistor T303'2 It is below the absolute maximum rating of the supply transistor T303-2. In this way, the clamping transistor T311-1 and the supply transistor are biased. The voltage value of = Vbias2 can be any suitable value so that: the clamp transistor ™ feeding transistor T3 03_3 operates in the saturation region; the clamp transistor Μΐ + ίνί 极 ^ 极 f ΐϊ 细, 极 极 — 源The source voltage of Vds and the back-closed pole is one source. The voltage of the mother of Vbs is the absolute maximum of clamp transistor T3u_2, and the voltage between gate and source of supply transistor T303_3 is fine. _, Each of the source-to-source voltages Vbs is below the absolute maximum rating of the power supply solar panel T303-3. The value of L = Lbif can be any appropriate value so that: the clamp transistor T303-4 operates in the saturated region; the clamp transistor is old and the voltage between the electrodes VgS and the electrode-source The voltage of the electrode voltage Vds and the back gate-source voltage source Vbs-the voltage is below the absolute maximum rating of the clamp transistor T311_3, and the gate-source voltage Vgs of the supply transistor T303-4 Wu Ji

Vds與後閑極—源極間電壓Vbs之每一個電壓為供給用 電日日體T303-4之絕對最大額定值以下。 並且’當使用如圖8(A)所示之電晶體312_N或如圖8(B)所示 之電晶體312-P代替二極體312—D時,也能獲得同樣效果。 因應參考電壓VREFH與參考電壓VREFL之電壓值,能夠在供 2電晶體T3G3-2與供給用電晶體綱—3之間以及在電阻R3〇5 二=用電晶體T303-3之間增加钳位電晶體。如此一來 參 考電壓VREFH與參考電壓聰FL之間之電位差大,也能使供給用 33 200532300 電晶體與鉗位電晶體低耐壓化。 μ另外’儘管在本實施形態中,使用供給電流產生部(選擇用 運算放大器302、電阻R304與R305、供給用電晶體Τ3〇3-1至 Τ303-4、以及鉗位電晶體Τ311—丨至Τ311—3)取代階梯電阻1〇1L 及選擇部102L,但是也能夠使用此供給電流產生部取代階梯電阻 101H及選擇部ι〇2Η。在這種情況下,使用n通道電晶體取代p通 道電b曰體(供給用電晶體T303-1等),使用P通道電晶體代替n 通道電晶體(供給用電晶體T3〇3-3等)等即可。 (第4實施形態) 〈整體結構〉 一 本發明之第4實施形態之驅動電壓產生裝置4具備如圖9所 不之VC0M電壓產生部42,取代如圖6所示之VC0M電壓產生部32。 除此之1,其他結構與圖6相同。並且,於此,時間控制部31使 用控制信號Sb與振幅情報Sc來控制由vc〇M電壓產生部42 出之驅動電壓VC0MH、VC0ML之電壓值。 所輪 &lt; VC0M電壓產生部42之内部結構〉 、μ如圖9所示之VC0M電壓產生部42具備如圖7所示之供給用 運算放大器则、獅用運算放大器观、供給用 ^〇3-2、钳位電晶體Τ31η與Τ311_2、電阻謂5以及二= 312 D,取代如圖}所示之階梯電阻1〇1Η與選擇部ι〇2Η。其他蚌 構如圖1所示之VC0M電壓產生部12。 、&quot; 供給用運算放大器連接到選擇部職與開關電晶體別2 選擇用運算放大器302、供給用電晶體T3〇3—;l、T3〇3—2 阻甜位電晶體T3U—1與Τ311—2之連接方式如圖7 ί 不。供、,、口用電晶體Τ303-2、钳位電晶體與T3U_2、 =R3G5 ’串聯連接^參考節點__3與節點細%之間。節點 pm、查ΪΤ給用運算放大$ 301與開關電晶體SW2之間。電阻 5連接到钳位電晶體Τ3Π-2與節點N405L之間。 34 200532300 二極體312-D連接到供給用運算放大器綱 間之節點财叫與接收參考電壓脱之參考節 開關電晶體SW1至剔連接到鉗位電晶體T3 i】-2 之間之互連節點N405H與節點N405L·之間。 &quot;、 開關電晶體SW1至SW6之連接關係如圖1所示。 〈動作〉 其次,說明如圖9所示之VC0M電壓產生部42之叙於 選擇部102L因應'來自日寺間控制部31之古^作° 階梯電阻腿所產生之供給電壓中之其中— 由選擇部102L所選擇之驅動電壓則ml輪出°到開$ τ咖,一方f力’選擇用運算放大器302、供給用電晶體T303-!盘 ρΠ 電晶體T3U—卜T311—2執行與第3實施形_目 =之動^因此’在節點_5Η產生之驅動電壓vc_之 如下述(式4)所示。 既 $動電壓yam)=(鶴賴職L) + (振幅電壓 (電阻 R305) / (電阻 R304) (式 4) 如这般’將對應控制信號Sb與振幅情報Sc之驅動電壓VC0MH ,到開關,晶體SW1,並且將對應控制信號Sb之驅動電壓vc〇ML 攸供給用運算放大301供應到開關電晶體gw〗。 其次,開關電晶體SW1至SW6執行與在第1實施形態中相同 之動=。因,’在節點N4〇5H所產生之驅動電壓vc〇腿及從供給 ,運算放大斋301輸出到節點N4〇5L之驅動電壓VQ)ML輪流被輸 出到VC0M用運算放大器13 (參照圖6)。 〈效果〉 如上所述,由於經由使開關電晶體SW1到讓適當動作,節 點N405H之電位能穩定在“+5v” ,因此能夠使供給用電晶體 T303-2兩端之電位差小於“(參考電壓VREFH)—(參考電壓 35 200532300 VREFL) ”。因此,也能夠使钳位電晶體T311-1與T311-2之各自 兩端之電位差小於“(參考電壓VREFH)-(參考電壓VREFL),,。 經由此,與如圖13所示之現有驅動電壓產生裝置相較,能夠降低 供給用電晶體T303-1與T303-2之财壓,從而能夠縮減電路規模。 並且,由於能夠降低供給用電晶體T303-1之製程偏差,因此 降低供給用電晶體T303-1之電流特性之差異。並且,與供給用電 晶體T303-1同樣,能夠降低供給用電晶體T303-2之電流特性之 差異。經由此,能夠精確產生對應控制信號Sb及振幅情報Sc之 驅動電壓VC0MH、VC0ML。 並且,當使用如圖8(A)所示之電晶體312-N或如圖8(B)所示 Φ之電晶體312-P取代二極體312-D時,也能獲得相同效果。 (第5實施形態) 〈整體結構〉 圖10表示本發明之第5實施形態之驅動電壓產生裝置5之整 體結構。裝置5具備VC0M電壓產生部52與圖6所示之時間控制 部31,取代如圖5所示之時間控制部11及vc〇M電壓產生部22。 驅動電壓產生裝置5還包括如圖7所示之二極體312-D。其他結構 ,圖5相同。VC0M電壓產生部52因應來自時間控制部之^制 信號Sa與振幅情報Sc,產生驅動電壓VC0MH、VC0ML。二極體312-D 連接到位於VC0MH用運算放大器23H與開關電晶體SW1之間之節 點N512-1與接收參考電壓VSS之參考節點N512-2之間。 &lt; VC0M電壓產生部52〉 ,10所示之VC0M電壓產生部52具備圖7所示之選擇用運算 放大杰302、供給用電晶體T303-1至T303-4、電阻R304與R305、 以及鉗位電晶體T31M至Τ3Π-3,取代了如圖5所示之階梯電阻 101L與選擇部102L。其他結構與圖5相同。 選擇用運异放大器302、供給用電晶體T303-1至T303-4、電 阻R304與鉗位電晶體T311-1至T311-3之連接關係與圖7相同。 電阻R305、钳位電晶體T31丨-3與供給用電晶體T3〇3—4串聯連接 36 200532300 到位於VC0MH用運算放大器23H與開關電晶體SW1之間之節點 N505H以及參考節點N301-5之間。電阻R305與鉗位電晶體T31 之間之互連節點N305L連接到VC0ML用運算放大器23L。 〈動作〉 說明圖10所示之VC0M電壓產生部52之動作。 首先,與第2實施形態中相同,選擇部i〇2H選擇由階梯電阻 101L所產生之複數供給電壓中之其中一個電壓。其次,vc〇mh用 運算放大器23H將由選擇部1_所選擇之供給電壓輸出作為 電壓VC0MH。Each voltage between Vds and the post-source-to-source voltage Vbs is below the absolute maximum rating of the power supply sun-body T303-4. And when the transistor 312_N shown in FIG. 8 (A) or the transistor 312-P shown in FIG. 8 (B) is used instead of the diode 312-D, the same effect can be obtained. According to the voltage values of the reference voltage VREFH and the reference voltage VREFL, it is possible to increase the clamp between the supply transistor T3G3-2 and the supply transistor Gang-3 and between the resistor R3 05 and the transistor T303-3. Transistor. In this way, the large potential difference between the reference voltage VREFH and the reference voltage Satoshi FL can also reduce the withstand voltage of the supply 33 200532300 transistor and the clamp transistor. In addition, although in the present embodiment, a supply current generating section (selective operational amplifier 302, resistors R304 and R305, supply transistors T303-1 to T303-4, and clamp transistor T311 --- T311-3) replaces the step resistor 101L and the selection section 102L, but it is also possible to use this supply current generation section instead of the step resistor 101H and the selection section 102L. In this case, use n-channel transistors instead of p-channel transistors (supply transistor T303-1, etc.), and use p-channel transistors instead of n-channel transistors (supply transistor T30-03-3, etc.) ) Just wait. (Fourth Embodiment) <Overall Structure> A driving voltage generating device 4 according to a fourth embodiment of the present invention includes a VCOM voltage generating unit 42 as shown in Fig. 9 instead of the VCOM voltage generating unit 32 shown in Fig. 6. Except for this, other structures are the same as those in FIG. 6. In addition, here, the time control unit 31 uses the control signal Sb and the amplitude information Sc to control the voltage values of the driving voltages VC0MH and VC0ML output from the vcOM voltage generation unit 42. <The internal structure of the VC0M voltage generating section 42>, μ The VC0M voltage generating section 42 shown in FIG. 9 includes a supply operational amplifier shown in FIG. 7, a lion operational amplifier concept, and a supply ^ 〇3. -2, clamping transistors T31η and T311_2, resistors 5 and 2 = 312 D, instead of the step resistors 101 and 102 shown in Figure}. The other structures are shown in the VCOM voltage generating section 12 shown in FIG. &Quot; Supply operation amplifier is connected to the selection department and switching transistor 2 Selection operation amplifier 302, supply transistor T3〇3-—l, T30-03-2 Sweet resistance transistor T3U-1 and T311 The connection of —2 is shown in Figure 7. ί No. The supply transistor, T303-2, clamp transistor and T3U_2, = R3G5 are connected in series ^ between the reference node __3 and the node fine%. The node pm and the search circuit give an operation between $ 301 and the switching transistor SW2. The resistor 5 is connected between the clamp transistor T3Π-2 and the node N405L. 34 200532300 Diode 312-D is connected to the node between the supply operational amplifier and the reference node. The reference transistor is switched off and the switch transistor SW1 is connected to the clamp transistor T3. Between node N405H and node N405L ·. &quot;、 The connection relationship of the switching transistors SW1 to SW6 is shown in FIG. 1. <Operation> Next, a description will be given of one of the supply voltages generated by the step resistor legs of the VCM voltage generating section 42 shown in FIG. 9 in response to the selection of the selection section 102L from the control operation of the Japanese temple control section 31. The driving voltage selected by the selection unit 102L is then turned out to ° $ τca. One of the f-forces is the op amp 302 for selection, the transistor T303-! Disk ρΠ transistor T3U—bu T311-2. The implementation form_ 目 = 的 动 ^ Therefore, the driving voltage vc_ generated at the node_5Η is as shown in the following (Equation 4). That is, the dynamic voltage yam) = (He Lai post L) + (Amplitude voltage (Resistor R305) / (Resistance R304) (Equation 4) Like this' will correspond to the control signal Sb and the amplitude information Sc driving voltage VC0MH to the switch , The crystal SW1, and the driving voltage vcOML corresponding to the control signal Sb is supplied to the switching transistor gw. Secondly, the switching transistors SW1 to SW6 perform the same operation as in the first embodiment = The reason is that the driving voltage vc generated at the node N4055H and the driving voltage VQ outputted from the supply, the operational amplifier 301 to the node N4055L) are alternately output to the VC0M operational amplifier 13 (see FIG. 6). ). <Effect> As described above, the potential of the node N405H can be stabilized at "+ 5v" by appropriately switching the switching transistor SW1 to "1", so that the potential difference between the two ends of the supply transistor T303-2 can be made smaller than "(reference voltage VREFH) — (Reference voltage 35 200532300 VREFL) ”. Therefore, the potential difference between the two ends of the clamp transistors T311-1 and T311-2 can also be made smaller than "(reference voltage VREFH)-(reference voltage VREFL). As a result, it can be compared with the conventional drive shown in Fig. 13 Compared with the voltage generating device, the financial pressure of the supply transistors T303-1 and T303-2 can be reduced, which can reduce the circuit scale. Moreover, the process deviation of the supply transistor T303-1 can be reduced, so the supply power is reduced. The difference in the current characteristics of the crystal T303-1. Also, similar to the supply transistor T303-1, the difference in the current characteristics of the supply transistor T303-2 can be reduced. Through this, the corresponding control signal Sb and amplitude information can be accurately generated The driving voltages VC0MH and VC0ML of Sc. When using transistor 312-N as shown in FIG. 8 (A) or transistor 312-P as shown in FIG. 8 (B) instead of diode 312-D The same effect can be obtained. (Fifth Embodiment) <Overall Structure> FIG. 10 shows the overall structure of a driving voltage generating device 5 according to a fifth embodiment of the present invention. The device 5 includes a VCOM voltage generating unit 52 and the structure shown in FIG. Time control unit 31, instead of as shown in Figure 5 The time control unit 11 and vcoM voltage generating unit 22 are shown. The driving voltage generating device 5 further includes a diode 312-D as shown in Fig. 7. The other structure is the same as that in Fig. 5. The VCOM voltage generating unit 52 responds to time. The control signal Sa and the amplitude information Sc of the control unit generate the driving voltages VC0MH and VC0ML. The diode 312-D is connected to the node N512-1 between the VC0MH operational amplifier 23H and the switching transistor SW1 and the receiving reference voltage VSS. Between the reference node N512-2. &Lt; VC0M voltage generating section 52>, VC0M voltage generating section 52 shown in 10 is provided with a selection operational amplifier 302 shown in FIG. 7 and a supply transistor T303-1 to T303- 4. The resistors R304 and R305, and the clamping transistors T31M to T3Π-3 replace the ladder resistor 101L and the selection section 102L shown in Fig. 5. The other structure is the same as that in Fig. 5. The selection amplifier 302, supply The connection relationship between the transistor T303-1 to T303-4, the resistor R304 and the clamp transistor T311-1 to T311-3 is the same as that in Fig. 7. The resistor R305, the clamp transistor T31 丨 -3 and the supply transistor T3. 3-4 series connection 36 200532300 to the operational amplifier 23H and switch located at VC0MH The node N505H between the transistor SW1 and the reference node N301-5. The interconnection node N305L between the resistor R305 and the clamp transistor T31 is connected to the operational amplifier 23L for VC0ML. <Operation> VC0M shown in FIG. 10 Operation of the voltage generating section 52. First, as in the second embodiment, the selection unit 102H selects one of the plural supply voltages generated by the step resistor 101L. Next, the operational amplifier 23H for vcomh outputs the supply voltage selected by the selection unit 1_ as the voltage VCOMH.

另一方面,選擇用運算放大器302、供給用電晶體T3〇3—;[至 T303-4、電阻R304與R305、以及钳位電晶體T311—丨至了311一3, 執行與第3貫施形態中相同之動作。因此,在節點n3〇5l產生驅 動電壓VC0ML。其次,VC0ML用運算放大器23L將節點N305L所產 生之驅動電壓VC0ML輸出到開關電晶體SW2。 其次,開關電晶體SW1至SW6執行與在第2實施形態中相同 之動作。因此,從VC0MH用運算放大器23Η輪出到開關電晶體SW1 之驅動電壓VC0MH與從VC0ML用運算放大器23L輸出到開關電曰 體SW2之驅動電壓VC0ML輪流被輸出到輸出端子15。 曰曰 〈效果〉 如上所述,由於節點N24H之電位能夠穩定在“+5V” ,所以 能夠以低耐壓電晶體構成VC0MH用運算放大器23H。並且,由於節 點N24L之電位能夠穩定在“—5V” ,所以能夠以低耐壓電晶體構 成VC0ML用運算放大器23L。因此,能夠縮減電路規模。並且,能 夠提高VC0MH用運算放大器23H與VC0ML用運算放大器23L之^ 動能力(反應速度)。 ^ ” (第6實施形態) 〈整體結構〉 圖11表示本發明之第6實施形態之驅動電壓產生裝置6之整 體結構。裝置6具備時間控制部61與VC0M電壓產生部62,取代 37 200532300 it U與聰電壓產生部22。驅動電麵 控制信號Sb ===/1使用 ί ί ί^Ι; ΓI^fΓ!L 031;:; ™ 參考;;以3i;==:間之節點_以及接收 &lt; VC0M電麈產生部62之内部結構〉 1運曾;?大圖=示1聰龍產生部62具備如圖9所示之選擇用 ^ ίί/ 用電晶體T303—1與T303_2、電阻讎4盥 R305、以及鉗位電晶體與T3U = Kt3UL、 梯電阻咖與^擇部醜。其他結構與圖5相同 階 阻用P:放大器3〇2、供給用電晶體T303-1與T303-2、電 HE?聯 &gt;,rai-2與電阻讎5之互連節點娜H連接到vc〇丽用運算放 大器23H。 〈動作〉 說明如圖11所示之VC0M電壓產生部62之動作。 首先,與在第2實施形態中相同的,選擇部1〇2L選擇由階梯 ^阻101L所產生之複數供給電遷中之其中一個電遂。vc〇ML用運 部皿所之供賴輸出作為驅動電 另一方面,選擇用運算放大器3〇2、供給用電晶體Tgogq與 T303-2、電阻R304與R305,以及钳位電晶體T31M與T311 -2 38 200532300 執行與第4實施形態中相同之動作。因此,在^ 動電壓VC0MH。其次,髓Η用運算放大器23H ^ 區 生之驅動電壓VC0MH輸出到開關電晶體SW1。 ^ MUbH所產 其:人,開關心日體SW1至SW6執行與第2實 動作。因此,從VC0MH用運算放大器23H輸出 3 之驅動電壓VOM與從·ML用運算放大n 23L輪曰1 體SW2之驅動電壓VC0ML輪流地被輸出到輪出端子』开Ί關包日曰 〈效果〉On the other hand, the selection operational amplifier 302, the supply transistor T3 03-; [to T303-4, the resistors R304 and R305, and the clamp transistor T311-31 to 31-3 are performed, and the third implementation is performed. Same action in form. Therefore, the driving voltage VC0ML is generated at the node n3051. Next, the VC0ML uses the operational amplifier 23L to output the driving voltage VC0ML generated by the node N305L to the switching transistor SW2. Next, the switching transistors SW1 to SW6 perform the same operations as in the second embodiment. Therefore, the driving voltage VC0MH outputted from the operational amplifier 23Η for VC0MH to the switching transistor SW1 and the driving voltage VC0ML outputted from the operational amplifier 23L for VC0ML to the switching body SW2 are output to the output terminal 15 in turn. <Effect> As described above, since the potential of the node N24H can be stabilized at "+ 5V", the operational amplifier 23H for VC0MH can be constituted by a low withstand voltage crystal. In addition, since the potential of the node N24L can be stabilized at "-5V", the operational amplifier 23L for VC0ML can be constituted by a low withstand voltage crystal. Therefore, the circuit scale can be reduced. In addition, the operational capability (response speed) of the operational amplifier 23H for VC0MH and the operational amplifier 23L for VC0ML can be improved. ^ "(Sixth Embodiment) <Overall Structure> Fig. 11 shows the overall structure of a driving voltage generating device 6 according to a sixth embodiment of the present invention. The device 6 includes a time control section 61 and a VCM voltage generating section 62 instead of 37 200532300 it U and Satoshi voltage generating section 22. The driving electrical surface control signal Sb === / 1 uses ί ί ^ 1; ΓI ^ fΓ! L 031 ;: ™ reference ;; with 3i; ==: node between _ and Receiving &lt; internal structure of VC0M electric generating unit 62〉 1 large image = shown 1 Satoshi generating unit 62 is equipped with a selection as shown in Figure 9 ^ ί / transistor T303-1 and T303_2, resistor雠 4 R305, and clamp transistor and T3U = Kt3UL, ladder resistors and resistors. Other structures are the same as in Figure 5. P: amplifier 302, supply transistors T303-1 and T303- 2. Electric HE &gt;, the interconnection node NaH of rai-2 and resistor 连接 5 is connected to VC0 operational amplifier 23H. <Operation> The operation of the VC0M voltage generating unit 62 shown in FIG. 11 will be described. First, as in the second embodiment, the selection unit 102L selects one of the plurality of electric power supply generators generated by the step resistance 101L. Vc〇ML uses the supply output of the Ministry of Transport as the driving power. On the other hand, the op amp 302, the supply transistors Tgogq and T303-2, the resistors R304 and R305, and the clamp transistor T31M and T311 -2 38 200532300 performs the same operation as in the fourth embodiment. Therefore, the operating voltage VC0MH is used. Second, the driving voltage VC0MH generated by the operational amplifier 23H ^ is output to the switching transistor SW1. ^ Produced by MUbH It: human, switch heart sun body SW1 to SW6 perform the second real action. Therefore, the driving voltage VOM of 3 is output from the operational amplifier 23H for VC0MH and the driving voltage VC0ML of 1 body SW2 for operational amplifier n23L from · ML. "Alternatively output to the turn-out terminal"

如上所述,由於能夠以低耐壓電晶體構成Vc〇MH用運曾放 器23H與VC0ML用運算放大器23L,因此能夠縮減電路規模^且, 能夠提高VC0MH用運算放大器23H與VC0ML用運算放大哭23L之 驅動能力(反應速度)。 w 此外,在以上之本發明之實施形態中舉出具體數值加以說 明,但是未必侷限於這些具體例子,而能夠用其他適當數值加以 取代。 一產業上利用之可能性— 由於本發明之驅動電壓產生裝置能夠縮減電路規模,因此作 為以父流驅動方法驅動行動電話等液晶顯示面板之驅動電壓產生 裝置極為有用。 五、【圖式簡單說明】 圖1係表示本發明第1實施形態之驅動電壓產生裝置之整體 結構圖。 圖2(A)係表示圖1所示之階梯電阻1〇111及選擇部ι〇2Η之構 成例圖;圖2(B)係表示圖1所示之階梯電阻i〇il與選擇部102L 之構成例圖。 圖3(A)〜(F)係表示控制信號si至S6之輸出例之波形圖。 圖4(A)〜(〇係表示節點NH、【與NL之各自之電位變化之例 子之波形圖。 39 200532300 圖5係表不本發明第2實施形態之驅動電壓產生裝置之整體 結構圖。 6係表示本發明第3實施形態之驅動電壓產生裝置之整體 結構圖。 圖7係表示圖6所示之VC0M電壓產生部之内部結構圖。 圖8(A)及(B)係表示圖6中所使用之鉗位電路圖。 圖9係表示本發明第4實施形態所使用之咒 内部結構圖。 ㈣座生。P之 結構| 10係表示本發明第5實施形態之驅動電壓產生裝置之整體 圖11係表示本發明之第6實施形態之驅動電壓產生 體結構圖。 圖12係表示現有之驅動電壓產生裝置之整體結構圖。 圖13係表示現有驅動電壓產生裝置之整體結構圖。 【主要元件符號說明】 I、 2、3、5、6 驅動電壓產生裝置 II、 31、61、81、91 時間控制部 12、 22、32、42、52、62、82、92 VC0M 電壓產生部 13、 83 VC0M用運算放大器 ° 14、 24H、24L· 平滑電容 15 ^ 85 輸出端子 23Η、23L VC0MH用運算放大器 101Η、101L 階梯電阻 102Η、102L 選擇部 301供給用運算放大器 302選擇用運算放大器 312-D 二極體 312-Ν、312-Ρ 電晶體 200532300 801H、801L 階梯電阻 802H、802L 選擇部 901 供給用運算放大器 902 選擇用運算放大器 C14、C24H、C24L、C84 平滑電容 N14、N24H、N24L 節點 參考節點 N101H-1 、 N101H-2 、 N101L-1 、 N101L-2 N102H、N102L 節點 N103H、N103L 規定電壓供給節點 N301-1 〜N301-5、N312-2 參考節點 N303 互連節點 R111H-1 〜R111H-N 電阻 R111L-1 〜R111L-N 電阻 R304、R305 電阻 S1〜S6 控制信號 SW1〜SW6開關電晶體 ΐΟ〜t5 時間 T112H-1 〜T112H-N 電晶體 T303-1〜T303-4 供給用運算放大器 T311 -1〜T311 - 4 鉗位運算放大器 TAPH-1〜TAPH-N 分接頭 41As described above, since the VcMH operational amplifier 23H and the VC0ML operational amplifier 23L can be configured with a low withstand voltage crystal, the circuit scale can be reduced ^ and the VC0MH operational amplifier 23H and the VC0ML operational amplifier can be improved. 23L driving capacity (response speed). w In the above embodiment of the present invention, specific numerical values are given for explanation, but they are not necessarily limited to these specific examples, and can be replaced with other appropriate numerical values. Possibility of industrial utilization-Since the driving voltage generating device of the present invention can reduce the circuit scale, it is extremely useful as a driving voltage generating device for driving a liquid crystal display panel such as a mobile phone by a parent current driving method. V. [Brief Description of the Drawings] FIG. 1 is a diagram showing the overall structure of a driving voltage generating device according to the first embodiment of the present invention. FIG. 2 (A) is a diagram showing an example of the configuration of the step resistor 1011 and the selection section 1022 shown in FIG. 1; FIG. 2 (B) is a diagram showing the steps of the step resistance 101 and the selection section 102L shown in FIG. Structure example diagram. 3 (A) to (F) are waveform diagrams showing output examples of the control signals si to S6. 4 (A) to (0) are waveform diagrams showing examples of potential changes of respective nodes NH, [, and NL. 39 200532300 FIG. 5 is a diagram showing the overall structure of a driving voltage generating device according to the second embodiment of the present invention. 6 is a diagram showing the overall structure of a driving voltage generating device according to a third embodiment of the present invention. FIG. 7 is a diagram showing the internal structure of the VCOM voltage generating unit shown in FIG. 6. FIGS. 8 (A) and (B) are diagrams showing FIG. Figure 9 is a diagram showing the internal structure of a mantra used in the fourth embodiment of the present invention. The structure of the puppet. The structure of P | 10 shows the overall drive voltage generating device of the fifth embodiment of the present invention. Fig. 11 is a structural diagram of a driving voltage generator according to a sixth embodiment of the present invention. Fig. 12 is an overall structural diagram of a conventional driving voltage generating device. Fig. 13 is an overall structural diagram of a conventional driving voltage generating device. [Main Description of component symbols] I, 2, 3, 5, 6 Drive voltage generator II, 31, 61, 81, 91 Time control section 12, 22, 32, 42, 52, 62, 82, 92 VC0M voltage generation section 13, 83 VC0M Operational Amplifier ° 14, 24H, 24L · Smoothing capacitor 15 ^ 85 Output terminals 23Η, 23L VC0MH operational amplifier 101Η, 101L step resistor 102Η, 102L selection unit 301 supply operational amplifier 302 selection operational amplifier 312-D diode 312-N , 312-P transistor 200532300 801H, 801L step resistor 802H, 802L selection section 901 supply operational amplifier 902 selection operational amplifier C14, C24H, C24L, C84 smoothing capacitor N14, N24H, N24L node reference node N101H-1, N101H- 2, N101L-1, N101L-2 N102H, N102L Nodes N103H, N103L Specified voltage supply nodes N301-1 to N301-5, N312-2 Reference node N303 Interconnect node R111H-1 to R111H-N Resistors R111L-1 to R111L -N resistor R304, R305 resistor S1 ~ S6 control signal SW1 ~ SW6 switching transistor 电 〇 ~ t5 time T112H-1 ~ T112H-N transistor T303-1 ~ T303-4 supply operation amplifier T311 -1 ~ T311-4 clamp Bit Operational Amplifiers TAPH-1 ~ TAPH-N Tap 41

Claims (1)

200532300 十、申請專利範圍: 1. 一種驅動電壓產生裝置,包括: 第3部中=接收複數之第1供綱並輸出該第1供給電 第2壓選之^之用一於接收複數之第2供帽並輪出該第2供给電 4 串聯連接到前述第1選擇部與前述第2選擇部之間 Μ 開關; 乐1至第 第1規定電壓供給部,用於向前述第J關與前 ^之第1互連節點供應第丨規定電壓;以及 ^開關之間 弟2規定電壓供給部,用於向前述第3開關與前述 ^之第2互連節點供應第2規定電壓; 4開關之間 ^述^1開關連接到前述第丨選擇部與前述第2 2述第2關連接到前述第丨關與前述第3 _ ? ’ 2述第3關連接顺述第2關與前述第4開關之^ : I述第4關連接到前述第3開關與前述第2選丄’ H1 定為導通時,前述第1規定電壓供給部不二前述 當前述第4開關為導通時,前述第2規定電壓供給 第2規定電壓; |个1/、愿則返 1規疋電壓供給部之輸出阻抗低於前述第2選擇部之輪出 前規定電壓供給部之輪出阻抗低於前述第1選擇部之輪出 申請專利範圍第1項之驅動電壓產生裝置,其進-步包括: 卓1階梯電阻,串聯連接到接收第丨參考電壓之第丨參考· 接收第2參考電壓之第2參考節點之間,產生_ (N為自: ★數)不同電壓位準之第1供給電壓;以及 w 第2階梯電阻,串聯連接到接收第3參考電壓之第3參考節點與 42 200532300 =第4參考電壓之第4參考節點之間,產生請(M為自然 數)不同電壓位準之第2供給電壓; 月選擇部輸出由前述第1階梯電阻所產生之N個第1供給 電壓中之其中之一; 丽Ϊί!選ΪΪ輸出由前述第2階梯_所產生個第2供給 電壓中之其中之一; 給部包括連接到接收前述第1規定電壓之第 前、第1互連節點之間之第5開關; 2;入rC、堅,,部包括連接到接收前述第2規定電壓之第 ίΞίί 1 ϋ通時,前述第5開關為軸 3 通時,前述第6開關為_。 雨述第5開關之導通電阻小於前 中. 4 t第尸關之導通電阻小於前述第1二ΪΪ : •如申凊專利辄圍第2項之驅動電難 2=1參考龍高於前述第2參考 '、中· :述第3參考電虔高於前述第;JJ: 前述第1規定電麼滿足: m (弟2參考電壓)&lt; 广楚彳十 前述第2規定電壓滿、疋電壓)$ (第1參考電壓); (第4參考電壓)$ (第2規 ^申請專利範_ 2項之驅 ^ ) = ( H參考電麼)。 ;述第1階梯電阻包括輪出前US ’其中: =述第2階梯電阻包括輪出前述Μ個個第1分接頭; 剛述第1選擇部包括對應於前固七電麼之Μ個第2分接頭; 分接頭之Ν個第1選擇電晶體· ^梯電阻所含之Ν個第1 别述第2選擇部包括對應於前述第 分接頭之Μ個第2選擇電晶體· &amp;梯電阻所含之Μ個第2 43 200532300 前纖制觸㈣_與前述 前^個開第關擇艘電之晶ηΓ別連接到所對應之第2分接頭與前述 圍第2項之驅動1壓產生裝置,1中. ΐ=ί ί裝置進—娜:控術述第1衫剛電晶 前述控制部具有第1至第4模式; 在,第1、第2及第6開關電晶體斷開, • 前=中第’4使前,第3及匕難體斷間, 在=:以=關電第 在t,:述第3、第4及第5開關電晶體斷開Γ關電B曰體導通’ ^^㈢中^吏前述仏以及第—日體導通, '-種壓2產生 電晶趙斷開。 第^ 接收複數第1供給電壓並選擇前述第1供給電 # 生具有對應表示規定電位差之振幅信號 串第1選擇部與前述供給電流產生部之間之第1 ,連接前述第1選擇部與前述第丨_ · =供,流產生部與前述第/開:二 ·=第位於前述第2 甜顺述第1轉,胁將料1配狀電仅限制 44 200532300 之第1互連節點輸開關與前述第2開關之間 洳述第1開關連接到前述篦抑 、 前述第2_連接到前述3擇部f前述第2開關之間; 前述第3開關連接到前述望=關與J述第3開關之間; 前述第4開關連接到前述^述第4開關之間; 當前述第1開關為導通時,前^ ^、刚^5供0給電流產生部之間; 第1規定電壓;、^ 見疋電壓供給部不輸出前述 當第前=為導通時’前述第2規定電壓供給㈣^ 定電壓供給部之輸出阻抗低於前述供給電流產生部 H2峨壓供給部之輸纽抗低於前述第1選擇部之輸出 8.如申請專利範圍第7項之驅動產 写:;:述第1配線之第1節點與前述第1選擇部:括第' 前述供給電流產生部包括: 串聯體t接第 1第電;=且參考節點與第2參考節點之間之第1供給用電晶 第2差動放大電路,其一方之輸入端子連接到前 晶體與前述第2電阻之間之互連節點,在另 供…用電 幅信號,其輸出端子連接到前述第丨供二= 串聯連接到位於前述第2配線之第2節點與前述第 間之第2供給用電晶體、第i鉗位電晶體與第ί即點之 前述第2供給用電晶體連制前述第i參考節騎前甘^^曰曰體; 45 200532300 其間極接收前述第1供給用電晶體之閘極 前Hit電晶體連接翁述第1供給用電晶體與前述第2 乂、〔々电日日體之間,並在其閘極接收第1偏壓; 刖H 2鉗位電晶體連接到位於前述第2配線之第2節點 第1鉗位電晶體之間,在其閘極接收第2偏壓。/、,a 9·如申凊專利範圍第8項之驅動電壓產生裝置,其中· 電塵值為使得前述第Ϊ钳位電晶體之間極-源極 間電屋等於前述振幅情報之電壓值。 原木 10·如申請專利範圍第8項之驅動電壓產生裝置,盆十. =第2偏屢之賴值等於前述第2钳位電晶體之閉極—源極間 11·如申請專利範圍第7項之轉麵產生裝置, 第1配線之第1節點與前述第1選擇部之間ϊ第1 前述供給電流產生部包括: 串===參考節點與第2參考節點之間之第1供給用電晶 第曰2 就輸人端子連接顺述第1供給用電 =體與則述第2電阻之間之互連節點,在另一個輸入端子 剛述振幅信號,輸出端子連接到前述第j供給用電晶體之 極; 』 串聯連接到前述第1參考節點與第3參考節點之間之第2供 電晶體、第1及第2钳位電晶體、以及第3供給用電晶^ 串聯連接到位於前述第2 Si線之第2節點與前述第3參考節點 間之第3鉗位電晶體及第4供給用電晶體; 前述第2供給用電晶體連接到前述第1參考節點與前述第i鉗位 電晶體之間,並在其閘極接收前述第!供給用冑晶體之 產生之閘極電壓; 46 200532300 月曰曰體連接到前述第1供給用電晶體與前述第2 乂鉗^电日日體間,並在其閘極接收第丨偏壓,· 別if f ί!位電晶體連接到前述第1鉗位電晶體與前述第3供給 义用,日日體之間,並在其閘極接收第2偏壓; 給用電晶體連接顺述第2钳位電晶體與前述第3 乂參f即點之間,其閘極與其汲極彼此連接; 别if上曰:曰Ϊ連接到位於前述第2配線之第2節點與前述 電日日體之間,並在其閘極接收第3偏壓; 月’、考節點5用電曰”接到前述第3鉗位電晶體與前述第3 所產生極接收前述第3供給用電晶體之閘極 利範圍第11項之驅動電壓產生裝置,其中: ㈤體之問;㈣極_等於前述第3钳位電晶 電 連^到前述第2選擇部與前述第4開關之間之第2差動放大電 利範㈣8項之‘鶴電麵生裝置,I進-牛勺杯. 第以:;:位於前述第1配線之第f節點步與包ί述 第ί 路,連接到位於前述第2配線之第__ 該驅種動控電$電裝壓 置之方法,其中: 第1選擇部’用於接收複數之第!供給電壓並輪出該第1供給電 47 200532300 壓中之其中之一; 第接收複數之第2供給賴並輸㈣第2供給電 串聯連接到力述第1選擇部與前述第2選擇部之間之第1至 開關; 乐4 1 1 1 ^ 關之間^i弟連即點存在於所述第1開關與前述第2開 第門連ίί第2互ί節點與接收第2規定電壓之第2輪入 之間;Β,“弟2互連節點位於前述第3開關與前述第4開關 議观傭前述第2 應之第2規纖之阻抗低於前述第1 鈿述控制方法包括: 步驟(A),#铪、+、络! „ 第4與第5開4 2及第6開關斷開,並使前述第3、 步?前述第卜第2及第6開_開,並使前述第3、 昂4興弟5開關導通; ,3開V導、,:,步,驟⑴切換到前述步驟⑻時,使前述第 關導通2/關導通,其次使前述第1與第6開 步驟(D),述苐4及弟5開關斷開;以及 2開關暮步驟⑻切換到前述步驟⑴時,使前述第 開關it禮前述第3開關斷開,其次使前述第4及第6 開關導通並使前述第1及第6開關斷開。 十一、囷式: 48200532300 X. Scope of patent application: 1. A driving voltage generating device, including: in Part 3 = receiving the first supply of the plurality and outputting the first supply of the second voltage; 2 supply the cap and rotate out the second power supply 4 connected in series to the M switch between the first selection section and the second selection section; Le 1 to the first specified voltage supply section for The first interconnecting node of the former ^ supplies the first prescribed voltage; and the second prescribed voltage supply unit between the switches is for supplying the second prescribed voltage to the aforementioned third switch and the aforementioned second interconnecting node; 4 switches The ^ 1 ^ switch is connected to the aforementioned 丨 selection section and the aforementioned 2nd to 2nd off. Connected to the aforementioned 丨 off and the aforementioned 3rd _? ^ Of the 4 switches: The fourth switch is connected to the third switch and the second option. When H1 is set to be on, the first prescribed voltage supply unit is different. When the fourth switch is on, the first 2 prescribed voltage to supply the second prescribed voltage; | 1 /, may return to the regulation of the voltage supply department The drive voltage generating device whose impedance is lower than that of the predetermined voltage supply unit before the second selection unit has a lower output impedance than that of the first selection unit in the first range of the patent application scope, the driving voltage generating device includes the following steps: The resistor is connected in series between the second reference node receiving the first reference voltage and the second reference node receiving the second reference voltage, and generates _ (N is from: ★ number) the first supply voltage of different voltage levels; and w The second step resistor is connected in series between the third reference node that receives the third reference voltage and the fourth reference node that 42 200532300 = the fourth reference voltage, and generates a second supply (M is a natural number) with a different voltage level Voltage; the month selection section outputs one of the N first supply voltages generated by the aforementioned first step resistance; the Ϊ! Selection output one of the second supply voltages generated by the aforementioned second step_ 1. The supply unit includes a fifth switch connected between the first and the first interconnection nodes that receive the first specified voltage; 2; the rC, the power supply, the unit includes the first connection that is connected to the second specified voltage; 1 When communicating, Said first switch when the shaft 3 through 5, the sixth switch is _. The on-resistance of the 5th switch is less than that of the previous middle. The on-resistance of the 4th corpse is less than the above-mentioned first two: • The driving electrical difficulty of the 2nd item of the application of the patent application 2 is higher than the previous reference. 2Reference ', Medium ·: The third reference voltage is higher than the first; JJ: The first specified voltage satisfies: m (the second reference voltage) &lt; ) $ (No. 1 reference voltage); (No. 4 reference voltage) $ (No. 2 ^ Patent application application _ 2 driving ^) = (H reference power). ; Said the first step resistor includes US before the turn out; where: = Said the second step resistor includes the aforementioned M first taps; the first selection section just includes the M second Taps; N 1st selection transistors of the taps; N 1st alternatives included in the ladder resistors; 2nd selection sections including M 2nd selection transistors corresponding to the aforementioned taps; &amp; ladder resistors Contained M No. 2 43 200532300 front fiber contact _ and the aforementioned first ^ on and off selection of the ship's crystal ηΓ Do not connect to the corresponding second tap and the above-mentioned drive 1 pressure Device, 1. ΐ = ί Device access—Na: The first control unit of the first transistor has the first to fourth modes; the first, second, and sixth switching transistors are turned off. • The front = 4th in the middle makes the front, the 3rd, and the 3rd dagger interrupted, and the ==== the power is turned off at t ,: the 3rd, 4th, and 5th switching transistors are turned off and the power is turned off. The body is turned on, and the first solar body is turned on, and the --type pressure 2 generates the electric crystal and is turned off. The ^ th receiving a plurality of first supply voltages and selecting the first supply power # 1 has a first signal between the first selection unit and the supply current generation unit corresponding to an amplitude signal string representing a predetermined potential difference, and connects the first selection unit and the aforementioned No. 丨 _ = Supply, current generation unit and the aforementioned No./On: II. = No. 1 is located in the first turn of the above-mentioned second sweet order, and the distribution of electricity to the material No. 1 is restricted to the first interconnection node of 44 200532300. The first switch is connected to the second switch and the second switch is connected to the second switch, and the second switch is connected to the second switch. The third switch is connected to the above switch. 3 switches; the aforementioned fourth switch is connected to the aforementioned fourth switch; when the aforementioned first switch is on, the first ^, and ^ 5 are provided between 0 and the current generating section; the first specified voltage; ^ See that the voltage supply unit does not output the above. When the first = is on, the aforementioned second specified voltage supply ㈣ ^ The output impedance of the constant voltage supply unit is lower than the input impedance of the supply current generation unit H2 and the voltage supply unit. Output in the aforementioned first selection section 8. If item 7 of the scope of patent application Drive production write:;: The first node of the first wiring and the aforementioned first selection unit: including the aforementioned supply current generating unit includes: The serial body t is connected to the first electric power; = and the reference node and the second reference node In the first differential amplifier circuit for the first supply transistor, one input terminal is connected to the interconnection node between the front crystal and the second resistor, and the other output signal is connected to the output terminal. The aforementioned second supply = The second supply transistor connected in series to the second node located in the aforementioned second wiring and the aforementioned second supply transistor, the i-th clamp transistor and the aforementioned second supply transistor which is immediately connected Make the aforementioned i-th reference section to ride the front gan ^^ said body; 45 200532300 during which the gate receives the first supply transistor's front gate transistor and connects the first supply transistor with the aforementioned second 乂, [ 々 Electricity between the sun and the sun, and receives the first bias voltage at its gate; 刖 H 2 clamp transistor is connected between the first clamp transistor at the second node of the second wiring, and at its gate Receive the second bias. / ,, a 9 · The driving voltage generating device according to item 8 of the patent application, wherein the electric dust value is the voltage value that makes the electrode-source-to-source electric house between the first clamp transistor and the source voltage equal to the amplitude information. . Log 10 · If the driving voltage generating device of item 8 in the scope of the patent application, the pot is ten. = The value of the second bias is equal to the closed-source between the second clamping transistor 11 · If the scope of the patent application is seventh The rotating surface generating device of the item, between the first node of the first wiring and the first selection section, the first supply current generating section includes: a string for the first supply between the reference node and the second reference node The transistor 2 is connected to the input terminal in order to describe the interconnection between the first supply power source and the second resistor. The other input terminal has just described the amplitude signal, and the output terminal is connected to the j-th supply. The pole of the transistor; "The second power supply crystal, the first and second clamp transistors, and the third supply transistor connected in series between the aforementioned first reference node and the third reference node ^ are connected in series to A third clamp transistor and a fourth supply transistor between the second node of the second Si line and the third reference node; the second supply transistor is connected to the first reference node and the i-th clamp Between the transistor and the gate at its gate! The gate voltage generated by the supply tritium crystal; 46 200532300, said that the body is connected between the first supply transistor and the second second power clamp, and receives the first bias voltage at its gate. · Don't if f ί! The transistor is connected between the first clamp transistor and the third supply, the solar and solar body, and receives the second bias voltage at its gate; Between the second clamp transistor and the aforementioned third reference point f, its gate and its drain are connected to each other; do n’t say on the above: Yue is connected to the second node located on the aforementioned second wiring and the aforementioned electric day Between the body and receiving the third bias voltage at its gate; “the test node 5 uses electricity” to connect the third clamp transistor and the third generated transistor to receive the third supply transistor. The driving voltage generating device of the eleventh range of the gate pole, wherein: the body of the body; the pole _ is equal to the third clamp transistor which is electrically connected to the second between the second selection section and the fourth switch. Differential amplification electric power range 8 items of 'Hedian electric surface generating device, I enter-cow spoon cup. No.:;: Located at the first line of the aforementioned first wiring The f-node step and package are described in the first road, which is connected to the second __ method of driving the electric power $ electric device, which is located in the aforementioned second wiring, wherein: The first selection section is used to receive a plurality of first! Supply the voltage and rotate out one of the first power supply 47 200532300. The second supply power is received and the second power supply is input. The second power supply is connected in series to the first selection unit and the second selection unit. The first to the switch between the two; Le 4 1 1 1 ^ The connection between the ^ i link point exists between the first switch and the aforementioned second open door link, the second mutual node, and receiving the second specified voltage Between the second round; B, "The second interconnect node is located between the aforementioned third switch and the aforementioned fourth switch, and the impedance of the second fiber of the second response of the second switch is lower than the aforementioned first control method including: Step (A), # 铪, +, network! „The 4th and 5th switches 4 2 and 6 are turned off, and the aforementioned 3rd, step? 2nd and 6th switches are opened, and the 3rd, 5th and 5th switches 5 are turned on; , 3, turn on V, ,,,,,, Step, when switching to the previous step, turn on the 2nd turn on / off, and then turn on the 1st and 6th turn on steps (D), as described in 4 and 5 The switch is turned off; and when the switch 2 is switched to the previous step, the third switch is turned off, and the fourth and sixth switches are turned on, and the first and sixth switches are turned off. On. Eleventh style: 48
TW094107686A 2004-03-16 2005-03-14 Driving voltage generation device and method for controlling driving voltage generation device TW200532300A (en)

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