KR20060043675A - Driving voltage generation device and method for controlling driving voltage generation device - Google Patents

Abstract

The present invention constitutes a driving voltage generating device by a circuit of a low breakdown voltage meter.

First, the switches SW1, SW3, SW6 are turned off, and the switches SW2, SW4, SW5 are turned on. At this time, the driving voltage VCOML is supplied to the node NC. Next, the switch SW3 is turned on and the switch SW4 is turned off. At this time, the specified voltage VSETH supplied from the specified voltage supply node N103H to the node NH has a lower impedance than the driving voltage VCOML supplied from the selector 102L to the node NC. The potential variation of NH) is smaller than the potential variation of the node NC. That is, the potential of the node NH is stabilized at the voltage value of the specified voltage VSETH.

Description

DRIVING VOLTAGE GENERATION DEVICE AND METHOD FOR CONTROLLING DRIVING VOLTAGE GENERATION DEVICE}

1 is an overall configuration diagram of a driving voltage generating device according to a first embodiment of the present invention.

FIG. 2A shows a configuration example of the ladder resistor 101H and the selection section 102H shown in FIG. 1, and FIG. 2B shows a configuration example of the ladder resistor 101L and the selection section 102L shown in FIG. 1. To represent.

Fig. 3 is a waveform diagram showing an example of output of control signals S1 to S6.

4 is a waveform diagram showing an example of a potential change in each of the nodes NH, NC, and NL.

5 is an overall configuration diagram of a driving voltage generating device according to a second embodiment of the present invention.

6 is an overall configuration diagram of a driving voltage generating device according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating an internal configuration of the VCOM voltage generation unit shown in FIG. 6.

FIG. 8 is a diagram showing an example of a clamp circuit used in FIG. 6; FIG.

9 is an internal configuration diagram of a VCOM voltage generator used in the fourth embodiment of the present invention.

10 is an overall configuration diagram of a driving voltage generating device according to a fifth embodiment of the present invention.

11 is an overall configuration diagram of a driving voltage generating device according to a sixth embodiment of the present invention.

12 is a general configuration diagram of a conventional driving voltage generating device.

13 is an overall configuration diagram of a conventional driving voltage generating device.

Explanation of symbols on the main parts of the drawings

1, 2, 3, 5, 6: driving voltage generator 11, 31, 61: timing controller

12, 22, 32, 42, 52, 62: VCOM voltage generator

13: VCOM operational amplifier 14, 24H, 24L: smoothing capacity

15: Output terminal 101H, 101L: Ladder resistance

102H, 102L: Selection section SW1 to SW6: Switch transistor

N101H-1, N101H-2, N101L-1, N101L-2, N301-1 to N301-5, N312-2

 Reference Node

N103H, N103L: Regulatory voltage supply node 23H: Operational amplifier for VCOMH

23L: Operational Amplifier for VCOML

301, T303-1 to T303-4: Operational amplifier for supply

302: Op Amp for Selection R304, R305: Resistance

312-D: Diode 312-N, 312-P: Transistor

T311-1 to T311-4: Operational Amplifier for Clamp

The present invention relates to a device for controlling a drive voltage for alternatingly driving a load such as a liquid crystal display panel and a control method of the device, and more particularly, to a drive voltage generation device constituted by a circuit of a low breakdown voltage meter; The control method is related.

In order to alternatingly drive (e.g., line inverted) a liquid crystal display panel of a portable device (e.g., a mobile phone), a conventional liquid crystal drive device controls the driving voltage supplied to the counter electrode of the liquid crystal display panel. And a driving voltage generator (see, for example, Japanese Patent Application Laid-Open No. 2003-216256). This drive voltage generator inverts the polarity of the drive voltage in accordance with a predetermined timing.

(Conventional drive voltage generator 8)

<Configuration and operation>

The overall configuration of a conventional drive voltage generator 8 is shown in FIG. The apparatus 8 includes a timing controller 81, a VCOM voltage generator 82, an operational amplifier 83 for VCOM, a smoothing capacity C84, and an output terminal 85. The device 8 alternately outputs driving voltages VCOMH and VCOML to counter electrodes (not shown) of the liquid crystal display panel.

The timing controller 81 controls the voltage values of the drive voltages VCOMH and VCOML generated by the VCOM voltage generator 82 using the control signals Sa and Sb.

The VCOM voltage generator 82 includes ladder resistors (ladder type resistors) 801H and 801L, selectors 802H and 802L, and switch transistors SW3 and SW4.

The ladder resistor 801H and the selector 802H have a configuration as shown in FIG. 2A, for example. The ladder resistor 801H generates a plurality of supply voltages having different voltage values from each other. The selector 802H is composed of a plurality of select transistors. The selector 802H selects any one of the plurality of supply voltages generated by the ladder resistor 801H in accordance with the control signal Sa from the timing controller 81. The control signal Sa has a voltage value equal to the potential difference ((reference voltage VREFH)-(reference voltage VSSH)) between the reference node N801H-1 and the reference node N801H-2. The supply voltage selected by the selection unit 802H is output as the drive voltage VCOMH.

The ladder resistor 801L and the selector 802L have a configuration as shown in FIG. 2B, for example. The ladder resistor 801L generates a plurality of supply voltages having different voltage values. The selector 802L is composed of a plurality of select transistors. The selector 802L selects any one of the plurality of supply voltages generated by the ladder resistor 801L in accordance with the control signal Sb from the timing controller 81. The control signal Sb has a voltage value equivalent to the potential difference ((reference voltage VSSL)-(reference voltage VREFL)) between the reference node N801L-1 and the reference node N801L-2. The supply voltage selected by the selection unit 802L is output as the drive voltage VCOML.

The switch transistors SW3 and SW4 are connected in series between the selector 802H and the selector 802L. In addition, the timing controller 81 alternately sets the control signals S3 and S4 to " H level " in accordance with the timing signal TIMING from the outside, as shown in Figs. The control signals S3 and S4 are voltages for turning on the switch transistors SW3 and SW4 when they are at "H level", and are voltages for turning off the switch transistors SW3 and SW4 when they are at "L level". As a result, the drive voltage VCOMH from the selector 802H and the drive voltage VCOML from the selector 802L are alternately applied to the interconnect node NC of the switch transistor SW3 and the switch transistor SW4. Supplied.

The VCOM operational amplifier 83 outputs the drive voltages VCOMH and VCOML supplied by the VCOM voltage generator 82 to the output terminal 85. The smoothing capacity C84 is configured to smooth the output variations of the VCOM operational amplifier 83 and is provided between the node N84 and the ground node existing between the VCOM operational amplifier 83 and the output terminal 85. Is connected to.

The driving voltages VCOMH and VCOML output from the operational amplifier 83 for VCOM are connected to the counter electrode of the liquid crystal display panel (in this case, the panel load C (LC) as a load capacitance of the liquid crystal display panel) through the output terminal 85. Is shown.

Here

(Reference voltage VREFL) ≤ (reference voltage VSSH) ≤ (reference voltage VREFH)

(Reference voltage VREFL) ≤ (reference voltage VSSL) ≤ (reference voltage VREFH).

Specifically,

(Voltage value of reference voltage VREFH) = "+ 5V"

(Voltage value of the reference voltages VSSH and VSSL) = "0V"

(The voltage value of the reference voltage VREFL) = "-5V".

<Voltage value of supply voltage>

The voltage value of the supply voltage generated by the ladder resistor 801H represents the potential (reference voltage VREFH = "+ 5V") of the highest reference node N801H-1. Therefore, the voltage value of the drive voltage VCOMH represents the maximum "+ 5V". The voltage value of the supply voltage generated by the ladder resistor 801L represents the potential (reference voltage VREFL = "-5V") of the lowest reference node N801L-2. Therefore, the voltage value of the drive voltage VCOML represents the minimum "-5V".

<Withstand voltage of switch transistors SW3 and SW4>

The potential difference between both ends of the switch transistor SW3 is 10V ((reference voltage VREFH = "+ 5V")-(reference voltage VREFL = "-5V")). On the other hand, the potential difference between both ends of the switch transistor SW4 is also 10 V ((reference voltage VREFH = " + 5V ")-(reference voltage VREFL = " -5 V ") at the same time as the switch transistor SW3. . Therefore, the switch transistors SW3 and SW4 need to have a resistance of 10V.

(Conventional drive voltage generator 9)

<Configuration and operation>

FIG. 13 shows the overall configuration of one conventional drive voltage generator 9. As shown in FIG. This apparatus 9 includes a timing controller 81 and a VCOM voltage generator 92 instead of the timing controller 81 shown in FIG. 12, the VCOM voltage generator 82. The other structure is the same as that of FIG.

The timing controller 91 controls the voltage values of the drive voltages VCOMH and VCOML generated by the VCOM voltage generator 92 using the control signal Sa and the amplitude information Sc. The amplitude information Sc is a voltage (amplitude voltage VREFM) having a voltage value corresponding to the voltage difference (amplitude) between the driving voltage VCOMH and the driving voltage VCOML.

The VCOM voltage generator 92 replaces the ladder resistor 801L and the selector 802L shown in FIG. 12 with the operational operational amplifier 901, the operational operational amplifier 902, and the supply transistors T903-1 to ∼. T903-4) and resistors R904 and R905. The selection operational amplifier 902, the supply transistor T903-1, and the resistor R904 constitute a voltage current conversion circuit. Therefore, a supply current having a current value corresponding to the voltage value of the amplitude information Sc (amplitude voltage VREFM) flows through the supply transistor T903-1 and the resistor R904. Since the current mirror circuit is formed by the supply transistors T903-1 and T903-2, and the current mirror circuit is formed by the supply transistors T903-3 and T903-4, the resistor R905 and the supply transistor are provided. In T903-4, a supply current flowing to the supply transistor T903-1 flows. Therefore, the driving voltage VCOML is generated at the interconnect node N905 -L of the resistor R905 and the supply transistor T903-4.

(Drive voltage (VCOML)) = (Drive voltage (VCOMH))-(Amplitude voltage (VREFM) x (resistance (R905)) / (resistance (R904))

Next, the switch transistors SW3 and SW4 are turned on alternately so that the node NC alternates the drive voltage VCOMH from the supply operational amplifier 901 and the drive voltage VCOML generated at the node N905L. Is supplied.

And here,

(Reference voltage VREFL) ≤ (reference voltage VSSH) ≤ (reference voltage VREFH)

(Reference voltage VREFL) ≤ (reference voltage VSS) ≤ (reference voltage VREFH).

Specifically,

(Voltage value of reference voltage VREFH) = "+ 5V"

(Voltage values of reference voltages VSSH and VSS) = "0V"

(The voltage value of the reference voltage VREFL) = "-5V".

<Voltage value of supply voltage>

The voltage value of the supply voltage generated by the ladder resistor 801H represents the potential (reference voltage VREFH = "+ 5V") of the highest reference node N801H-1. Therefore, the voltage value of the drive voltage VCOMH represents the maximum "+ 5V". The voltage value of the drive voltage VCOML generated at the node N905L indicates the potential (reference voltage VREFL = "-5V") of the lowest reference node N901-5. Therefore, the switch transistors SW3 and SW4 need to have a resistance of 10V, similar to the driving voltage generator shown in FIG.

However, in the conventional drive voltage generator 8 shown in Fig. 12, when the switch transistor SW3 is switched from off to on, and the switch transistor SW4 is switched from on to off, the selection unit 802H and the switch are switched. There is a possibility that the potential of the node N802H existing between the transistors SW3 falls to the voltage value of the driving voltage VCOML. At this time, among the plurality of selection transistors included in the selection unit 802H, the potential difference between both ends is "(reference voltage VREFH-reference voltage VREFL)". Therefore, in the plurality of selection transistors included in the selection unit 802H, although the voltage value of the control signal Sa is 5V ((+ 5V)-(0V)), the plurality of selection transistors are 10V ((+ 5V)-(-5V)). It is necessary to have a breakdown voltage (the absolute maximum rating needs to be greater than 10V). On the other hand, when the switch transistor SW4 is switched from off to on, and the switch transistor SW3 is switched from on to off, the potential of the node N802L existing between the selection unit 802L and the switch transistor SW4. Since the voltage may rise to the voltage value of the driving voltage VCOMH, the selection transistor included in the selection unit 802L also needs to have a breakdown voltage of 10V, similarly to the selection unit 802H. Thus, it is necessary to make the selection part 802H, 802L into a circuit structure with a high breakdown voltage (high breakdown voltage circuit).

In general, the area of the high breakdown voltage transistor is larger than the area of the low breakdown voltage transistor. Specifically, the area of the transistor having a breakdown voltage of "10V" is about four times the area of a transistor having a breakdown voltage of "5V". Here, it is assumed that the gradation level of the driving voltages VCOMH and VCOML is "64 gradations". In this case, the area of the selection portion 802H shown in FIG. 12 is about 500 times as compared with the case where the selection portion 802H shown in FIG. 12 is constituted by a selection transistor of 5V breakdown voltage.

In recent years, the demand for high precision liquid crystal display panels has increased in mobile phones and the like. With high precision of the liquid crystal display panel, it is necessary to increase the gradation level of the driving voltages VCOMH and VCOML (that is, the number of supply voltages generated by the ladder resistors 801H and 801L). As the number of supply voltages increases, the number of selection transistors included in the selection units 802H and 802L also increases. As described above, since the circuit scale of the driving voltage generator increases as the liquid crystal display panel becomes more precise, it is important to reduce the circuit scale of the driving voltage generator.

In the drive voltage generator 9 shown in Fig. 13, since the potential of the node N905L may rise to " + 5V ", the supply transistor T903-4 is 10V ((+ 5V)-(-5V). It is necessary to have internal pressure of). In addition, since there is a possibility that the potential difference between both ends of each of the supply transistors T903-2 and T903-3 becomes "reference voltage VREFH-(reference voltage VREFL), the supply transistors T903-2 and T903-3). Must have a breakdown voltage of 10 V ((+5 V)-(-5 V)) and in a current mirror circuit constituted by the supply transistor T903-1 and the supply transistor T903-2, Since the transistor T903-1 preferably has the same current characteristics as the transistor T903-2, the transistor T903-1 has a breakdown voltage of 10V ((+ 5V)-(-5V)). In addition, since the potential difference between both ends of the supply operational amplifier 901 may also be "reference voltage VREFH-(reference voltage VREFL), the transistor having the supply voltage of the supply operational amplifier 901 having a breakdown voltage of 10V is required. In this way, the selection unit 802H, the supply operational amplifier 901, the supply current generation unit (the select operational amplifier 902, the supply transistor) Is required to be site (T903-1~T903-4), resistors (R904, R905)) to configure a high pressure circuit (high voltage system circuit).

In general, the higher the breakdown voltage of a transistor, the slower the response speed of the transistor. In general, the high breakdown voltage transistor has a larger variation (process variation) in the manufacturing process than the low breakdown voltage transistor. Therefore, the current mirror circuit formed by the high breakdown voltage transistor has a larger variation in current characteristics than the current mirror circuit formed by the low breakdown voltage transistor. Therefore, in the drive voltage generation device 9 shown in FIG. 13, it is difficult to accurately generate drive voltages VCOMH and VCOML in accordance with the control signal Sa and the amplitude information Sc. In addition, when an operational amplifier is described, an operational amplifier using a high breakdown voltage transistor has a lower driving capability (response speed) than an operational amplifier using a low breakdown voltage transistor.

SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a driving voltage generating device having a circuit of a low withstand voltage meter.

According to one aspect of the present invention, a drive voltage generator includes a first selector, a second selector, first to fourth switches, a first specified voltage supply and a second specified voltage supply. . The first selector receives a plurality of first supply voltages and outputs any one of the first supply voltages. The second selector receives a plurality of second supply voltages and outputs any one of the second supply voltages. The first to fourth switches are connected in series between the first selector and the second selector. The first specified voltage supply unit supplies a first specified voltage to the first interconnect node of the first switch and the second switch. The second specified voltage supply unit supplies a second specified voltage to the second interconnect node of the third switch and the fourth switch. The first switch is connected between the first selector and the second switch. The second switch is connected between the first switch and the third switch. The third switch is connected between the second switch and the fourth switch. The fourth switch is connected between the third switch and the second selector. The first specified voltage supply unit does not supply the first specified voltage when the first switch is in an ON state. The second specified voltage supply unit does not supply the second specified voltage when the fourth switch is in an ON state. The output of the first specified voltage supply section has a lower impedance than the output of the second select section. The output of the second specified voltage supply section has a lower impedance than the output of the first select section.

In the driving voltage generator, a voltage generated at the third interconnection node of the second switch and the third switch is supplied to the device at a later stage. For example, when the second switch and the third switch are turned on alternately, the voltage of the first interconnect node and the voltage of the second interconnect node can be alternately supplied to the later device. One of the output of the first selector and the output of the first specified voltage supply part is supplied to the first interconnect node. On the other hand, either of the output of the second selector and the output of the second specified voltage supply unit is supplied to the second interconnect node. Therefore, by suitably turning on / off the 1st-4th switches, either the output of a 1st selection part and the output of a 2nd selection part can be supplied to the apparatus of a later stage. Wherein the third and fourth switches are on and the second switch is off (the output of the second selector is fed to the third interconnect node), the second switch is on and the third switch is off. By leaving the first switch off before switching to the state, it is possible to supply the output of the first specified voltage supply to the first interconnect node before the second switch is switched from off to on. Since the output of the first specified voltage supply portion has a lower impedance than the output of the second select portion, the potential of the first interconnect node remains stable at the voltage value of the first specified voltage. Similarly, from the state in which the first and second switches are on and the third switch is off (with the output of the first selector supplied to the third interconnect node), the third switch is on and the second switch is off. By leaving the fourth switch off before switching to the state, the output of the second specified voltage supply can be supplied to the second interconnect node before the third switch is switched from off to on. Since the output of the second specified voltage supply portion has a lower impedance than the output of the first select portion, the potential of the second interconnect node remains stable at the voltage value of the first specified voltage. If the voltage value of the first specified voltage is an appropriate value (for example, the voltage value indicated by the output of the first selector), the potential difference between the input side and the output side in the first selector can be made smaller than before. Therefore, the breakdown voltage of the first selector can be lowered (for example, a low breakdown voltage transistor). Similarly, if the voltage value of the second specified voltage is an appropriate value (for example, the voltage value indicated by the output of the second selector), the potential difference between the input side and the output side in the second selector can be made smaller than before. Therefore, the breakdown voltage of the second select portion can be made low (for example, it can be constituted by a low breakdown voltage transistor). In this way, the breakdown voltage of each of the first and second selection units can be reduced, so that the circuit size can be reduced.

Preferably, the drive voltage generator further includes a first ladder resistor and a second ladder resistor. The first ladder resistor is connected in series between the first reference node receiving the first reference voltage and the second reference node receiving the second reference voltage, so that N first supply units having different voltage levels (N is a natural number) are supplied. Generate a voltage. The second ladder resistor is connected in series between the third reference node receiving the third reference voltage and the fourth reference node receiving the fourth reference voltage, so that the second supply of M pieces (M is a natural number) having different voltage levels from each other. Generate a voltage. The first selector outputs any one of the N first supply voltages generated by the first ladder resistor. The second selector outputs any one of the M first supply voltages generated by the second ladder resistor. The first specified voltage supply unit includes a fifth switch. A fifth switch is connected between the first input node receiving the first specified voltage and the first interconnect node. The second specified voltage supply unit includes a sixth switch. A sixth switch is connected between the second input node receiving the second specified voltage and the second interconnect node. The fifth switch is turned off when the first switch is in the on state. The sixth switch is turned off when the fourth switch is in the on state.

In the driving voltage generator, if the fifth switch is turned on before the second switch is turned on and the third switch is turned off from the state in which the output of the second selector is supplied to the third interconnect node. The output of the first regulated voltage supply may be supplied to the first interconnect node before the second switch is switched from off to on. Similarly, if the sixth switch is turned on before the third switch is turned on and the second switch is turned off from the state in which the output of the first selector is supplied to the third interconnect node, the third switch is turned on. A second specified voltage can be supplied to the second interconnect node before switching from off to on.

Preferably, the on resistance of the fifth switch is smaller than the second ladder resistance. The on resistance of the sixth switch is smaller than the first ladder resistance.

In the drive voltage generator, the impedance of the first specified voltage supplied to the first interconnect node can be lower than the output impedance of the second selector. Similarly, the impedance of the second specified voltage supplied to the second interconnect node can be made lower than the output impedance of the first selector.

Preferably, the first reference voltage is higher than the second reference voltage. The third reference voltage is higher than the fourth reference voltage. The first reference voltage is (second reference voltage) ≤ (first specified voltage) ≤ (first reference voltage). The second reference voltage is (fourth reference voltage) ≤ (second specified voltage) ≤ (third reference voltage).

In the drive voltage generation device, the potential difference between the input side and the output side can be made smaller in the first selector than in the prior art. Similarly, in the second selector, the potential difference between the input side and the output side can be made smaller than before.

Preferably, the first ladder resistor includes N first taps. The N first taps output the N supply voltages. The second ladder resistor includes M second tabs. M second taps output the M supply voltages. The first selector includes N first select transistors. N first select transistors correspond to N first taps included in the first ladder resistor. The second selector includes M second select transistors. The M second select transistors correspond to the M second taps included in the second ladder resistor. Each of the N first select transistors is connected between a corresponding first tap and the first switch transistor. The M second select transistors are respectively connected between a corresponding second tap and the second switch transistor.

Preferably, the drive voltage generator further comprises a control unit. The control unit has first to fourth modes and includes the first to sixth switch transistors. The control unit turns off the first, second, and sixth switch transistors in the first mode, and turns on the third, fourth, and fifth switch transistors. The controller turns off the first, third and sixth switch transistors and turns on the second, fourth and fifth switch transistors in the second mode. The control unit turns on the first, second, and sixth switch transistors in the third mode, and turns off the third, fourth, and fifth switch transistors. The controller turns on the first, third, and sixth switch transistors and turns off the second, fourth, and fifth switch transistors in a fourth mode.

According to another aspect of the present invention, a drive voltage generator includes a first selector, a supply current generator, first to fourth switches, first wiring, second wiring, second resistance, And a clamp circuit, a first specified voltage supply unit for outputting a first specified voltage, and a second specified voltage supply unit for outputting a second specified voltage. The first selector receives a plurality of first supply voltages and outputs any one of the first supply voltages. The supply current generation unit generates a supply current having a current value corresponding to an amplitude signal representing a predetermined potential difference. The first to fourth switches are connected in series between the first selector and the supply current generator. The first wiring connects the first selector and the first switch. The second wiring connects the supply current generator and the fourth switch. The first resistor is connected between the first node present in the first wiring and the second node present in the second wiring. The clamp circuit is connected to the first wiring and limits the potential of the first wiring within a predetermined range. The first specified voltage supply unit outputs a first specified voltage to the first interconnect node of the first switch and the second switch. The first specified voltage supply unit outputs a second specified voltage to the second interconnect node of the third switch and the fourth switch. The first switch is connected between the first selector and the second switch. The second switch is connected between the first switch and the third switch. The third switch is connected between the second switch and the fourth switch. The fourth switch is connected between the third switch and the supply current generator. The first specified voltage supply unit does not output the first specified voltage when the first switch is in an ON state. The second specified voltage supply unit does not output the second specified voltage when the fourth switch is in an ON state. The output of the first specified voltage supply unit has a lower impedance than the output of the supply current generator. The output of the second specified voltage supply section has a lower impedance than the output of the first select section.

In the above driving voltage generator, since the potential difference between the input side and the output side in the supply current generator can be made smaller than before, the breakdown voltage of the supply current generator can be lowered (for example, the supply current generator can be configured as a low breakdown voltage transistor). Can be). As a result, the circuit size can be reduced.

Preferably, the drive voltage generator further comprises a first differential amplifier circuit. The first differential amplifier circuit is connected between the first node existing in the first wiring and the first selector. The supply current generator includes first and second supply transistors, a second resistor, a second differential amplifier circuit, and first and second clamp transistors. The first supply transistor and the second resistor are connected in series between the first reference node and the second reference node. In the second differential amplifier circuit, one input terminal is connected to an interconnection node of a first supply transistor and a second resistor, the amplitude signal is received at the other input terminal, and an output terminal is connected to a gate of the first supply transistor. do. The second supply transistor, the first clamp transistor, and the second clamp transistor are connected in series between a second node present in the second wiring and the first reference node. The second supply transistor is connected between the first reference node and the first clamp transistor to receive a gate voltage generated at the gate of the first supply transistor. The first clamp transistor is connected between the first supply transistor and the second clamp transistor to receive the first bias voltage at the gate. The second clamp transistor is connected between the second node present in the second wiring and the first clamp transistor to receive the second bias voltage at the gate.

In the drive voltage generator, the breakdown voltage of the first and second supply transistors can be made lower than before. Therefore, since the manufacturing process deviation of a 1st supply transistor and a 2nd supply transistor can be reduced, the variation of the current characteristics of a 1st supply transistor and a 2nd supply transistor can be reduced. In addition, since the drain voltage fluctuation of each of the first and second supply transistors can be reduced, the influence of the drain voltage dependency can be alleviated. As a result, the driving voltage having the voltage value according to the amplitude information can be generated with high accuracy.

Preferably, the voltage value of the first bias voltage represents a value at which the gate-source voltage of the first clamp transistor is equal to the voltage value of the amplitude information.

Preferably, the voltage value of the second bias voltage is equal to the gate-source voltage of the second clamp transistor.

Preferably, the apparatus further includes a first differential amplifier circuit. The first differential amplifier circuit is connected between the first node existing in the first wiring and the first selector. The supply current generating unit includes first to fourth supply transistors, a second resistor, a second differential amplifier circuit, and first to third clamp transistors. The first supply transistor and the second resistor are connected in series between the first reference node and the second reference node. In the second differential amplifier circuit, one input terminal is connected to an interconnection node of the first supply transistor and the second resistor, and the output signal is connected to the gate of the first supply transistor, receiving the amplitude signal at the other input terminal. do. The second supply transistor, the first and second clamp transistors, and the third supply transistor are connected in series between the first reference node and the third reference node. The third clamp transistor and the fourth supply transistor are connected in series between the second node present in the second wiring and the third reference node. The second supply transistor is connected between the first reference node and the first clamp transistor to receive a gate voltage generated at the gate of the first supply transistor. The first clamp transistor is connected between the first supply transistor and the second clamp transistor to receive the first bias voltage at the gate. The second clamp transistor is connected between the first clamp transistor and the third supply transistor to receive a second bias voltage at the gate. The third supply transistor is connected between the second clamp transistor and the third reference node, and a gate is connected to the drain of the third supply transistor. The third clamp transistor is connected between the second node present in the second wiring and the fourth supply transistor to receive the third bias voltage at the gate. The fourth supply transistor is connected between the third clamp transistor and the third reference node to receive the gate voltage generated at the gate of the third supply transistor.

In the drive voltage generator, the breakdown voltage of the first to fourth supply transistors can be made lower than before. Therefore, the difference between the current value of the current flowing through the first supply transistor and the current value of the current flowing through the fourth supply transistor can be reduced.

Preferably, the gate-source voltage of the second clamp transistor is equal to the gate-source voltage of the third clamp transistor. The second and third bias voltages are equal to the gate-source voltage of the second clamp transistor or the gate-source voltage of the third clamp transistor.

Preferably, the drive voltage generation device further comprises a first differential amplifier circuit and a second differential amplifier circuit. The first differential amplifier circuit is connected between the first selector and the first switch. The second differential amplifier circuit is connected between the second selector and the fourth switch.

Preferably, the drive voltage generation device further comprises a first differential amplifier circuit and a second differential amplifier circuit. The first differential amplifier circuit is connected between the first node existing in the first wiring and the first selector. The second differential amplifier circuit is connected between the second node existing in the second wiring and the fourth switch.

According to yet another aspect of the present invention, the control method controls the driving voltage generating device. The drive voltage generator includes a first selector, a second selector, and first to sixth switch transistors. The first selector receives a plurality of first supply voltages and outputs any one of the first supply voltages. The second selector receives a plurality of second supply voltages and outputs any one of the second supply voltages. The first to fourth switches are connected in series between the first selector and the second selector. The fifth switch is connected between the first interconnect node of the first switch and the second switch and the first input node receiving the first specified voltage. The sixth switch is connected between the second interconnect node of the third switch and the fourth switch and the second input node receiving the second specified voltage. The first specified voltage supplied through the fifth switch has a lower impedance than the output of the second selector. The second specified voltage supplied through the sixth switch has a lower impedance than the output of the first selector. In the control method, steps A to D are executed. In step (A), the first, second and sixth switches are turned off, and the third, fourth and fifth switches are turned on. In step (B), the first, second and sixth switches are turned on, and the third, fourth and fifth switches are turned off. Process (C) is performed when switching from process (A) to process (B). In step (C), the third switch is turned off and the second switch is turned on. Next, the first and sixth switches are turned on and the fourth and fifth switches are turned off. Step (D) is executed when switching from step (B) to step (A). In step (D), the second switch is turned off and the third switch is turned on. Next, the fourth and fifth switches are turned on and the first and sixth switches are turned off.

In the control method of the drive voltage generator, in step A, the output of the second selector is supplied to the interconnect node (third interconnect node) of the second switch and the third switch. The first interconnect node is also supplied with a first specified voltage. In step (C), the first interconnect node is supplied with the first specified voltage, so that the potential of the first interconnect node is stabilized at the voltage value of the first specified voltage. On the other hand, in step (B), the output of the first selector is supplied to the third interconnect node. The second interconnect node is also supplied with a second specified voltage. In step (D), the second interconnect node is supplied with the second specified voltage, so that the potential of the second interconnect node is stabilized at the voltage value of the second specified voltage. Here, if the voltage value of the first specified voltage (second specified voltage) is set to an appropriate value, the potential difference between the input side and the output side in the first selection unit (second selection unit) can be made smaller than before. Therefore, the internal pressure of a 1st and 2nd selection part can be made low. As described above, since the breakdown voltage of each of the first and second selection units can be reduced, the circuit size of the driving voltage generator can be reduced.

The above and other objects and features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same code | symbol is attached | subjected to the same part or an equivalent part of drawing, and the description is not repeated.

(First embodiment)

The overall configuration of a drive voltage generator 1 according to the first embodiment of the present invention is shown in FIG. The apparatus 1 includes a timing controller 11, a VCOM voltage generator 12, an operational amplifier 13 for VCOM, a smoothing capacity C14, and an output terminal 15. This apparatus 1 controls the drive voltages VCOMH and VCOML for alternating-current driving (line inversion driving) of the liquid crystal display panel. In other words, the device 1 outputs one of the driving voltages VCOMH and VCOML to the counter electrode (not shown) of the liquid crystal display panel in accordance with the timing signal TIMING.

The timing controller 11 controls the voltage value of the drive voltage VCOMH output by the VCOM voltage generator 12 using the control signal Sa. In addition, the timing controller 11 controls the voltage value of the drive voltage VCOML output from the VCOM voltage generator 12 using the control signal Sb. The timing controller 11 also outputs the control signals S1 to S6 in accordance with the timing signal TIMING from the outside. The timing signal TIMING represents a timing for switching the driving voltage supplied to the counter electrode of the liquid crystal display panel from the driving voltage VCOMH to the driving voltage VCOML (or the driving voltage VCOML to the driving voltage VCOMH). .

The VCOM voltage generator 12 generates the drive voltages VCOMH and VCOML in accordance with the control signals Sa and Sb output from the timing controller 11. The VCOM voltage generator 12 outputs either of the drive voltages VCOMH and VCOML in accordance with the control signals S1 to S6 output from the timing controller 11.

The VCOM operational amplifier 13 outputs the drive voltages VCOMH and VCOML supplied by the VCOM voltage generator 12 to the output terminal 15.

The smoothing capacity C14 is configured to smooth the fluctuation of the output of the VCOM operational amplifier 13 and is provided between the node N14 and the ground node existing between the VCOM operational amplifier 13 and the output terminal 15. Is connected to.

The driving voltages VCOMH and VCOML output from the VCOM operational amplifier 13 are connected to the counter electrode of the liquid crystal display panel (here, the panel load C (LC) as a load capacitance of the liquid crystal display panel) through the output terminal 15. Is shown.

<Internal structure of the VCOM voltage generator 12>

The VCOM voltage generator 12 shown in FIG. 1 includes ladder resistors 101H and 101L, selectors 102H and 102L, and switch transistors SW1 to SW6.

The ladder resistor 101H is connected between the reference node N101H-1 receiving the reference voltage VREFH and the reference node N101H-2 receiving the reference voltage VSSH, and the plurality of supply voltages having different voltage values from each other. Create The selector 102H selects any one of the plurality of supply voltages generated by the ladder resistor 101H in accordance with the control signal Sa from the timing controller 11.

The ladder resistor 101L is connected between a reference node N101L-1 receiving the reference voltage VSSL and a reference node N101L-2 receiving the reference voltage VREFL, and supply voltages having different voltage values from each other. Create The selector 102L selects any one of the plurality of supply voltages generated by the ladder resistor 101L in accordance with the control signal Sb from the timing controller 11.

The switch transistors SW1 to SW4 are connected in series between the selector 102H and the selector 102L. The supply voltage selected by the selection unit 102H is supplied to the switch transistor SW1 as the driving voltage VCOMH. The supply voltage selected by the selection unit 102L is supplied to the switch transistor SW2 as the driving voltage VCOML. The switch transistor SW1 is connected between the selection unit 102H and the switch transistor SW3 to receive the control signal S1 from the timing controller 11 at the gate. The switch transistor SW3 is connected between the switch transistor SW1 and the switch transistor SW4 to receive the control signal S3 from the timing controller 11 at the gate. The switch transistor SW4 is connected between the switch transistor SW3 and the switch transistor SW2 to receive the control signal S4 from the timing controller 11 at the gate. The switch transistor SW2 is connected between the switch transistor SW4 and the selector 102L and receives the control signal S2 from the timing controller 11 at the gate.

The switch transistor SW5 is connected between the switch node SW1 and the interconnect node NH of the switch transistor SW3 and the specified voltage supply node N103H, so as to control the signal S5 from the timing controller 11. Receive at the gate. The specified voltage supply node N103H receives the specified voltage VSETH from the outside (for example, a power supply device). The switch transistor SW6 is connected between the switch node SW4 and the interconnect node NL of the switch transistor SW2 and the specified voltage supply node N103L to control the signal S6 from the timing controller 11. Receive at the gate. The specified voltage supply node N103L receives the specified voltage VSETL from the outside (for example, a power supply).

The switch transistors SW1 to SW6 are turned on when the control signals S1 to S6 are "H level", and are turned off when the control signals S1 to S6 are "L level".

Here, the voltage value of each reference voltage is

(Reference voltage VREFL) ≤ (reference voltages VSSH, VSSL) ≤ (reference voltage VREFH)

It shall be In addition, the voltage value of the specified voltage (VSETH, VSETL),

(Reference voltage VSSH) ≤ (prescribed voltage VSETH) ≤ (reference voltage VREFH)

(Reference voltage (VREFL)) ≤ (regulated voltage (VSETL)) ≤ (reference voltage (VSSL))

It shall be

<Configuration example of ladder resistor 101H and selector 102H>

An example of the configuration of the ladder resistor 101H and the selection unit 102H is shown in FIG. 2A. The ladder resistor 101H includes N resistors R111H-1 to R111H-N (N is a natural number). The resistors R111H-1 to R111H-N are connected in series between the reference node N101H-1 and the reference node N101H-2. N supply voltages VdivH1 to VdivHN are generated in each of the N taps TAPH-1 to TAPH-N of the ladder resistor 101H. The selector 102H includes N select transistors T112H-1 to T112H-N. The selection transistors T112H-1 to T112H-N are connected between the taps TAPH-1 to TAPH-N and the switch transistor SW1. In addition, the timing controller 11 applies a control signal Sa to any one of the selection transistors T112H-1 to T112H-N. The voltage value of the control signal Sa represents " reference voltage VREFH-reference voltage VSSH. &Quot; When any one of the selection transistors T112H-1 to T112H-N is turned on, any one of the N supply voltages VdivH1 to VdivHN is supplied to the switch transistor SW1 as the driving voltage VCOMH. In this way, the driving voltage VCOMH of the N gray level whose maximum value is the reference voltage VREFH is generated.

<Configuration example of the ladder resistor 101L and the selection unit 102L>

An example of the configuration of the ladder resistor 101L and the selector 102L is shown in FIG. 2B. The ladder resistor 101L includes N resistors R111L-1 to R111L-N. The resistors R111L-1 to R111L-N are connected in series between the reference node N101L-1 and the reference node N101L-2. N supply voltages VdivL1 to VdivLN are generated in each of the N taps TAPL-1 to TAPL-N of the ladder resistor 101L. The selector 102L includes N select transistors T112L-1 to T112L-N. The selection transistors T112L-1 to T112L-N are connected between the taps TAPL-1 to TAPL-N and the switch transistor SW2. In addition, the timing controller 11 applies the control signal Sb to any one of the selection transistors T112L-1 to T112L-N. The voltage value of the control signal Sb indicates " reference voltage VSSL-reference voltage VREFL. &Quot; When any one of the selection transistors T112L-1 to T112L-N is turned on, any one of the N supply voltages VdivL1 to VdivLN is supplied to the switch transistor SW2 as the driving voltage VCOML. In this way, the driving voltage VCOML of the N gray level having the lowest value is the reference voltage VREFL.

<Resistance value>

In general, in the drive voltage generation device, in order to reduce the current flowing through the ladder resistance, the resistance value of the ladder resistance has a relatively high resistance value. For example, the resistance value of the ladder resistor 101L represents about several hundreds of kΩ to several megohms. On the other hand, the on resistance of the switch transistor SW5 may be significantly smaller than the resistance value of the ladder resistor 101L. For example, the on resistance of the switch transistor SW5 represents about 50 kΩ. The ON resistance of the switch transistor SW6 is significantly smaller than the resistance value of the ladder resistor 101H, similarly to the case of the switch transistor SW5.

<Operation by the VCOM Voltage Generator 12>

Next, the operation by the VCOM voltage generation unit 12 shown in FIG. 1 will be described with reference to FIGS. 3 and 4. The voltage value of the reference voltage VREFH is "+ 5V", the voltage values of the reference voltages VSSH and VSSL are "0V", and the voltage value of the reference voltage VREFL is "-5V". The voltage value of the specified voltage VSETH is "+ 4V", and the voltage value of the specified voltage VSETL is "-4V". The selector 102H receives the control signal Sa to select a supply voltage indicating the voltage value "+ 5V", and the selector 102L receives the control signal Sb to supply the voltage value "-5V". Shall be selected. That is, it is assumed that the drive voltage VCOMH indicating the voltage value "+ 5V" is supplied to the node N102H, and the drive voltage VCOML indicating the voltage value "-5V" is supplied to the node N102L.

At the times t0 to t1, the timing controller 11 sets the control signals S1, S3, S6 to the "L level" and the control signals S2, S4, S5 to the "H level". Since the switch transistors SW2 and SW4 are on, the driving voltage VCOML (-5V) is supplied from the selection unit 102L to the node NC through the nodes N102L and NL. Therefore, the potentials of the nodes N102L, NL, and NC are all "-5V" (Figs. 4B and 4C). On the other hand, since the switch transistor SW5 is in the on state, the specified voltage VSETH is supplied from the specified voltage supply node N103H to the node NH. Therefore, the potential of the node NH becomes "+ 4V" (FIG. 4A). In addition, since the drive voltage VCOMH is supplied from the selector 102H to the node N102H, the potential of the node N102H becomes "+ 5V".

 At the time t1, the timing controller 11 sets the control signal S3 to "H level" and the control signal S4 to "L level". Since the switch transistor SW5 is in the on state and the switch transistor SW3 is in the on state, the node NC is connected to the specified voltage supply node N103H through the node NH. Therefore, the potential of the node NC varies from "-5V" to "+ 4V" (Fig. 4B). The potential of the node NH also changes. However, since the specified voltage VSETH supplied from the specified voltage supply node N103H to the node NH has a lower impedance than the drive voltage VCOML supplied from the selector 102L to the node NC, the node NH The variation in potential is less than the variation in node NC potential. That is, the potential of the node NH is stabilized at the voltage value (+ 4V) of the specified voltage VSETH (Fig. 4A). In addition, since the switch transistor SW1 remains off, the potential of the node N102H remains "+ 5V". On the other hand, since the switch transistor SW2 is on and the switch transistor SW4 is off, the driving voltage VCOML (-5V) is supplied from the selection unit 102L to the node NL through the node N101L. Therefore, the potentials of the nodes N102L and NL are all "-5V".

When the time t2 is reached, the timing control unit 11 sets the control signals S1 and S6 to the "H level" and the control signals S2 and S5 to the "L level". Since the switch transistor SW3 is in the on state and the switch transistor SW1 is in the on state, the selector 102H is connected to the node NC through the nodes N102H and NH. Therefore, the potentials of the nodes NH and NC all fluctuate from "+ 4V" to "+ 5V" (Figs. 4A and 4B). At this time, the driving voltage VCOMH supplied from the selector 102H to the node N102H has a higher impedance than the specified voltage VSETH supplied from the specified voltage supply node N103H to the node NH. The potential of N102H) may fluctuate. However, the potential of the node N102H does not become lower than the voltage value (+ 4V) of the specified voltage VSETH. On the other hand, since the switch transistor SW6 is turned on, the specified voltage supply node N103L is connected to the node NL. Therefore, the potential of the node NL varies from "-5V" to "-4V" (Fig. 4C). In addition, since the switch transistor SW4 is turned off, the potential of the node N102L remains "-5V".

 At the time t3, the timing controller 11 sets the control signal S3 to "L level" and the control signal S4 to "H level". Since the switch transistor SW6 is in the on state and the switch transistor SW4 is in the on state, the node NC is connected to the specified voltage supply node N103L through the node NL. Therefore, the potential of the node NC varies from "+ 5V" to "-4V" (Fig. 4B). The potential of the node NL also varies. However, since the specified voltage VSETL supplied from the specified voltage supply node N103L to the node NL has a lower impedance than the driving voltage VCOMH supplied from the selector 102H to the node NC, the node NL The variation in potential is less than the variation in node NC potential. That is, the potential of the node NL is stabilized at the voltage value (-4V) of the specified voltage VSETL (Fig. 4C). On the other hand, since the switch transistor SW1 is on and the switch transistor SW3 is off, the driving voltage VCOMH (+ 5V) is supplied from the selector 102H to the node NH through the node N102H. Therefore, the potentials of the nodes N102H and NH are both "+ 5V".

At the time t4, the timing controller 11 sets the control signals S1 and S6 to the "L level" and the control signals S2 and S5 to the "H level". Since the switch transistor SW4 is on and the switch transistor SW2 is on, the selector 102L is connected to the node NC through the nodes N102L and NL. Therefore, the potentials of the nodes NL and NC all fluctuate from "-4V" to "-5V" (Figs. 4B and 4C). At this time, the driving voltage VCOML supplied from the selector 102L to the node N102L has a higher impedance than the specified voltage VSETL supplied from the specified voltage supply node N103L to the node NL. The potential of N102L) may fluctuate. However, the potential of the node N102L does not become higher than the voltage value (−4V) of the specified voltage VSETL. On the other hand, since the switch transistor SW5 is turned on, the specified voltage supply node N103H is connected to the node NH. Therefore, the potential of the node NH changes from "+ 5V" to "+ 4V" (FIG. 4A). In addition, since the switch transistor SW3 is turned off, the potential of the node N102H remains "+ 5V".

At time t5, the same operation as that at time t1 is performed.

In this way, when the switch transistor SW3 is switched from off to on, the specified voltage VSETH having a low impedance is supplied from the specified voltage supply node N103H to the node NH, so that the potential of the node NH is regulated. It can be stabilized by the voltage value of (VSETH). In addition, when the switch transistor SW4 is switched from off to on, a low impedance specified voltage VSETL is supplied from the specified voltage supply node N103L to the node NH, so that the potential of the node NL is changed to the specified voltage ( It can be stabilized by the voltage value of VSETL).

The specified voltage (VSETH)

(Reference voltage VSSH) ≤ (prescribed voltage VSETH) ≤ (reference voltage VREFH)

Therefore, the potential difference between both ends of the selection transistor included in the selection unit 102H can be made smaller than "(reference voltage VREFH)-(reference voltage VREFL)".

Similarly, the specified voltage VSETL

(Reference voltage (VREFL)) ≤ (regulated voltage (VSETL)) ≤ (reference voltage (VSSL))

Therefore, the potential difference between both ends of the selection transistor included in the selection unit 102L can be made smaller than "(reference voltage VREFH)-(reference voltage VREFL)".

<Withstand voltage of transistor>

In the above operation, the potential difference between the node NH and the node NC and the potential difference between the node NL and the node NC are at most about 9V. On the other hand, the potential difference between the node N102H and the node NH, the potential difference between the node N102L and the node NL, the potential difference between the specified voltage supply node N103H and the node NH, and the specified voltage supply node N103L. The potential difference between and node NL is about 1V at maximum. Therefore, it is possible to lower the internal pressure of the switch transistors SW1, SW2, SW5, and SW6 with respect to the switch transistors SW3 and SW4 (the absolute maximum rating of the switch transistors SW1, SW2, SW5, and SW6 can be reduced). ).

In addition, since the potential of the node NH can be stabilized to "+ 5V", the absolute maximum rating of the selection transistor included in the selection unit 102H is 10V ((reference voltage VREFH)-(reference voltage VREFL)). It is not necessary to be larger than), but larger than 5V (voltage value of the control signal Sa). That is, the breakdown voltage of the selection transistor of the selection unit 102H can be lowered.

Similarly, since the potential of the node NL can be stabilized at " -5 V ", the absolute maximum rating of the selection transistor included in the selection section 102L is 10V ((reference voltage VREFH)-(reference voltage VREFL). It is not necessary to be larger than))), and may be larger than 5V (voltage value of the control signal Sb). That is, the breakdown voltage of the selection transistor of the selection unit 102L can be reduced.

<Effect>

As described above, compared with the conventional drive voltage generator shown in Fig. 12, in the drive voltage generator 1 according to the present embodiment, the selection transistors included in the selectors 102H and 102L are made low-voltage transistors. Can be. As a result, the circuit size can be reduced.

In addition, by lowering the selection transistors included in the selection sections 102H and 102L, the potential of the node NH (node NL) is reduced to the supply voltage selected by the selection section 102H (selection section 102L). The time required until the voltage stabilizes can be shortened. That is, the time required until the potential of the drive voltage VCOMH (drive voltage VCOML) is stabilized can be shortened.

(Second embodiment)

<Overall Configuration>

5 shows an overall configuration of a drive voltage generator 2 according to the second embodiment of the present invention. The apparatus 2 includes a timing control unit 11, an output terminal 15 and switch transistors SW1 to SW6 shown in FIG. 1, a VCOM voltage generator 22, an operational amplifier 23H for VCOMH, and a VCOML. The operational amplifier 23L and smoothing capacities C24H and C24L are provided.

The VCOM voltage generator 22 generates the drive voltages VCOMH and VCOML in accordance with the control signals Sa and Sb output from the timing controller 11.

The operational amplifier 23H for VCOMH outputs the drive voltage VCOMH generated by the VCOM voltage generator 22 to the switch transistor SW1. The operational amplifier 23L for VCOML outputs the drive voltage VCOML generated by the VCOM voltage generator 22 to the switch transistor SW2.

The smoothing capacity C24H is configured to smooth the output fluctuation of the VCOMH operational amplifier 23H, and is between the node N24H and the ground node existing between the VCOMH operational amplifier 23H and the switch transistor SW1. Is connected to. The smoothing capacity C24L is configured to smooth the output variation of the VCOML operational amplifier 23L, and is provided between the node N24L and the ground node existing between the VCOML operational amplifier 23L and the switch transistor SW2. Is connected to.

The switch transistors SW1 to SW4 are connected in series between the node N24H and the node N24L. The connection relationship between the switch transistors SW1 to SW6 is the same as in FIG.

The output terminal 15 is connected to the interconnect node NC of the switch transistor SW3 and the switch transistor SW4.

<Internal structure of the VCOM voltage generator 22>

The VCOM voltage generator 22 shown in FIG. 5 includes the ladder resistors 101H and 101L and the selectors 102H and 102L shown in FIG. 1. The connection relationship between the ladder resistor 101H and the selector 102H and the connection relationship between the ladder resistor 101L and the selector 102L are the same as in FIG. 1. The supply voltage selected by the selection unit 102H is supplied to the operational amplifier 23H for VCOMH as the drive voltage VCOMH. The supply voltage selected by the selection unit 102L is supplied to the operational amplifier 23L for VCOML as the driving voltage VCOML.

<Action>

The operation by the drive voltage generator 2 shown in FIG. 5 will be described.

First, the timing controller 11 outputs control signals Sa and Sb in the same manner as in the first embodiment.

Next, in the VCOM voltage generation section 22, the selection section 102H, as with the first embodiment, generates a plurality of ladder signals generated by the ladder resistor 101H in accordance with the control signal Sa from the timing control section 11. Select one of the supply voltages. The supply voltage selected by the selection unit 102H is output as the drive voltage VCOMH. The selector 102L selects any one of the plurality of supply voltages generated by the ladder resistor 101L in accordance with the control signal Sb from the timing controller 11, similarly to the first embodiment. . The supply voltage selected by the selector 102L is output as the drive voltage VCOML.

Next, the operational amplifier 23H for VCOMH outputs the drive voltage VCOMH supplied from the selection unit 102H to the switch transistor SW1. The VCOML operational amplifier 23L outputs the drive voltage VCOML supplied from the selector 102L to the switch transistor SW2.

Next, the switch transistors SW1 to SW6 operate in the same manner as in the first embodiment. Thus, the driving voltage VCOMH output from the VCOMH operational amplifier 23H to the switch transistor SW1 and the driving voltage VCOML output from the VCOML operational amplifier 23L to the switch transistor SW2 are alternately output terminals. Supplied to (15).

<Effect>

As described above, since the potential of the node N24H can be stabilized at " + 5V ", the operational amplifier 23H for VCOMH can be configured as a low breakdown voltage transistor. In addition, since the potential of the node N24L can be stabilized at " -5 V ", the operational amplifier 23L for VCOML can be constituted by a low withstand voltage transistor. As a result, the circuit size can be reduced. In addition, the driving capability (response speed) of the operational amplifier 23H for VCOMH and the operational amplifier 23L for VCOML can be improved.

(Third embodiment)

<Overall Configuration>

6 shows an overall configuration of a drive voltage generator 3 according to the third embodiment of the present invention. This apparatus 3 is provided with the timing control part 31 and the VCOM voltage generation part 32 instead of the timing control part 11 and the VCOM voltage generation part 22 shown in FIG. The other structure is the same as that of FIG.

The timing controller 31 controls the voltage values of the drive voltages VCOMH and VCOML output by the VCOM voltage generator 32 using the control signal Sa and the amplitude information Sc. The amplitude information Sc is a voltage (amplitude voltage VREFM) having a voltage value corresponding to the potential difference between the drive voltage VCOMH and the drive voltage VCOML to be generated by the VCOM voltage generator 32. The timing controller 31 also outputs the control signals S1 to S6 in accordance with the timing signal TIMING from the outside.

The VCOM voltage generator 32 generates the drive voltages VCOMH and VCOML in accordance with the control signal Sa and the amplitude information Sc output from the timing controller 31. The VCOM voltage generator 32 outputs either one of the driving voltages VCOMH and VCOML in accordance with the control signals S1 to S6 output from the timing controller 31.

<Internal structure of the VCOM voltage generator 32>

The internal structure of the VCOM voltage generation part 32 shown in FIG. 6 is shown in FIG. The VCOM voltage generation unit 32 replaces the ladder resistor 101L and the selection unit 102L shown in FIG. 1 with the operational amplifier 302 for selection, the supply transistors T303-1 to T303-4, and a resistor. R304 and R305, clamp transistors T311-1 to T311-3, and a diode 312-D are provided. The driving voltage generation device 3 also includes an operational amplifier 301 for supply. The rest of the configuration is the same as that of the VCOM voltage generator 12 shown in FIG.

The supply operational amplifier 301 is a voltage follower circuit and is connected between the selection unit 102H and the switch transistor SW1.

The selection operational amplifier 302, the supply transistor T303-1, and the resistor R304 constitute a voltage current conversion circuit. The selecting operational amplifier 302 has an output terminal connected to the gate of the supply transistor T303-1, and one input terminal is connected to an interconnect node N303 of the supply transistor T303-1 and the resistor R304. And receives amplitude information Sc (amplitude voltage VREFM) from the timing controller 31 at the other input terminal. The supply transistor T303-1 and the resistor R304 are connected in series between a reference node N301H-1 receiving the reference voltage VREFH and a reference node N301-2 receiving the reference voltage VSS. .

The supply transistor T303-2, the clamp transistors T311-1 and T311-2, and the supply transistor T303-3 include the reference node N301-3 and the reference voltage receiving the reference voltage VREFH. It is connected in series between the reference nodes N301-4 which receive (VREFL). The supply transistor T303-2 is connected between the reference node N301-3 and the clamp transistor T311-1, and a gate is connected to the gate of the supply transistor T303-1. The clamp transistor T311-1 is connected between the supply transistor T303-2 and the clamp transistor T311-2, and is gated to the bias voltage supply node N311-1 receiving the bias voltage Vbias1. Is connected. The clamp transistor T311-2 is connected between the clamp transistor T311-1 and the supply transistor T303-3, and is gated to the bias voltage supply node N311-2 receiving the bias voltage Vbias2. Is connected. The supply transistor T303-3 is connected between the clamp transistor T311-2 and the reference node N301-4, and a gate is connected to the drain of the supply transistor T303-3.

The resistor R305, the clamp transistor T311-3, and the supply transistor T303-4 include the node N305H existing between the supply operational amplifier 301 and the switch transistor SW1 and the reference voltage. VREFL) is connected in series between the reference nodes N301-5. The resistor R305 is connected between the node N305H and the clamp transistor T311-3. The clamp transistor T311-3 is connected between the resistor R305 and the supply transistor T303-4, and a gate is connected to a bias voltage supply node N311-3 that receives the bias voltage Vbias3. The supply transistor T303-4 is connected between the clamp transistor T311-3 and the reference node N301-5 which receives the reference voltage VREFL, and the gate thereof is a gate of the supply transistor T303-3. Is connected to.

The switch transistors SW1 to SW4 are connected in series between the node N305H and the node N305L. The node N305L is an interconnect node of the resistor R305 and the clamp transistor T311-3. The connection relationship between the switch transistors SW1 to SW6 is the same as in FIG.

The diode 312-D is a clamp circuit configured to limit the potential of the node N305H to be higher than the potential (reference voltage VSS) of the reference node N312-2, and the supply operational amplifier 301 and The node N312-1 existing between the switch transistor SW1 is connected between the node N312-2 receiving the reference voltage VSS.

Here, the voltage value of the reference voltage VSS and the voltage value of the amplitude information Sc (amplitude voltage VREFM) are

(Reference voltage VREFL) ≤ (reference voltage VSS) ≤ (reference voltage VREFH)

(Reference voltage (VSS)) ≤ (amplitude voltage (VREFM)) ≤ (reference voltage (VREFH))

It shall be

<Action>

Next, the operation by the VCOM voltage generator 32 shown in FIG. 7 will be described. Here, the voltage value of the reference voltage VREFH is "+ 5V", the voltage values of the reference voltages VSSH and VSS are "0V", and the voltage value of the reference voltage VREFL is "-5V".

The selector 102H selects any one of the plurality of supply voltages generated by the ladder resistor 101H in accordance with the control signal Sa from the timing controller 31. The supply operational amplifier 301 outputs the drive voltage VCOMH selected by the selection unit 102H to the switch transistor SW1.

On the other hand, the selection operational amplifier 302 receives the amplitude information Sc from the timing controller 31. As the supply transistor T303-1 and the resistor R304, a supply current IrefM having a current value corresponding to the voltage value of the amplitude information Sc (amplitude voltage VREFM) flows. This supply current IrefM satisfies Equation 1 below.

(Supply current (IrefM)) = (amplitude voltage (VREFM) / (resistance (R304))

Next, the supply transistor T303-2 receives the gate voltage generated at the gate of the supply transistor T303-1 at the gate. Thus, the supply current IrefM flows through the supply transistor T303-2, the clamp transistors T311-1 and T311-2, and the supply transistor T303-3.

Next, the supply current IrefM flowing through the supply transistor T303-3 flows through the supply transistor T303-4 by the current mirror circuits constituted by the supply transistors T303-3 and T303-4. As a result, the driving voltage VCOML is generated at the node N305L. This driving voltage VCOML satisfies Equation 2 below.

(Drive voltage (VCOML)) = (Drive voltage (VCOMH))-(Supply current (IrefM)) x (resistance (R305))

From the equations (1) and (2), the voltage value of VCOML before driving generated at the node N305L is expressed by the following equation (3).

(Drive voltage (VCOML)) = (Drive voltage (VCOMH))-(Amplitude voltage (VREFM) x (resistance (R305)) / (resistance (R304))

As such, the driving voltage VCOMH according to the control signal Sa is supplied from the operational amplifier 301 for supply to the switch transistor SW1 and the driving voltage VCOML according to the control signal Sa and amplitude information Sc. ) Is supplied to the switch transistor SW2.

Next, the switch transistors SW1 to SW6 operate in the same manner as in the first embodiment. Thus, the driving voltage VCOMH output from the supply operational amplifier 301 to the node N305H and the driving voltage VCOML generated at the node N305L are alternately transferred to the operational amplifier 13 for the VCOM (see FIG. 6). Is output.

<Operation of Clamp Transistor>

By configuring the clamp transistor T311-1, the drain voltage of the supply transistor T303-2 can be adjusted. That is, the drain voltage of the supply transistor T303-2 can be set to "(bias voltage Vias) + (gate-source voltage of transistor T311-1)". As a result, the voltage value of the drain voltage of the supply transistor T303-2 can be made higher than the voltage value of the reference voltage VREFL. In addition, since the drain voltage variation of the supply transistor T303-2 can be made smaller than before, the influence of the drain voltage dependency can be alleviated.

Here, the bias voltage Vbias1 represents " 0 V ", and the gate-source voltage of the clamp transistor T311-1 is preferably equal to or substantially equivalent to the " amplitude voltage VREFM ". In this case, since the drain voltage of the supply transistor T303-2 can be made equal to the drain voltage of the supply transistor T303-1, the influence by the drain voltage dependency can be further alleviated.

Further, by configuring the clamp transistors T311-2 and T311-3, the drain voltages of the supply transistors T303-3 and T303-4 can be adjusted. That is, the drain voltage of the supply transistor T303-3 does not become higher than "(bias voltage Vias2)-(gate-source voltage of the transistor T311-2)", and the supply transistor T303- The drain voltage of 4) does not become higher than "(bias voltage Vias3)-(gate-source voltage of transistor T311-3)". Therefore, the drain voltages of the supply transistors T303-3 and T303-4 can be lower than the reference voltage VREFH. Like the supply transistor T303-2, the influence of the drain voltage dependency of the supply transistors T303-3 and T303-4 can be alleviated.

Here, the gate-source voltage of the clamp transistor T311-3 is equal to or nearly equal to the gate-source voltage of the clamp transistor T311-2, and the bias voltages Vbias2 and Vbias3 are " clamp " It is preferable that the gate-to-source voltage of the transistor T311-2 (T311-3) is equal to or nearly equal to. In this way, it is possible to prevent the drain voltages of the supply transistors T303-3 and T303-4 from being higher than " 0V. &Quot;

<Effect>

As described above, since the switches SW1 to SW6 are properly operated, the potential of the node N305L can be stabilized at " -5 V ", so that the potential difference between both ends of the supply transistor T303-4 is " (reference voltage VREFH). )-(Reference voltage VREFL) ". Further, the potential difference between both ends of each of the supply transistors T303-2 and T303-3 can be made smaller than "(reference voltage VREFH)-(reference voltage VREFL)". Further, the potential difference between both ends of each of the clamp transistors T311-1 to T311-3 can also be made smaller than "(reference voltage VREFH)-(reference voltage VREFL)". As a result, the breakdown voltage of the supply transistors T303-1 to T303-4 can be lowered as compared with the conventional drive voltage generator shown in Fig. 13, so that the circuit size can be reduced.

In addition, by reducing the breakdown voltage of the supply transistors T303-1 to T303-4 and the clamp transistors T311-1 to T311-3, the variation in the manufacturing process of each transistor can be reduced. Therefore, variations in the current characteristics of the current mirror circuit constituted by the supply transistors T303-1 and T303-2 and the current mirror circuit constituted by the supply transistors T303-3 and T303-4 can be reduced. In addition, the influence of the drain voltage dependence of the supply transistors T303-1 to T303-4 and the clamp transistors T311-1 to T311-3 can be alleviated. Thereby, the driving voltage VCOML having the voltage value corresponding to the control signal Sa and the amplitude information Sc can be generated with high precision.

The voltage value of the bias voltage Vbias1 is such that the clamp transistor T311-1 and the supply transistor T303-2 operate in a saturation region, and the gate-source voltage of the clamp transistor T311-1 ( Vgs), the drain-source voltage Vds, and the backgate-source voltage Vbs are each less than or equal to the absolute maximum rating of the clamp transistor T311-1, and the supply transistor T303-2. The gate-source voltage Vgs, the drain-source voltage Vds, and the backgate-source voltage Vbs may each be a value which is equal to or less than the absolute maximum rating of the supply transistor T303-2. In this manner, the clamp transistor T311-1 and the supply transistor T303-2 do not have to be destroyed by the bias voltage Vbias1.

The voltage value of the bias voltage Vbias2 is such that the clamp transistor T311-2 and the supply transistor T303-3 operate in a saturation region, and the gate-source voltage of the clamp transistor T311-2 ( Vgs), the drain-source voltage Vds, and the backgate-source voltage Vbs are each less than or equal to the absolute maximum rating of the clamp transistor T311-2, and the supply transistor T303-3 The gate-source voltage Vgs, the drain-source voltage Vds, and the backgate-source voltage Vbs may each be a value which is equal to or less than the absolute maximum rating of the supply transistor T303-3.

In addition, the voltage value of the bias voltage Vbias3 is such that the clamp transistor T311-3 and the supply transistor T303-4 operate in a saturation region, and the gate-source voltage of the clamp transistor T311-3 ( Vgs), the drain-source voltage Vds, and the backgate-source voltage Vbs are each less than or equal to the absolute maximum rating of the clamp transistor T311-3, and the supply transistor T303-4. The gate-source voltage Vgs, the drain-source voltage Vds, and the backgate-source voltage Vbs may each be a value which is equal to or less than the absolute maximum rating of the supply transistor T303-4.

Here, similar effects can be obtained by using the transistor 312-N shown in FIG. 8A or the transistor 312-P shown in FIG. 8B instead of the diode 312-D. .

In addition, between the supply transistor T303-2 and the supply transistor T303-3, and between the resistor R305 and the supply transistor T303-4 in accordance with the voltage values of the reference voltages VREFH and VREFL. You may add a clamp transistor again. In this way, even when the potential difference between the reference voltage VREFH and the reference voltage VREFL is large, it is possible to make the supply transistor and the clamp transistor low voltage.

In the present embodiment, instead of the ladder resistor 101L and the selector 102L, a supply current generator (selective operational amplifier 302, resistors R304 and R305) and supply transistors T303-1 to T303-4 Clamp transistors T311-1 to T311-3 are used, but this supply current generator can be used in place of the ladder resistor 101H and the selector 102H. In this case, processing such as replacing a P-channel transistor (supply transistor (T303-1, etc.)) with an N-channel transistor, and replacing the N-channel transistor (supply transistor (T303-3, etc.)) with a P-channel transistor is performed. Just do it.

(Example 4)

<Overall Configuration>

The drive voltage generator 4 according to the fourth embodiment of the present invention includes the VCOM voltage generator 42 shown in FIG. 9 instead of the VCOM voltage generator 32 shown in FIG. The other structure is the same as that of FIG. Here, the timing control part 31 controls the voltage value of the drive voltages VCOMH and VCOML which the VCOM voltage generation part 42 outputs using the control signal Sb and amplitude information Sc.

<Internal Configuration of VCOM Voltage Generator 42>

The VCOM voltage generator 42 shown in FIG. 9 replaces the ladder resistor 101H and the selector 102H shown in FIG. 1 with the operational operational amplifier 301 shown in FIG. 7 and the operational operational amplifier 302 for selection. And supply transistors T303-1 and T303-2, clamp transistors T311-1 and T311-2, resistors R304 and R305, and a diode 312-D. The rest of the configuration is the same as that of the VCOM voltage generator 12 shown in FIG.

The supply operational amplifier 301 is connected between the selection unit 102L and the switch transistor SW2.

The connection relationship between the selection operational amplifier 302, the supply transistors T303-1 and T303-2, the resistor R304, and the clamp transistors T311-1 and T311-2 is the same as in FIG. The supply transistor T303-2, the clamp transistors T311-1 and T311-2, and the resistor R305 are connected in series between the reference node N301-3 and the node N405L. The node N405L is present between the operational operational amplifier 301 and the switch transistor SW2. The resistor R305 is connected between the clamp transistor T311-2 and the node N405L.

The diode 312 -D is connected between the node N412-1 existing between the supply operational amplifier 301 and the switch transistor SW2 and the node N412-2 receiving the reference voltage VSS. .

The switch transistors SW1 to SW4 are connected between the clamp transistor T311-2 and the interconnect node N405H of the resistor R305 and the node N405L.

The connection relationship between the switch transistors SW1 to SW6 is the same as in FIG.

<Action>

Next, the operation by the VCOM voltage generator 42 shown in FIG. 9 will be described.

The selector 102L selects any one of the plurality of supply voltages generated by the ladder resistor 101L in accordance with the control signal Sb from the timing controller 31. The supply operational amplifier 301 outputs the drive voltage VCOML selected by the selector 102L to the switch transistor SW2.

On the other hand, the selection operational amplifier 302, the supply transistors T303-1 and T303-2, and the clamp transistors T311-1 and T311-2 perform operations similar to those of the third embodiment. Therefore, the voltage value of the driving voltage VCOMH generated at the node N405H is expressed by Equation (4).

(Driving voltage (VCOMH)) = (driving voltage (VCOML) + (amplitude voltage (VREFM)) x (resistance (R305)) / (resistance (R305))

As such, the driving voltage VCOMH according to the control signal Sb and the amplitude information Sc is supplied to the switch transistor SW1, and the driving voltage VCOML according to the control signal Sb is supplied to the operational amplifier 301. ) Is supplied to the switch transistor SW2.

Next, the switch transistors SW1 to SW6 operate in the same manner as in the first embodiment. Thus, the driving voltage VCOMH generated at the node N405H and the driving voltage VCOML output from the supply operational amplifier 301 to the node N405L are alternately transferred to the operational amplifier 13 for the VCOM (see FIG. 6). Is output.

<Effect>

As described above, since the switch transistors SW1 to SW6 operate properly, the potential of the node N405H can be stabilized at " + 5V, " )-(Reference voltage VREFL) ". The potential difference between both ends of each of the clamp transistors T311-1 and T311-2 can also be made smaller than "(reference voltage VREFH)-(reference voltage VREFL)". As a result, the breakdown voltage of the supply transistors T303-1 and T303-2 can be lowered as compared with the conventional drive voltage generator shown in Fig. 13, so that the circuit size can be reduced.

In addition, since variations in the manufacturing process of the supply transistor T303-1 can be reduced, variations in the current characteristics of the supply transistor T303-1 can be reduced. In addition, similar to the supply transistor T303-1, the current characteristic variation of the supply transistor T303-2 can also be reduced. As a result, the driving voltages VCOMH and VCOML corresponding to the control signal Sb and the amplitude information Sc can be generated with high accuracy.

The same effect can be obtained by using the transistor 312-N shown in FIG. 8A or the transistor 312-P shown in FIG. 8B instead of the diode 312-D. .

(Example 5)

<Overall Configuration>

10 shows an overall configuration of a drive voltage generator 5 according to the fifth embodiment of the present invention. This apparatus 5 is provided with the VCOM voltage generation part 52 and the timing control part 31 shown in FIG. 6 instead of the timing control part 11 and the VCOM voltage generation part 22 shown in FIG. In addition, the drive voltage generator 5 includes a diode 312 -D shown in FIG. 7. The other structure is the same as that of FIG. The VCOM voltage generation unit 52 generates the driving voltages VCOMH and VCOML in accordance with the control signal Sa and the amplitude information Sc from the timing controller 31. The diode 312-D is connected between the node N512-1 existing between the operational amplifier 23H for VCOMH and the switch transistor SW1 and the reference node N512-2 receiving the reference voltage VSS. do.

<Internal structure of the VCOM voltage generator 52>

The VCOM voltage generator 52 shown in FIG. 10 replaces the ladder resistor 101L and the selector 102L shown in FIG. 5 with the operational op amp 302 shown in FIG. 7 and the supply transistor T303-1. T303-4, resistors R304 and R305, and clamp transistors T311-1 to T311-3. The other structure is the same as that of FIG.

The connection relationship between the selection operational amplifier 302, the supply transistors T303-1 to T303-4, the resistor R304, and the clamp transistors T311-1 to T311-3 is the same as in FIG. 7. Among them, the resistor R305, the clamp transistor T311-3, and the supply transistor T303-4 include the node N505H existing between the operational amplifier 23H for the VCOMH and the switch transistor SW1. It is connected in series between the reference nodes N301-5. The interconnect node N305L of the resistor R305 and the clamp transistor T311-3 is connected to the operational amplifier 23L for VCOML.

<Action>

Next, the operation by the VCOM voltage generation unit 52 shown in FIG. 10 will be described.

First, the selector 102H selects any one of the plurality of supply voltages generated by the ladder resistor 101H similarly to the second embodiment. Next, the operational amplifier 23H for VCOMH outputs the supply voltage selected by the selection unit 102H as the drive voltage VCOMH.

On the other hand, the selection operational amplifier 302, the supply transistors T303-1 to T303-4, the resistors R304 and R305, and the clamp transistors T311-1 to T311-3 operate in the third embodiment. Do the same as Therefore, the driving voltage VCOML is generated at the node N305L. Next, the VCOML operational amplifier 23L outputs the drive voltage VCOML generated at the node N305L to the switch transistor SW2.

Next, the switch transistors SW1 to SW6 operate in the same manner as in the second embodiment. Thus, the driving voltage VCOMH output from the VCOMH operational amplifier 23H to the switch transistor SW1 and the driving voltage VCOML output from the VCOML operational amplifier 23L to the switch transistor SW2 are alternately output terminals. Is outputted to (15).

<Effect>

As described above, since the potential of the node N24H can be stabilized at " + 5V ", the operational amplifier 23H for VCOMH can be configured as a low breakdown voltage transistor. In addition, since the potential of the node N24L can be stabilized at " -5 V ", the operational amplifier 23L for VCOML can be constituted by a low withstand transistor. As a result, the circuit size can be reduced. In addition, the driving capability (response speed) of the operational amplifier 23H for VCOMH and the operational amplifier 23L for VCOML can be increased.

(Example 6)

<Overall Configuration>

11 shows an overall configuration of a drive voltage generator 6 according to the sixth embodiment of the present invention. This apparatus 6 is provided with the timing control part 61 and the VCOM voltage generation part 62 instead of the timing control part 11 and the VCOM voltage generation part 22 shown in FIG. The drive voltage generation device 6 also includes a diode 312-D shown in FIG. The other structure is the same as that of FIG. The timing controller 61 controls the voltage values of the drive voltages VCOMH and VCOML output by the VCOM voltage generator 62 using the control signal Sb and the amplitude information Sc. The timing controller 61 outputs the control signals S1 to S6 in accordance with the timing signal TIMING from the outside. The VCOM voltage generator 62 generates the drive voltages VCOMH and VCOML in accordance with the control signal Sb and the amplitude information Sc from the timing controller 61. The diode 312-D is connected between the node N612-1 existing between the operational amplifier 23L for VCOML and the switch transistor SW2 and the reference node N612-2 which receives the reference voltage VSS. .

<Internal Configuration of VCOM Voltage Generator 62>

The VCOM voltage generator 62 shown in FIG. 11 replaces the ladder resistor 101H and the selector 102H shown in FIG. 5 with the selection operational amplifier 302 shown in FIG. 9 and the supply transistor T303-1. And T303-2, resistors R304 and R305, and clamp transistors T311-1 and T311-2. The other structure is the same as that of FIG.

The connection relationship between the selection operational amplifier 302, the supply transistors T303-1 and T303-2, the resistor R304, and the clamp transistors T311-1 and T311-2 is the same as in FIG. Supply transistor T303-2, clamp transistors T311-1, T311-2, and resistor R305 are nodes N605L existing between VCOML operational amplifier 23L and switch transistor SW2. And a reference node N301-3 are connected in series. The interconnect node N405H of the clamp transistor T311-2 and the resistor R305 is connected to the operational amplifier 23H for VCOMH.

<Action>

The operation by the VCOM voltage generator 62 shown in FIG. 11 will be described.

First, the selector 102L selects any one of the plurality of supply voltages generated by the ladder resistor 101L similarly to the second embodiment. The operational amplifier 23L for VCOML outputs the supply voltage selected by the selection unit 102L as the driving voltage VCOML.

On the other hand, the selection operational amplifier 302, the supply transistors T303-1 and T303-2, the resistors R304 and R305, and the clamp transistors T311-1 and T311-2 are different from those in the fourth embodiment. Do the same. Therefore, the driving voltage VCOMH is generated at the node N405H. Next, the VCOMH operational amplifier 23H outputs the drive voltage VCOMH generated at the node N405H to the switch transistor SW1.

Next, the switch transistors SW1 to SW6 operate in the same manner as in the second embodiment. Thus, the driving voltage VCOMH output from the VCOMH operational amplifier 23H to the switch transistor SW1 and the driving voltage VCOML output from the VCOML operational amplifier 23L to the switch transistor SW2 are alternately output terminals. Is outputted to (15).

<Effect>

As described above, the VCOMH operational amplifier 23H and the VCOML operational amplifier 23L can be configured as low-voltage transistors, so that the circuit size can be reduced. In addition, the driving capability (response speed) of the operational amplifier 23H for VCOMH and the operational amplifier 23L for VCOML can be improved.

In addition, although the specific numerical value was mentioned as the example and demonstrated in the Example of this invention above, it is not necessarily limited to this specific example and may be another numerical value.

As described above, the potential difference between the input side and the output side in the first selector (second selector) can be made smaller than before. Therefore, the internal pressures of the first and second selection portions can be lowered. As described above, since the breakdown voltage of each of the first and second selection units can be reduced, the circuit size of the driving voltage generator can be reduced.

The drive voltage generation device of the present invention can reduce the circuit size, and thus is useful as a drive voltage generation device or the like for alternatingly driving liquid crystal display panels such as mobile phones.

Claims (15)

A first selector which receives a plurality of first supply voltages and outputs any one of the first supply voltages; A second selector which receives a plurality of second supply voltages and outputs any one of the second supply voltages; First to fourth switches connected in series between the first selector and the second selector; A first specified voltage supply unit supplying a first specified voltage to a first interconnect node of the first switch and the second switch; A second specified voltage supply unit for supplying a second specified voltage to a second interconnection node of the third switch and the fourth switch, The first switch, Connected between the first selector and the second switch, The second switch, Connected between the first switch and the third switch, The third switch, Connected between the second switch and the fourth switch, The fourth switch, Connected between the third switch and the second selector, The first specified voltage supply unit, When the first switch is in the on state, the first specified voltage is not supplied. The second specified voltage supply unit, When the fourth switch is in the on state, the second prescribed voltage is not supplied. The output of the first specified voltage supply unit has a lower impedance than the output of the second select unit, And the output of the second specified voltage supply unit has a lower impedance than the output of the first selector. The method of claim 1, The driving voltage generating device is further A first connection node connected in series between a first reference node receiving a first reference voltage and a second reference node receiving a second reference voltage to generate N first supply voltages having different voltage levels from each other (N is a natural number); Ladder resistance, A second reference voltage connected in series between a third reference node receiving a third reference voltage and a fourth reference node receiving a fourth reference voltage, and generating second M supply voltages having different voltage levels from each other (M is a natural number); With ladder resistance, The first selection unit, Outputs any one of the N first supply voltages generated by the first ladder resistor, The second selection unit, Outputs any one of the M second supply voltages generated by the second ladder resistors, The first specified voltage supply unit, A fifth switch connected between the first input node receiving the first specified voltage and the first interconnect node; The second specified voltage supply unit, A sixth switch connected between the second input node receiving the second specified voltage and the second interconnect node; The fifth switch, When the first switch is in the on state, it is turned off, The sixth switch, And the fourth switch is turned off when the fourth switch is turned on. The method of claim 2, The on resistance of the fifth switch is smaller than the second ladder resistance, The on-resistance of the sixth switch, characterized in that less than the first ladder resistance drive voltage generator. The method of claim 2, The first reference voltage is higher than the second reference voltage, The third reference voltage is higher than the fourth reference voltage, The first specified voltage is, (Second reference voltage) ≤ (first specified voltage) ≤ (first reference voltage), The second specified voltage is, And a fourth reference voltage ≤ (second specified voltage) ≤ (third reference voltage). The method of claim 2, The first ladder resistor includes N first taps for outputting the N supply voltages, The second ladder resistor includes M second taps for outputting the M supply voltages, The first selection unit, N first selection transistors corresponding to N first taps included in the first ladder resistor, The second selection unit, M second selection transistors corresponding to M second taps included in the second ladder resistor, Each of the N first select transistors Connected between a corresponding first tap and the first switch transistor, Each of the M second select transistors And a corresponding second tap and the second switch transistor are connected to each other. The method of claim 2, The driving voltage generator, Further comprising a control unit for controlling the first to sixth switch transistor, The control unit, Have first to fourth modes, In the first mode, The first, second, and sixth switch transistors are turned off, The third, fourth, and fifth switch transistors are turned on, In the second mode, The first, third, and sixth switch transistors are turned off, The second, fourth, and fifth switch transistors are turned on, In the third mode, The first, second, and sixth switch transistors are turned on, The third, fourth, and fifth switch transistors are turned off, In the fourth mode, The first, third, and sixth switch transistors are turned on, And the second, fourth, and fifth switch transistors are turned off. A first selector which receives a plurality of first supply voltages and outputs any one of the first supply voltages; A supply current generator for generating a supply current having a current value corresponding to an amplitude signal representing a plurality of potential differences; First to fourth switches connected in series between the first selector and the supply current generator; First wiring connecting the first selection unit and the first switch; A second wiring connecting the supply current generator and the fourth switch; A first resistor connected between the first node present in the first wiring and the second node present in the second wiring; A clamp circuit connected to the first wiring, for limiting the potential of the first wiring within a predetermined range; A first specified voltage supply unit for outputting a first specified voltage to the first interconnect node of the first switch and the second switch; A second specified voltage supply unit configured to output a second specified voltage to the second interconnect node of the third switch and the fourth switch, The first switch, Connected between the first selector and the second switch, The second switch, Connected between the first switch and the third switch, The third switch, Connected between the second switch and the fourth switch, The fourth switch, Connected between the third switch and the supply current generating unit; The first specified voltage supply unit, When the first switch is in the on state, the first specified voltage is not output. The second specified voltage supply unit, When the fourth switch is in the on state, the second specified voltage is not output. The output of the first specified voltage supply unit has a lower impedance than the output of the supply current generator, And an output of the second specified voltage supply unit has an impedance lower than that of the first selector. The method of claim 7, wherein A first differential amplifier circuit further connected between the first node existing in the first wiring and the first selector, The supply current generating unit, A first supply transistor and a second resistor connected in series between the first reference node and the second reference node; A second differential having one input terminal connected to an interconnect node of the first supply transistor and the second resistor, receiving the amplitude signal at the other input terminal, and an output terminal connected to a gate of the first supply transistor; Amplification circuit, A second supply transistor, a first clamp transistor, and a second clamp transistor connected in series between a second node existing in the second wiring and the first reference node, The second supply transistor, Is connected between the first reference node and the first clamp transistor to receive a gate voltage generated at the gate of the first supply transistor, The first clamp transistor, Connected between the first supply transistor and the second clamp transistor to receive a first bias voltage at a gate; The second clamp transistor, And a second bias voltage applied to the gate between the second node existing in the second wiring and the first clamp transistor. The method of claim 8, The voltage value of the first bias voltage is And a gate-source voltage of the first clamp transistor is equal to a voltage value of the amplitude information. The method of claim 8, The voltage value of the second bias voltage is And a gate-source voltage of the second clamp transistor. The method of claim 7, wherein A first differential amplifier circuit further connected between the first node existing in the first wiring and the first selector, The supply current generating unit, A first supply transistor and a second resistor connected in series between the first reference node and the second reference node; A second differential having one input terminal connected to an interconnect node of the first supply transistor and the second resistor, receiving the amplitude signal at the other input terminal, and an output terminal connected to a gate of the first supply transistor; Amplification circuit, A second supply transistor, a first and second clamp transistor, and a third supply transistor connected in series between the first reference node and a third reference node; A third clamp transistor and a fourth supply transistor connected in series between a second node existing in the second wiring and the third reference node, The second supply transistor, Is connected between the first reference node and the first clamp transistor to receive a gate voltage generated at the gate of the first supply transistor, The first clamp transistor, Connected between the first supply transistor and the second clamp transistor to receive a first bias voltage at a gate; The second clamp transistor, Connected between the first clamp transistor and the third supply transistor to receive a second bias voltage at a gate; The third supply transistor, Connected between the second clamp transistor and the third reference node, a gate is connected to the drain of the third supply transistor, The third clamp transistor, Is connected between the second node present in the second wiring and the fourth supply transistor to receive a third bias voltage at the gate, The fourth supply transistor, And a gate voltage connected between the third clamp transistor and the third reference node to receive a gate voltage generated at the gate of the third supply transistor. The method of claim 11, The gate-source voltage of the second clamp transistor is equal to the gate-source voltage of the third clamp transistor, The second and third bias voltages, And a gate-source voltage of the second clamp transistor or a gate-source voltage of the third clamp transistor. The method of claim 1, A first differential amplifier circuit connected between the first selector and the first switch; And a second differential amplifier circuit connected between the second selector and the fourth switch. The method of claim 8, A first differential amplifier circuit connected between the first node existing in the first wiring and the first selector; And a second differential amplifier circuit connected between the second node existing in the second wiring and the fourth switch. A first selector which receives a plurality of first supply voltages and outputs any one of the first supply voltages; A second selector which receives a plurality of second supply voltages and outputs any one of the second supply voltages; First to fourth switches connected in series between the first selector and the second selector; A fifth switch connected between the first interconnect node of the first switch and the second switch and a first input node receiving a first specified voltage; And a sixth switch connected between the third switch and a second interconnect node of the fourth switch and a second input node receiving a second specified voltage. The first specified voltage supplied through the fifth switch has a lower impedance than the output of the second selector, The second specified voltage supplied through the sixth switch has a lower impedance than the output of the first selector. The control method, Turning off the first, second and sixth switches and turning on the third, fourth and fifth switches; (B) turning on the first, second and sixth switches and turning off the third, fourth and fifth switches; When switching from the step (A) to the step (B), the third switch is turned off and the second switch is turned on at the same time, and then the first and sixth switches are turned on. Simultaneously turning off the fourth and fifth switches (C); When switching from the step (B) to the step (A), the second switch is turned off and the third switch is turned on, and then the fourth and fifth switches are turned on. And controlling the first and sixth switches to be off at the same time.

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