TW200531247A - Semiconductor package with leads in different wire-bonding planes - Google Patents

Semiconductor package with leads in different wire-bonding planes Download PDF

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Publication number
TW200531247A
TW200531247A TW93106549A TW93106549A TW200531247A TW 200531247 A TW200531247 A TW 200531247A TW 93106549 A TW93106549 A TW 93106549A TW 93106549 A TW93106549 A TW 93106549A TW 200531247 A TW200531247 A TW 200531247A
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Taiwan
Prior art keywords
bonding
plane
pins
wire
patent application
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TW93106549A
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Chinese (zh)
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TWI240398B (en
Inventor
Chih-Cheng Hung
Chih-Shih Wang
Chin-Chuan Li
Cheng-Tsung Hsu
Cheng-Lan Tseng
Yu Liang Lin
Chuang Sue Huang
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Advanced Semiconductor Eng
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Priority to TW93106549A priority Critical patent/TWI240398B/en
Publication of TW200531247A publication Critical patent/TW200531247A/en
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Publication of TWI240398B publication Critical patent/TWI240398B/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

A semiconductor package with leads in different wire-bonding planes includes a chip encapsulated by a package body. A plurality of first leads and a plurality of second leads are staggered around the chip. Wherein, each of the second leads has a connecting finger protruded from the first leads. The second leads are bent so that connecting fingers of the second leads are formed on a wiring-bonding plane different from that of connecting fingers of the first leads formed on. A plurality of first wires and a plurality of second wires respectively connect the connecting fingers of the first leads and the connecting fingers of the second leads to the chip in different loop heights. The wires will not be wire-swept during formation of the package body.

Description

200531247200531247

發明所屬之技術領域】 本發明係有關於一錄本道辦+ » U+ ^ n ^ ^ Μ Β P種+導體封裝構造，特別係有關於 種知線連接M片與導線架之半導體封裝構造。 先前技術】The technical field to which the invention belongs] The present invention relates to a recording package + »U + ^ n ^ ^ Β P + conductor package structure, and particularly relates to a semiconductor package structure in which the known wire connects the M chip to the lead frame. Prior art

習知半導體封裝構造係以一導線架作為外部連接介 質’並以銲線打線連接該導線架之引腳與該晶片之録墊 〔bondmg pad〕，如我國專利公告第5424〇3號揭示有— 種由導線架完成之晶片封裝構造，該導線架係包含有一晶 片承座以及複數個配置在該晶片承座外周之引腳，一邊緣 鋸齒狀之金屬環係以聯結桿連接且環繞該晶片承座，一晶 片係設於該晶片承座，複數個銲線係連接該晶片之銲墊與 該些引腳之内端指部〔或稱内引腳〕，隨著晶片銲墊之高 密度發展，在相鄰銲線間之間距也越來越小，容易在封膠 體形成之壓模製程中，產生銲線沖線〔wire swe 之問 请參閱第1及2圖，一種平面内引腳設計之半導體封裝 構造100係包含有由一導線架形成之複數個引腳11〇與一晶 片承座120、一晶片13〇、複數個銲線14〇及一封膠體15〇，The conventional semiconductor package structure uses a lead frame as an external connection medium and uses solder wires to connect the leads of the lead frame and the bond pad of the chip. As disclosed in Chinese Patent Bulletin No. 5424〇3- A chip packaging structure is completed by a lead frame. The lead frame includes a chip holder and a plurality of pins arranged on the periphery of the chip holder. A jagged metal ring is connected by a connecting rod and surrounds the chip holder. A wafer is provided on the wafer holder, and a plurality of bonding wires are connected between the pads of the wafer and the inner fingers (or inner pins) of the pins. With the high density development of the wafer pads, The distance between adjacent bonding wires is also getting smaller and smaller, and it is easy to produce bonding wires in the compression molding process of forming the sealant. [Wire swe Please refer to Figures 1 and 2 for a kind of in-plane pin design The semiconductor package structure 100 includes a plurality of pins 11 and a wafer holder 120, a wafer 130, a plurality of bonding wires 14 and a gel 15 formed by a lead frame.

每一引腳110係具有一内端連接指ηι以及延伸至該封膠體 150外之外腳部112，該些連接指U1係環繞在該晶片承座 120外周並形成在同一打線平面，該晶片丨3〇係黏設於該晶 片承座120，並以該些銲線HO連接該晶片130之銲塾131與 该些引腳110之連接指111，由於習知該些引腳之連接 指111係在同一打線平面，因此該些銲線丨4〇係具有大致相Each pin 110 has an inner connecting finger η and a foot 112 extending to the outside and outside of the encapsulant 150. The connecting fingers U1 surround the periphery of the wafer holder 120 and are formed on the same wiring plane. The chip丨 30 is glued to the wafer holder 120, and the welding pads 131 of the wafer 130 and the connecting fingers 111 of the pins 110 are connected by the bonding wires HO. Because the connecting fingers of the pins are known to be 111 Because they are on the same wire plane, these bonding wires

第12頁 200531247 五、發明說明（2) 同^弧高，當該些連接指111共平面地高密度排列時，該 些銲線140的間距也越來越小，容易在壓模形成該封膠體 150^之過程中，導致該些銲線14〇發生沖線問題，此外'習 知該晶片130之銲墊131將依照該些引腳13〇之順序而對應 配置，當該晶片13〇之銲墊131與該些引腳13〇之對應位置 順序不致時，该些銲線1 4 G無法作交叉打線，否則會有 沖線短路之問題。 &…會有 【發明内容】 本發明之主要目的係在於提供一種具不 腳之半導體封裝構造，在相鄰之第一引腳之間係 二f第二引腳之突出連接指係形成於-打線平面， 八=幸又犬出於該些第一引腳之連接指並且與該些第一引 = : = = 線平面具有一高度差，使得連接在該 ί鮮線與連接在該第：引腳之連接指 密度引腳之排列，甚至可運用於銲線之錯位交：於： 得該晶片之料具有更高度彈性之設計。乂又連接，使 本發明之次一目的係在於提供一種具不同打 俜體封裝構造，複數個第—引腳與複數個第二引腳 列，該些第二引腳係具有較突出於該丄;丨： 腳 s &且該些第二引腳其係經彎折，使得該些第一 連接指係形成於第一打線平面，該些第二引腳之 ^係形成於第二打線平面，該第一打線平面與該二 面具有-高度差，連接在該第一引腳之連接指之銲‘與Page 12 200531247 V. Description of the invention (2) With the same arc height, when the connecting fingers 111 are arranged in a high-density plane, the pitches of the bonding wires 140 are getting smaller and smaller, and it is easy to form the seal in the stamper. During the process of the colloid 150 ^, the bonding wire 14o has a punching problem. In addition, it is known that the bonding pads 131 of the wafer 130 will be correspondingly arranged in accordance with the order of the pins 13o. When the corresponding positions of the bonding pads 131 and the pins 13 are not in order, the bonding wires 14G cannot be cross-connected, otherwise there will be a problem of short-circuiting. & ... will have [Content of the invention] The main purpose of the present invention is to provide a semiconductor packaging structure with no legs, the two first pins adjacent to the second f-pin protruding connection fingers are formed in -The plane of the wire, eight = fortunately, because of the connecting pins of the first pins and the first lead =: = = the plane of the wire has a height difference, so that the connection on the fresh line and the connection on the first : The connection of the pins refers to the arrangement of the density pins, which can even be applied to the misalignment of the bonding wires: In: The material of the wafer has a more highly flexible design. It is connected again, so that a second object of the present invention is to provide a package structure with different dome bodies, a plurality of first-pin and a plurality of second pin rows, and the second pins are more prominent than the丨; 丨: The feet s & and the second pins are bent, so that the first connection fingers are formed on the first wiring plane, and the second pins are formed on the second wiring. Plane, the first wire-bonding plane and the two sides have a -height difference, and the connection fingers connected to the first pin are soldered and

第13頁 200531247 五、發明說明（3) 連接在該第二引腳之連接指之銲線具有不同之弧高，以滅 少沖線發生，甚至可運用於銲線之錯位交叉連接。 依本發明之具不同打線平面引腳之半導體封裝構造， 主要^含有複數個第一引腳、複數個第二引腳、一晶片及 一封膠體，其中該些第一引腳與該些第二引腳係構成於_ ^線架中且呈錯位排列，每一第一引腳係具有一第一連接 指，以，打線連接，該些第一連接指係形成於一第一打線 平面，每一第二引腳係具有較突出於鄰近之第一引腳之第 一連接私，忒些第二連接指係形成於一第二打線平面，該 ，第二引腳係，彎折，使得該第二打線平面係與該第一打 、、’平面具有呵度差，該晶片係具有複數個第一銲墊以及 Ϊί㈣二銲塾，該晶片係黏設在-晶片承座，並以複數 f第二知線連接該晶片之該些第一銲墊與該些第一引腳之 了連接指，以複數個第二銲線連接該晶片之該些第二銲 Ϊ片、引腳之第二連接指，並且該封膠體係密封該 ;曰2 if一銲線與該些第二銲線，由於該些第-連接 ί係形成於不同打線平面，使得該些第-銲 、、^二二第一銲線具有不同弧高，以減少 【實施方式】 王 所附圖式，本發明將列舉以下實施例說明。 種且二閱ΐ3及4冑，依據本發明之-具體實施例，-ϊ;:平面引腳之半導體封裝構造2〇0係主要包含 ΐίϊϊ第一引腳210、複數個第二引腳22〇、-晶片240 -〜體260 ’其中該些第一引腳21〇與該些第二引腳 第14頁 200531247 五、發明說明（4) 2 2 0係構成於一導線架中〔圖未繪出〕，在本實施例中， 該些第一引腳210與該些第二引腳220係呈錯位排列，以引 腳朝向該晶片240之長度定義該些第一引腳210與該些第二 引腳22 0，在本實施例中，該導線架另包含有一晶片承座 230〔die pad〕，以黏設固定該晶片240，該晶片承座230 係以複數個聯結桿2 31〔 t i e bar〕連接至該導線架，每一 第一引腳2 1 0係具有一第一連接指21 1，在本實施例中，每 一第一引腳2 1 0係具有一對應之外腳部2 1 2，或者亦可以 是，如QFN導線架之無外引腳之連接墊取代該外腳部212， 該些第一連接指21 1係形成於一第一打線平面p 1，以供第 一銲線251之打線連接，每一第二引腳220係具有一第二連 接指221，其係較突出於鄰近之第一引腳21〇，該些第二連 接指22 1係形成於一第二打線平面P2，而每一第二引腳220 亦可具有一外腳部〔圖未繪出〕，在本實施例中，該些第 二引腳220係可以一彎折部222彎折而形成一下沉區 〔down-set area〕，其亦可以彎折而形成一上升區，使 得該第二打線平面P 2係與該第一打線平面p 1具有一高度 差，以供連接不同弧南之鲜線2 5 1、2 5 2，在本實施例中， 該第二打線平面P2係較低於該第一打線平面pi ,並且每一 聯結桿232係具有一彎折部232，使得該晶片承座230較下 沉於該第二打線平面P2，使得，該第二打線平面p2係介於 該第一打線平面P1與該晶片承座230之間，以縮短該些第 一銲線251與該些第二銲線252之長度。 該晶片240係具有一主動面241及一對應之背面242，Page 13 200531247 V. Description of the invention (3) The connecting wire connected to the second pin means that the welding wire has a different arc height in order to reduce the occurrence of punched wires and can even be applied to the misaligned cross-connection of the welding wire. According to the present invention, a semiconductor package structure with different wiring plane pins mainly includes a plurality of first pins, a plurality of second pins, a chip, and a colloid, wherein the first pins and the first pins are The two pins are formed in the _ ^ wire frame and are arranged in a misalignment. Each first pin has a first connection finger, which is connected by a wire. The first connection fingers are formed on a first wire plane. Each second pin has a first connection that protrudes from the adjacent first pin, and some second connection fingers are formed on a second wiring plane. The second pin is bent so that The second bonding plane is different from the first bonding plane, the wafer has a plurality of first pads and two solder pads, and the wafer is adhered to a wafer holder, and f The second known wire connects the first bonding pads of the chip with the first pins, and a plurality of second bonding wires connect the second bonding pads and pins of the chip with a plurality of second bonding wires. Two connecting fingers, and the sealant system seals the; said 2 if a bonding wire and the second bonding wires, The first connection lines are formed on different planes, so that the first and second welding lines have different arc heights, so as to reduce [Embodiment] The drawings of the drawings, the present invention will list The following examples illustrate. According to the specific embodiments of the present invention, the two-dimensional structure of the semiconductor package structure 200 includes a first lead 210 and a plurality of second leads 22. --- Chip 240 --- Body 260 'These first pins 21 and the second pins are described on page 14. 200531247 V. Description of the invention (4) 2 2 0 is formed in a lead frame (not shown) Out], in this embodiment, the first pins 210 and the second pins 220 are arranged in an offset manner, and the lengths of the pins toward the chip 240 are used to define the first pins 210 and the first pins 210. Two pins 22 0. In this embodiment, the lead frame further includes a die pad 230 to fix and fix the die 240. The die pad 230 is connected with a plurality of tie rods 2 31 [tie bar] is connected to the lead frame, and each first pin 2 1 0 has a first connection finger 21 1. In this embodiment, each first pin 2 1 0 has a corresponding outer leg. 2 1 2 or alternatively, such as a QFN lead frame without an outer pin connection pad replacing the outer leg portion 212, the first connection fingers 21 1 are formed in a A wire plane p 1 is used for wire connection of the first bonding wire 251. Each second pin 220 has a second connection finger 221, which is more prominent than the adjacent first pin 21. The two connecting fingers 22 1 are formed on a second wiring plane P2, and each second pin 220 may also have an outer leg portion (not shown). In this embodiment, the second pins 220 The bending part 222 can be bent to form a down-set area, and it can also be bent to form a rising area, so that the second wiring plane P 2 and the first wiring plane p 1 have A height difference for connecting the fresh lines 2 5 1 and 2 5 2 of different arc south. In this embodiment, the second wiring plane P2 is lower than the first wiring plane pi, and each connecting rod 232 It has a bent portion 232, so that the wafer holder 230 sinks below the second wire plane P2, so that the second wire plane p2 is between the first wire plane P1 and the wafer seat 230 In order to shorten the length of the first bonding wires 251 and the second bonding wires 252. The chip 240 has an active surface 241 and a corresponding back surface 242.

第15頁 200531247 五、發明說明（5) ^孩主動面241形成有複數個第一銲墊243以及複數個第二 =塾244 ’該晶片240之背面242係黏設在該晶片承座23 0， 複，個第一銲線251係連接該晶片24〇之該些第一銲墊243 ，4些第一引腳21 〇在第一打線平面？1之第一連接指2U， 複數個第二銲線252係連接該晶片240之該些第二銲墊244 與4些第二引腳2 20在第二打線平面p2之第二連接指221， 由於该些第一連接指211係與第二連接指22i係參差錯位地 形成在不同打線平面P1、P2，使得該些第一銲線251與該 些第二銲線252具有不同弧高，在本實施例中，該些第二 ^線252係低於該些第一銲線251，以減少沖線發生，該封 膠體260係密封該晶片240與該些第一輝線251與該些第二 銲線25 2。 — 一 因此，本發明係利用第一引腳2丨〇與具有該些突出狀 =二連接指221之第二引腳220呈錯位排列且該些第一連接 #曰2 11與该些第二連接指2 21形成在不同打線平面，使得連 接該些第一連接指211之第一銲線25 i與連接第二連接指 2 21之第二銲線2 52具有不同之弧高，以增加銲線之間距， 甚至如第4圖所示，必要時可以將至少一第二銲線託2係與 ，近之第一銲線251錯位交叉，而不會有沖線短路之問/、 題，故本發明適用於高密度之引腳排列之半導體封裝，並 且該些第一銲墊243與該些複數個第二銲墊2 44可不需要依 序錯位排列，可以彈性化設計該晶片24〇之第一銲^43與义 第二銲墊244配置，而不需受限於銲線沖線短路之問題。” 本發明之保護範圍當視後附之申請專利範圍所界定者 200531247 五、發明說明（6) 為準，任何熟知此項技藝者，在不脫離本發明之精神和範 圍内所作之任何變化與修改，均屬於本發明之保護範圍。Page 15 200531247 V. Description of the invention (5) ^ The active surface 241 of the child is formed with a plurality of first pads 243 and a plurality of second = 244 ′ The back surface 242 of the wafer 240 is adhered to the wafer holder 23 0 Moreover, the first bonding wires 251 are connected to the first bonding pads 243 of the chip 24, and the first pins 21 are on the first wiring plane? The first connection finger 1 is 2U, and the plurality of second bonding wires 252 are the second connection fingers 221 connecting the second pads 244 and 4 second pins 2 20 of the chip 240 on the second wiring plane p2, Since the first connecting fingers 211 and the second connecting fingers 22i are staggered and formed on different wire planes P1 and P2, the first bonding wires 251 and the second bonding wires 252 have different arc heights. In this embodiment, the second wires 252 are lower than the first bonding wires 251 to reduce the occurrence of punching lines. The sealing compound 260 seals the wafer 240 and the first glow wires 251 and the second wires. Welding wire 25 2. — One, therefore, the present invention uses the first pin 2 and the second pin 220 having the protruding shapes = two connection fingers 221 to be misaligned, and the first connections # 21 and the second The connecting fingers 2 21 are formed on different wire bonding planes, so that the first bonding wires 25 i connecting the first connecting fingers 211 and the second bonding wires 2 52 connecting the second connecting fingers 2 21 have different arc heights to increase bonding. The distance between the wires, even as shown in Fig. 4, if necessary, at least one second welding wire holder 2 can be crossed with the nearest first welding wire 251, and there will be no problem of short circuit. Therefore, the present invention is suitable for semiconductor packages with high-density lead arrangements, and the first solder pads 243 and the plurality of second solder pads 2 44 need not be sequentially misaligned, and the chip can be flexibly designed. The first bonding pad 43 and the second bonding pad 244 are arranged without being limited by the problem of a short-circuit of the bonding wire. The scope of protection of the present invention shall be determined by the scope of the appended patent application 200531247 V. Description of Invention (6) shall prevail. Anyone skilled in the art may make any changes and modifications without departing from the spirit and scope of the present invention. Modifications belong to the protection scope of the present invention.

Hi 第17頁 200531247 圖式簡單說明 — 【圖式簡單說明】 第1圖：習知平面内引腳設計之半導體封裝構造之截面示 意圖； 第2圖：習知平面内引腳設計之半導體封裝構造之上表面 透視圖； 第3圖：依據本發明之具不同打線平面引腳之半導體封裝 構造之截面示意圖；及 、 第4圖：依據本發明之具不同打線平面引腳之半導體封裝 構造之上表面透視圖。 元件符號簡單說明： 1〇〇半導體封裝構造 110 引腳 in 連接指 112 外腳部 120 晶片承座 121 聯結桿 130 晶片 131 銲墊 140 銲線 150 封膠體 200 半導體封裝構造 210 第一引腳 211 第一連接指 212 外腳部 220 第二引腳 221 第二連接指 222 青折部 230 晶片承座 231 聯結桿 232 彎折部 240 晶片 241 主動面 242 背面 243 第一銲墊 244 第二銲墊 251 第一銲線 252 第二銲線 260 封膠體 P1 第一打線平面 P2 第二打線平面Hi Page 17 200531247 Brief description of the drawings — [Simplified description of the drawings] Figure 1: Cross-sectional schematic diagram of a semiconductor package structure with conventional in-plane pin design; Figure 2: Semiconductor package structure with conventional in-plane pin design Upper surface perspective view; Figure 3: Schematic cross-sectional view of a semiconductor package structure with different wiring plane pins according to the present invention; and, Figure 4: Above a semiconductor package structure with different wiring plane pins according to the present invention Surface perspective view. Simple explanation of the component symbols: 100 semiconductor package structure 110 pin in connection finger 112 outer leg 120 chip holder 121 connecting rod 130 chip 131 solder pad 140 bonding wire 150 sealing compound 200 semiconductor package structure 210 first pin 211 first One connecting finger 212 outer leg 220 second pin 221 second connecting finger 222 green folding part 230 chip holder 231 coupling rod 232 bending part 240 chip 241 active surface 242 back surface 243 first pad 244 second pad 251 First bonding wire 252 Second bonding wire 260 Sealant P1 First bonding plane P2 Second bonding plane

Claims (1)

200531247 六、申請專利範圍 【申請專利範圍】 1、一種具不同打線平面W腳之半導體封 複數個第-引腳，每—第一引腳係 '構^ ’包含·· 指，該些第一連接指係形成於一第線^第—連接 連接； +面，以供打線 複數個第二引腳，其係與該些第一 一第二引腳係具有一第二連接指，其係位排列，每 -引腳，該些第二連接指係形成於一第： = 近之第 =連接，該第二打線平面係與該第—打線平面具有：： 墊一晶片，其係具有複數個第一銲墊以及複數個第二銲 複數個第/銲線’其係連接該晶片之該些第一銲塾盘 該些第一引腳之第一連接指； 一 複數個第二鲜線’其係連接該晶片之該些第二鲜塾與 該些第二引腳之第二連接指；及 〃 一封膠體，其係悉封该晶片與该些第一鲜線與該此第 二銲線。 2、如申請專利範圍第1項所述之具不同打線平面引腳之 半導體封裝構造，其中該些至少一第二銲線係與鄰近之第 一銲線錯位交又。 3、如申請專利範圍第1項所述之具不同打線平面引腳之 半導體封裝構造，其中該第二打線平面係較低於該第一打 線平面，且該痤第二銲線之弧高係較低於該些第一銲線之200531247 VI. Scope of patent application [Scope of patent application] 1. A semiconductor package with different wire plane W pins has several -pins, each-the first pin is 'structure ^' contains ... means that these first The connecting finger is formed on a first line ^ -connecting connection; + surface for wiring a plurality of second pins, which has a second connecting finger with the first and second pins, and its position Arranged, per-pin, the second connection fingers are formed in a first: = near the first = connection, the second wire bonding plane and the first wire bonding plane have: a pad with a wafer, which has a plurality of A first pad and a plurality of second bonding pads / bonding wires 'which are first connection fingers connected to the first bonding pads of the wafer and the first pins; a plurality of second fresh wires' It is a second connection finger connecting the second fresh 塾 of the wafer and the second pins; and 〃 a gel, which seals the wafer and the first fresh wires and the second solder line. 2. The semiconductor package structure with different wiring plane pins as described in item 1 of the scope of the patent application, wherein the at least one second bonding wire is misaligned with the adjacent first bonding wire. 3. The semiconductor package structure with different wiring plane pins as described in item 1 of the scope of patent application, wherein the second wiring plane is lower than the first wiring plane, and the arc height of the second bonding wire is Lower than those of the first bonding wires 第19頁 200531247 六、申請專利範圍 弧南。 4、 如申請專利範圍第1項所述之具不同打線平面引腳之 半導體封裝構造，其中每一第二引腳係具有_彎折部。 5、 如申請專利範圍第1項所述之具不同打線平面引腳之 半導體封裝構造’其另包含有一晶片承座，用以固定該晶 片0 6、 如申請專利範圍第5 半導體封裝構造，其中該 平面與該晶片承座之間。 7、 一種導線架，適用於 複數個第一引腳，每 指，該些第一連接指係形 連接；及 複數個第二引腳，其 一第一弓丨腳係具有一第二 一引腳，該些第二連接指 打線連接，該第二打線平 度差。 8、 如申請專利範圍第7 線平面係較低於該第一打 9、 如申請專利範圍第7 引腳係具有一彎折部。 1 0、如申請專利範圍第7 一晶片承座，用以固定一 項所述之具不同打線平面引腳之 第二打線平面係介於該第一打線 晶片封裝’其係包含： 一第一引腳係具有一第一連接 成於一第一打線平面，以併打線 係與該些第一引腳錯位排列，每 連接指，其係較突出於鄰近之第 係形成於一第二打線平面，以供 面係與該第一打線平面具有一高 項所述之導線架，其中該第二打 線平面。 項所述之導線架，其中每一第二 曰項所述之導線架’其另包含有 曰曰片〇Page 19 200531247 6. Scope of Patent Application Arc South. 4. The semiconductor package structure with different wiring plane pins as described in item 1 of the scope of patent application, wherein each second pin has a _bend portion. 5. The semiconductor package structure with different wiring plane pins as described in item 1 of the scope of the patent application, which further includes a wafer holder for fixing the chip. 0. The semiconductor package structure of the fifth scope of the patent application, where Between the plane and the wafer holder. 7. A lead frame suitable for a plurality of first pins, each finger, the first connection fingers being connected in a form; and a plurality of second pins, a first bow of which has a second lead Feet, the second connection fingers are connected by a wire, and the second wire is flat. 8. If the 7th line plane of the scope of the patent application is lower than the first dozen 9. If the 7th pin of the scope of the patent application has a bent portion. 10. According to the 7th chip holder of the scope of the patent application, a second bonding plane with different bonding plane pins as described above is located between the first bonding chip package and it includes: a first The lead system has a first connection formed on a first wiring plane, and the parallel wiring system is aligned with the first pins. Each connecting finger is more prominent than the adjacent first system and is formed on a second wiring plane. The supply plane and the first wiring plane have a lead frame according to the above item, wherein the second wiring plane. The lead frame according to the item, wherein each of the lead frames according to the second item, further includes a yoke piece. 第20頁 200531247 六、申請專利範圍 11、 如申請專利範圍第1 〇項所述之導線架，其中該第二 打線平面係介於該第一打線平面與該晶片承座之間。 12、 一種具不同打線平面引腳之半導體封裝構造，包 含·· 複數個第一引腳，每一第一引腳係具有一第一連接 冲曰’该些第一連接指係形成於一第一打線平面，以供打線 連接； 一第二引腳，其係排列於該些第一引腳之間，該第 二引腳係具有一第二連接指，該第二連接指係形成於一第Page 20 200531247 6. Scope of patent application 11. The lead frame as described in item 10 of the scope of patent application, wherein the second bonding plane is between the first bonding plane and the wafer holder. 12. A semiconductor package structure with different wiring plane pins, including a plurality of first pins, each of which has a first connection, said 'the first connection fingers are formed in a first A wire plane for wire connection; a second pin arranged between the first pins, the second pin having a second connection finger formed on a First 二打線平面，以供打線連接，該第二打線平面係與該第一 打線平面具有一高度差； 曰曰片’其係具有複數個第^„輝塾以及至少一第二 銲墊； 一 複數個第一銲線，其係連接該晶片之該些第一銲墊 與該些第一引腳之第一連接指； 一第二銲線，其係連接該晶片之該第二銲墊與該第 二引腳之第二連接指，兮笛_ ^ 埂接知 忒第一銲線之弧高係不同於該些第 一知線之弧高；及 綠一封膠體，其係密封該晶片與該些第一銲線與該第Two wire planes for wire connection, the second wire plane has a height difference from the first wire plane; the film 'it has a plurality of first and second solder pads; a plurality of A first bonding wire that connects the first bonding pads of the chip and the first connecting fingers of the first pins; a second bonding wire that connects the second bonding pad of the wafer and the The second connection of the second pin means that the arc height of the first bonding wire connected to the first wire is different from the arc height of the first known wires; and the green colloid seals the chip and The first bonding wires and the first 1 3、如申請專利範圍第1 2 之半導體封裝構造，其中該 線錯位交又。 項所述之具不同打線平面引腳 第二銲線係與鄰近之一第一銲 14 項所述之具不同打線平面引腳 如申請專利範圍第1 21 3. For the semiconductor package structure No. 12 in the scope of patent application, the lines are dislocated and intersected. The second bonding wire with different wiring planes described in item 1 is soldered with a neighboring one of the first bonding pins. 200531247 六、申請專利範圍 ------ 之半導體封裝構造’其中該第± 打線平面，使得該第二銲線平面係較低於該第一 弧高。 弧咼係低於該些第一銲線之 1 5、如申請專利範圍第丨2 項 之半導體封裝構造，其中該第 1 6、如申請專利範圍第丨2項 之半導體封裝構造，其另包含 晶片 。 所述之具不同打線平面引腳 二引腳具有一彎折部。 所述之具不同打線平面引腳 有一晶片承座，用以固定該 17、如申請專利範圍第丨6項 之半導體封裝構造，其中該第—之具不同打線平面引腳 線平面與該晶片承座之間。〜打線平面係介於該第一打200531247 Sixth, the scope of patent application ------ The semiconductor package structure ′ wherein the first ± wiring plane makes the second bonding wire plane lower than the first arc height. The arcs are lower than those of the first bonding wires. For example, the semiconductor package structure of item No. 2 in the scope of patent application, wherein the semiconductor package structure of item No. 16 at the scope of patent application No. 2 includes: Wafer. The two pins with different wiring plane pins have a bent portion. The chip with different wire bonding planes has a chip holder for fixing the semiconductor package structure according to item 17 of the patent application, wherein the first wire with different wire bonding planes and the chip carrier Between seats. ~ The line plane is between the first line
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614860B (en) * 2014-10-08 2018-02-11 Li Ming Fen Semiconductor wire bonding structure and process thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI614860B (en) * 2014-10-08 2018-02-11 Li Ming Fen Semiconductor wire bonding structure and process thereof

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