200525438 玖、發明說明： 【發明所屬之技術領域】 本發明係關於可攜式資料儲存裝置，及利用此裝置 與擷取寫入之資料的方法。 【先前技術】 過去數年中，提供含有快閃記憶體且可連接至電腦 列匯流排之資料儲存裝置已越來越受重視。此領域之 領先技術文件係為W 0 0 1 / 6 1 6 9 2，其揭示一種後來以 「Thumbdrive」行銷之單件式裝置。在此文件的一具 中，此裝置之殼體上所裝設之公USB插頭直接連接至 腦中的母USB插座，使得電腦能夠在USB控制器的控 將資料來回傳輸到可攜式儲存裝置之快閃記憶體。針 種裝置，已有各種改良提出。例如，W 0 0 3 / 0 0 3 2 8 2揭 置可設有一指紋感測器，只有在指紋感測器比較使用 瞄指紋與預先儲存資料，藉以核對使用者身份後，才 取裝置中所儲存的資料。此等文件所揭示之内容併述 以供參考。 此種可攜式儲存裝置的結構如圖1所示。可攜式儲 置標示為1，其具有一殼體，以虛線表示。其包括一 控制器2，控制一 USB介面3 (例如一 USB插頭），其 連接到主機電腦5之U S B介面4 (例如一 ϋ S B插座）。 機電腦5傳輸到USB介面3的資料透過USB控制器2 到一主控制單元7。 資料封包有各種類型。包括W R I T E資料封包，其含 312/發明說明書(補件)/93-08/93115289 儲存 之串 一項 商標 體例 一電 制下 對此 示裝 者掃 能存 於此 存裝 USB 直接 從主 而傳 有 6 200525438 W R I Τ E指令，將5 1 2位元組之倍數的資料量寫到特定邏輯 位址。另外亦包括R E A D資料封包，其含有一 R E A D指令， 從特定邏輯位址讀取資料。W R I Τ E指令一般含有一第一部 分資料必須寫入之位置的邏輯位址、欲寫入多少資料之指 示、及欲寫入之資料。傳遞一個W R I Τ E指令可能需要數個 資料封包。同樣地，一 READ指令指示一開始讀取之邏輯位 址、及欲從該處讀取多少記憶體之指示。 主控制單元7藉由控制一 NAND快閃記憶體9來實施此 等指令。主控制單元7可利用示意圖中標示為1 2之一或多 條線傳送命令符元，藉以控制N A N D快閃記憶體9。典型地， 此等線1 2包括一條線在資料欲寫入到快閃記憶體9時用於 傳送WR I TE信號，一條線在快閃記憶體欲傳送資料到主控 制單元7時用於傳送READ信號，多條線用於傳送一位址信 號，指示資料應寫入記憶體中的位置、或資料應從記憶體 中讀取的位置，及一 ENABLE信號，其必須設為某特定值， 快閃記憶體才能夠運作。 當主控制單元7需要將資料儲存到快閃記憶體9時，其 在傳送W R I Τ E命令、E N A B L E信號及位址的同時，經由一 8 -位元匯流排8將資料傳送過去。位址係為一實體位址（亦 即記憶體單元9中的一特定位址），此實體位址係根據主控 制單元7内或主控制單元7可存取之RAM記憶體所儲存的 對映表而對應於邏輯位址。反應於一 READ命令時，資料會 從裝置傳出，其係以5 1 2位元組封包從N A N D快閃記憶體9 傳出，經由8 -位元匯流排8，而傳到主控制單元7。主控 312/發明說明書(補件)/93-08/93 ] 15289 200525438 制單元將5 1 2位元組封包傳送到U S B控制器2，其透過U S B 介面3而將封包從裝置1傳送到主機5。 此裝置習知係透過USB介面3而供應電源，當USB介面 3從電腦的USB插座卸下時，裝置的電源即關閉。所有儲 存在主控制單元7之RAM中的資料都會消失。 圖2顯示NAND快閃記憶體9的記憶體空間。此裝置之 結構在每一 「頁」6中可儲存5 1 2位元組區段之資料（請 注意亦有其他可能性，例如每頁儲存2千位元組），每一頁 亦含有一個別控制資料儲存區11，用以儲存控制資料（典 型為1 6位元組）。資料係配置在「區塊」1 0中（亦即圖2 中的各列），例如每一區塊1 0具有6 4頁6。習知N A N D快 閃記憶體有三項限制： 1 .任何一特定頁不是處於「擦除」狀態、就是處於「未 擦除」狀態，在「擦除」狀態中，可將資料寫入該頁，在 「未擦除」狀態中，該頁儲存有資料，而不同的資料不可 寫入該頁。這些頁只能以區塊為單位（b 1 〇 c k - b y - b 1 〇 c k ) 的方式從未擦除狀態轉換到擦除狀態，亦即，一特定區塊 的所有未擦除頁必須一次擦除，失去其中所儲存的所有資 料。 2. 一特定的區塊或頁具有有限的生命週期。換言之， 其從擦除狀態轉換成未擦除狀態只能進行有限的次數，例 如1 0，0 0 0或1 0，0 0 0次。這會限制記憶體裝置的壽命。 3 . N A N D快閃記憶體有時會有「損壞」區塊，亦即資料 無法可靠地寫入其中。 8 312/發明說明書(補件)/93-08/93115289 200525438 如上所述，N A N D記憶體裝置9中寫入資料之位址或讀出 資料之位址，係由USB介面3所接收之資料封包中編碼的 一邏輯位址決定。習知上，主控制單元必須存取一表，用 於儲存邏輯位址空間中的位址與不在髒表（d i r t y t a b 1 e ) 中之記憶體裝置區塊中之實體記憶體空間中的位置（亦即 記憶體中的「實體位址」）之間的一對映關係。具體言之， 每一區塊係對映到邏輯位址空間的一個別區域，其具有之 位址數量與頁的數量相同。此對映係被固定。因此，損壞 區塊並未關聯於任何邏輯位址。 除了損壞區塊以外，還有其他區塊未關聯於邏輯位址。 此等為「保留」區塊，其係用於儲存可攜式儲存裝置可能 需要的其他資料。例如，髒位址表本身係儲存在保，留區塊 中 〇 主控制單元7包括一檔案管理系統，包括一區塊定位 表，其指示每一區塊係處於擦除狀態或未擦除狀態、以及 有多少區塊係處於擦除狀態或未擦除狀態。當主控制單元 7接收到資料欲寫入記憶體中之一區塊中的一位置時，主 控制單元7利用區塊定位表，找出區塊是否處於擦除狀 態。習知上，若發現區塊係處於未擦除狀態，其會將區塊 中任何不想被覆寫的資料複製到一不同位置，將此區塊擦 除，然後將欲儲存到記憶體中的新資料寫回該區塊，並將 資料複製到不同位置。 【發明内容】 本發明提供一種新穎且實用之可攜式資料儲存裝置。 9 312/發明說明書(補件)/93-08/93115289 置的操作期間，改變邏輯位 間之區域間的對映關係。換 憶體區域之間維持一種一對 隨時間改變。 通常主機電腦上之習知作業 統計上相關，這表示，若邏 關係，則某些實體位址將會 容易很快損壞。 實體位址之間的關係，表示 減少。實質上，根據本發明 關係，當接收到一指令欲將 頁時，可改變邏輯位址與實 於擦除狀態之新區塊關聯於 區塊，而舊區塊中任何所儲 區塊。因此，舊資料只需要 術複製二次。此使得裝置的 暫時對映關係，係由一記憶 作速度，記憶體位址對映表 如，在主控制單元本身内）。 儲存在快閃記憶體本身内， 失去資料。 多頁之控制資料儲存區可儲 10 200525438 概言之，本發明提出：在裝 址空間之區域與實體記憶體空 言之’邏輯位址區域與實體記 一的對映關係，但此對映關係 這具有數項優點。 首先，本發明人已注意到， 系統所產生的邏輯位址傾向於 輯位址與實體位址具有一固定 較其他位址更常被使用，因此 再者，能夠改變邏輯位址與 需要寫入資料之寫入操作次數 之邏輯位址與實體位址之對映 資料寫入到處於未擦除狀態之 體位址之對映關係，使得一處 該邏輯位址。新資料被寫入新 存之未被擦除的資料亦寫入新 複製一次，而非如上揭習知技 整體操作加快。 邏輯位址與實體位址之間的 體位址對映表所定義。為了操 較佳係儲存在RAM記體中（例 但，定義之對映資料較佳亦可 使得在關閉電源的狀態下不會 特別地，一特定區塊之一或 312/發明說明書(補件)/93-08/93115289 200525438 存指示資料，指示該區塊目前關聯於哪一個邏輯位置區 域。當裝置連接至一主機電腦且主控制單元供應有電源 時，主控制單元利用此資料產生對映表（其可儲存於其快 取記憶體中當對映關係改變，使得對映於一特定邏輯位 址區域之實體位址從一第一區塊改變成一第二區塊，則對 映表中的資料及快閃記憶體裝置中所儲存的對映資料會被 更新。在資料儲存於快閃記憶體的情況，其方式僅係在第 一區塊擦除之前將定義對映關係的資料從第一區塊複製到 第二區塊。 如上所述，在習知系統中，邏輯位址空間係小於實體位 址空間，因為有些區塊未關聯於任何邏輯位址。此等為保 留區塊與損壞區塊。在本發明中，除了保留區塊與損壞區 塊，任何時候均另外有一組區塊（此處稱為「貯列區塊」） 可利用來對映於一邏輯位址區域，取代目前對映於該邏輯 位址區域之區塊。當對映關係需要改變時，其中一貯列區 塊會被選取，成為關聯於一個邏輯位址區域。貯列區塊在 貯列中排隊時較佳係處於擦除狀態，而不是在其成為關聯 於一個邏輯位址區域時才進行擦除。 記憶體位址對映關係的更新（亦即，選擇一擦除之第二 區塊來取代對映關係中的一第一區塊）的執行時機，係在 每當所接收之新W R I Τ E指令到要將資料寫到一非處於擦除 狀態之實體位址之位置時。 其可在接收到此W R I Τ E指令時就立即執行。或者，在本 發明之較佳改良中，主控制單元依據一特定W R I Τ E指令所 11 312/發明說明書(補件)/93-08/93115289 200525438 執行的寫入操作可懸置一段特定期間，只有在該期間 收到符合一預定之第一指令相似性標準的指令時，才 行。正如同上述可變化之位址對映表的觀念部分係受 於邏輯位址統計上相關之觀察，此一改良係受後述觀 啟發，亦即，在一相對短時間期間内所接收到的指令 係為充分強烈相關，一併處理會比個別處理更有效率 此可增進可攜式資料儲存裝置之速度及/或壽命。此種 入操作懸置以便確認是否有另一相關之W R I Τ E指令到 觀念，構成本發明之另一獨立的態樣，除了與可變對 結合使用外，亦可於本發明之範圍内使用。 一第一此種相關係為密集連續寫入指令指定資料欲 入連續之相同邏輯區域中。針對此點，主控制裝置接 一第一指令，其指定將資料寫入一邏輯位址區域，依 憶體位址對映關係，此邏輯位址區域係對映於實體記 之一特定第一區塊，此時，主控制裝置較佳懸置至少 作，使得不被覆寫之第一區塊中所儲存的資料被複製 二區塊。如果在該期間中，主控制裝置未接收到含有 欲將資料寫入到該區塊之連續頁的封包，則其可繼續 將第一區塊中的資料複製到第二區塊之操作。或者， 在該期間中接收到一或多個封包指定其他資料欲寫入 邏輯位址區域的其他位置，則可將所有封包之資料寫 該區塊中，在此種情況中，只需要將第一區塊之其他 的資料複製到第二區塊。 一第二此種相關係為，本發明人已注意到，主控制 3丨2/發明說明書(補件)/93-08/93115289 未接 會執 啟發 察所 經常 ，因 將寫 達的 映表 寫 收到 據記 憶體 一操 到第 指令 進行 如果 相同 入到 部分 裝置 12 200525438 經常會在一短時間内接收到指定完全相同之邏輯 有W R I T E指令之封包。每當接收到一個此等指令 明之具體例不會立刻重設記憶體位址對映關係， 地在一時間期間内懸置此操作。在此期間内，資 主控制裝置所操作的一資料快取記憶體中（例如 之RAM快取記憶體）。如果在此時間期間中未收到 邏輯位址之指令，則主控制裝置如前所述開始將 快閃記憶體中。然而，在此期間中，若接收到一 令（或者，在另一具體例中，非為關於相同邏輯 則主控制裝置將資料寫到其快取記憶體（並且通 其時鐘）。在此期間中，若接收到一關於相同邏^ R E A D指令，則該資料係從快取記憶體讀取，而非 憶體裝置讀取。 選擇性地，快取記憶體可大到足以儲存關於複 位址之資料。亦即，快取記憶體可分割成複數個 一區段用於儲存關於一對應邏輯位址之資料，且 關聯於一個別計時器，用於從接收到關於該邏輯 W R I T E指令時開始測量時間。 較佳地，資料儲存裝置能夠分辨哪一個邏輯位 易經常有資料寫入（亦即，其根據輸入指令執行 識演算法），使其可選擇其認為有必要執行前二段 取操作的一組之一或多個邏輯位置。 以上說明係假設每一個欲關聯到邏輯位址區域 均有一個別對映關係，但這點需要記憶體位址對 3丨2/發明說明書(補件)/93-08/93115289 位址之含 時，本發 而是較佳 料儲存在 ，其内部 關於相同 資料寫到 W R I T E 指 位址者）， 常會重設 缉位址之 從快閃記 數個邏輯 區段，每 每一區段 位址之 置特別容 一模式辨 所述之快 之區塊 映表之内 13 200525438 容至少與可儲存資料之區塊數目一樣多。另一種方式，係 將邏輯位址區域關聯到個別區塊群組。例如，區塊可分成 (例如）每四個區塊為一個群組（因此，總共有例如 4 X 6 4二2 5 6頁），邏輯位址區域會是對映係數之倍數大（例 如，四倍大）。此種情況中，記憶體位址對映表在每一群組 與一個別之邏輯位址區域之間定義一種一對一的對映關 係。 群組可單純是連續的區塊，但是在具有任何損壞區塊的 情況下，較佳有一種較複雜的區塊設定方式，將非損壞之 區塊分組。然後，區塊群組可視為實體記憶體區域，關聯 於邏輯位址空間之區域。主控制單元可存取一指示此分組 之分組表，使得指定一邏輯位址即可利用記憶體位址表來 決定一對應群組，並利用分組表來識別構成此群組之區塊。 由於損壞區塊很少，因此大部分的群組可依照簡單規則 設定（例如，群組設為四個連續區塊為個別一組），分組表 僅儲存未依照此規則之個別區塊資料。這將可減少分組表 所需的尺寸。 為了方便起見，特定邏輯位址區域關聯於此等特殊群組 任一者的事實，可在對映位址表中包括一旗標。因此，記 憶體對映位址表將會指示何時需要參考分組表來決定關聯 於一特定邏輯位址之實體位址。 主控制單元可將一特定邏輯位址區域中的邏輯位址關 聯於對應群組之區塊，使得連續邏輯位址對應於頁之 「欄」。此種將區塊群組對應於邏輯位址區域之概念，以及 14 312/發明說明書(補件)/93./93115289 200525438 將一邏輯位址區域中的連續邏輯位址關聯於頁之襴的概 念，構成本發明之另一獨立態樣，除了與可變對映表結合 使用外，亦可於本發明之範圍内使用。 本發明第一態樣的具體表現係為一種可攜式資料儲存 裝置，包括： (i ) 一資料介面，用於將資料封包傳入或傳出裝置， (i i ) 一介面控制器， (i i i ) 一主控制單元，及 (i v )至少一 N A N D快閃記憶體單元， 介面控制器係配置成可將接收之資料透過介面而傳送 到主控制單元，及 主控制單元係配置成可辨識某些資料封包編碼有READ 指令及其他資料封包編碼有W R I T E指令： (a )當接收到指示一邏輯位址的一 R E A D指令時，存取 一記憶體位址對映表，記憶體位址對映表係將一邏輯記憶 體空間中的邏輯位址區域關聯於記憶體單元中的個別第一 實體位址區域，根據位址對映表，從對應於邏輯位址之記 憶體單元中之實體位址讀取資料，並將一或多個包括所讀 取之資料的資料封包傳送到資料介面，及 (b )當接收到指示一邏輯位址及欲寫入至該邏輯位址 之資料的W R I T E指令時，根據記憶體位址對映表，確認對 映於邏輯位址之實體位址是否處於擦除狀態，及： 若是，將資料寫到該實體位址，或 若否，修改位址對映表，將一第二實體位址區域關聯於 15 312/發明說明書(補件)/93-08/93115289 200525438 含有邏輯位址之邏輯位址區域，根據修改之記憶體位址對 映表，將資料寫至一對應於邏輯位址之實體位址，並將第 一實體位址區域之其他位置中所儲存的資料複製到第二實 體位址區域之對應位置。 應瞭解，在意圖之背景中，可能具有含有欲儲存在複數 頁中之資料的W R I Τ E指令，或者從複數頁要求資料之R E A D 資料封包。換言之，上述之位址可例如為一實體位址區域 之複數頁部分的起始位址。 【實施方式】 現在將參照以下圖式說明本發明之較佳具體例，其僅作 為例示用途。 現在將說明本發明之第一具體例。其可具有相同於圖1 所示之實體結構，因此，具體例之對應元件將以相同於圖 1使用之元件符號表示。所有顯示的元件可包含於一單一 殼體中，例如一個安裝有USB連接器3的殼體。USB連接 器3 (例如U S B插頭）可插入主機電腦5之一 U S B插座4， 藉以直接連接至一主機電腦（例如一個人電腦（P C ))。或 者，可在二者之間附接一纜線。應注意，此裝置亦可具有 圖1中未明確顯示之特徵，但為公開可得之可攜式資料儲 存裝置所習知者，例如密碼保護、利用指紋核對進行存取 控制等。此等特徵之實施係為熟習此項技術者所知。 圖3顯示第一具體例所使用的記憶體位址對映表。此表 係儲存於主控制單元7的揮發性R A Μ記憶體中。左欄2 1 係為標示邏輯位址區域之索引，右欄2 3係為標示實體位址 16 312/發明說明書(補件)/93-08/93115289 200525438 空間之區塊的編號，其係以一對一的方式對映於該等邏輯 位址區域。為了簡化起見，假設邏輯位址區域的數量為8 (標示為索引0至7 )，區塊的數量為1 6 (標示為索引0 至1 5 )。實際上，此等數量將會高出非常多。因此，每一 邏輯位址區域中可儲存的資料量為5 1 2位元組（假設此為 頁的尺寸）乘以每區塊的頁數（例如6 4 )。右攔的每一列 僅儲存一索引，標示一對應區塊。邏輯位址區域的數量對 應於任一時間用於儲存資料之區塊數量。 例如，由於其假設每區塊有6 4頁，邏輯位址6 7係關於 邏輯位址區域1中的一頁。這是因為邏輯位址區域0的頁 具有邏輯位址〇，1， ... 6 3，而邏輯位址區域1的頁具有邏 輯位址6 4，6 5，... 1 2 7，故邏輯位址6 7係為邏輯位址區域1 中的第四位址。在圖3所示的對映關係中，邏輯位址區域 1係對映至區塊1 0。 除了對映於邏輯位址區域之區塊，實體位址空間包括有 數個其他區塊（在以上所示之範例中為8 )。此等包括保留 區塊6、1 2與1 3，及「損壞」區塊7 (無法運作）。因此， 此等位址未出現於圖3之對映表中（雖然具體例較佳亦具 有一髒區塊表及一保留區塊表，用於以習知方式執行習知 可攜式儲存裝置中之其他操作）。這留下數個區塊（此實施 例為四個）可用於成為對映於邏輯位址區域。 此等區塊稱為「貯列區塊」，其在圖3之記憶體位址對 映表中顯示為2 5。此等區塊係處於擦除狀態。當一區塊從 貯列的頂端移除時，所有其他區塊往上移一列；然後一新 17 312/發明說明書(補件)/93-08/93115289 200525438 區塊插入區段2 5的最下面一列。為方便起見，其實施方式 可在一記憶體中配置四個位置，每一者儲存一個索引，並 具有一指標，指示四個位置的其中一者。指標所指的位置 係邏輯上均等於區塊2 5的「最上面一列」。因此，移除索 引及區段25的「最上面一列」，並將一新索引寫入區段的 「最下面一列」，係對映於將新索引覆寫到指標所指之位 置，並以循環（r 〇 u n d - r 〇 b i η )方式指到下一個位置。 對映至一對應邏輯位址區域之每一區塊之第一頁的控 制資料儲存區1 1包括有對應邏輯位址之索引（若儲存此索 引所需的位元數大於第一頁之區1 1中可利用的位元數，則 索引可被編碼並儲存在對應於區塊之一個以上之區1 1 中）。因此，若裝置電源關閉（使得圖3之記憶體位址對映 表從RAM消失），當裝置再度供應電源時，主控制單元7 可利用控制資料儲存區1 1所儲存的索引，而在其RAM中重 新產生記憶體位址對映表。 現在參照圖4所示之流程圖考慮第一具體例之操作。在 步驟1中，接收到一指令，在步驟2中，主控制單元7判 斷其係為R E A D指令或W R I T E指令。 假設指令係為R E A D指令，欲從邏輯位址6 7開始讀取資 料。在步驟3中，主控制單元7利用圖3之記憶體位址對 映表，決定對應於含有邏輯位址之對應邏輯位址區域的對 應區塊（即區塊1 0 )，及區塊中對應於邏輯位址之頁（即 第四頁）。然後，在步驟4，根據習知技術執行讀取操作： 主控制單元7發出一命令至記憶體單元9，從區塊1 0提取 18 312/發明說明書(補件)/93-08/93〗15289 200525438 第四頁所儲存的資料；此資料係經由匯流排8而從記憶體 單元9傳送到主控制單元7 ;主控制單元將此形成一或多 個封包，並傳出裝置。 假設主控制單元接收到一 W R I T E指令，欲從邏輯位址6 7 開始寫入某資料。在步驟5中，主控制單元7判斷對應於 邏輯位址之區塊及頁（如同步驟3 )，在步驟6中，主控制 單元判斷此頁處於擦除或未擦除狀態。可利用一檔案管理 系統達成（例如，利用前述習知技術中的區塊定位表）。 若區塊1 0的第四頁係為擦除，則根據習知技術，主控 制單元7發送一寫入指令到記憶體9，使記憶體將資料儲 存在區塊10的第四頁中。 另一方面，若區塊1 0的第四頁係為未擦除，則在步驟8 中，主控制單元指示記憶體單元將區塊1 0的前三頁和區塊 1 0的最後6 0頁中所儲存的資料複製到一新區塊。此新區 塊係為貯列區塊2 5的第一個，亦即區塊4。然後，在步驟 9中，W R I T E指令中所包含的資料被寫到區塊4的頁4。然 後，在步驟1 0中，記憶體位址表重設為圖5所示的形式。 亦即，區塊4現在係關聯於邏輯位址區域1。區塊1 0被擦 除，並放入貯列2 5的後面。由於貯列中有四個區塊，主控 制單元被指示將資料寫入未擦除頁發生三次之後，區塊1 0 可被重新使用。請注意，步驟8到1 0的操作可依據實施方 式而以其他的順序執行。 請注意，利用一檔案管理系統的另一種方案係使裝置省 略步驟6與7，而直接從步驟5到步驟8。換言之，每當接 19 312/發明說明書(補件)/93-08/93 Π 5289 200525438 收到一寫入指令時，都會執行複製步驟8到1 0。 圖6顯示本發明之第二具體例。在第一具體例中，8邏 輯位址區域的每一者係對映到一個別區塊，而在第二具體 例中，邏輯位址區域（此實施例中仍為8個）的每一者係 對映到一對應區塊群組（此實施例中為四個區塊）。在此實 施例中，區塊的數量等於6 4，以索引0到6 3標示。區塊 6 0、6 1、6 2與6 3係作為保留區塊。區塊9、1 7、1 8與2 7 假設為損壞區塊。損壞群組係在圖6 ( a )所示的「髒表」中 指定。此表可在裝置第一次供應電源時藉由測試所有區塊 並找出損壞區塊而產生；依照此方式，可確保所定義的保 留區塊不會包含損壞區塊。然後，損壞區塊表典型地係儲 存在一或多個保留區塊中；或者，其可在每次裝置供應電 源的時候重新產生。 記憶體位址對映表係顯示於圖6 ( b )。在此例中，每一個 邏輯位址區域0到7 (左欄3 1 )係對映於一群組編號（中 間攔3 3 )。共有1 2個群組可用來對映到個別之邏輯位址區 域，此等群組係以個別群組索引0到1 1標示。 大部分的群組（假設索引為i )係由一組區塊4 i - 4、 4 i - 3、4 i - 2及4 i - 1所組成。然而，有些區塊屬於此簡單 規則的例外，因為依照此規則，群組會包含一或多個損壞 區塊。定義此種群組的區塊係設定在「乾淨表」中’如圖 6 ( c )所示。 例如，群組1係為前四個區塊0、1、2與3。群組2係 為第二組四個區塊4、5、6與7。然而，群組3非為區塊8、 20 312/發明說明書(補件)/93-08/93115289 200525438 9、1 0與1 1，因為如上所述，區塊9係為損壞區塊。而， 圖6 ( c )的乾淨表指示群組3係由區塊8、5 9、1 0與1 1所 組成。群組4根據一般規則係為區塊1 2、1 3、1 4與1 5。 群組5再度為一般規則的例外（因為區塊1 7與1 8係為損 壞區塊），根據乾淨表，其係由區塊1 6、5 8、5 7與1 9所組 成。群組6係再度為正常，亦即，區塊2 0、2 1、2 2與2 3。 群組7再度為不正常（因為區塊2 7係為損壞區塊），根據 乾淨表，其係為區塊2 4、2 5、2 6與5 6。群組8到1 1係依 據一般規則。 因此，此實施例中，乾淨表僅定義三個群組的内容：群 組3、5與7。事實上，在典型的具體例中，損壞群組的比 例非常低，因此乾淨表比記憶體位址對映表小很多。乾淨 表的最大列數係為損壞群組的數量。 為了指示群組3未依照規則，記憶體位址對映表在第三 欄3 7中含有一旗標，及在第四欄3 8中含有一對應指示， 要參照圖6 ( c )的哪一列以獲得群組的正確内容（在圖6 ( b ) 中，第四欄38的值分別為0、1、2，這三個值分別標示圖 6 ( c )之乾淨表的三列）。 當主控制單元接收到一 WR I TE指令指示其將某資料寫入 邏輯位址6 7時，在此例中，其定義邏輯位址係在邏輯位址 區域0中（因為邏輯位址區域0係為邏輯位址0至2 5 5 )。 圖6 ( b )中，邏輯位址與群組之間的對映關係顯示對應群組 為群組2。欄3 7中的對應旗標並未設定，因此不需要參照 乾淨表來識別對應於群組2之區塊：依照規則係為4、5、 21 312/發明說明書(補件)/93-08/93115289 200525438 6與7。因此邏輯位址6 7係為區塊5的第四頁。 若此頁係處於擦除狀態，則來自W R I T E指令的資料被寫 入到該頁中。 若此頁非處於擦除狀態，則W R I T E指令中的資料係寫到 貯列2 5上端之群組之第二區塊的第四頁，亦即群組7。然 後，圖6 ( b )的記憶體位址對映表更新成圖6 ( d )，其方法係 將貯列上端的群組編號（亦即群組編號7 )移到攔3 3中對 應於邏輯位址區域0的列，並將指示區塊7為不規則的旗 標複製到第三欄3 7的相同列中，且將指示乾淨表之列的對 應資料複製到第四欄3 8的新列中。區塊4、5、6與7之其 他頁所儲存的任何資料係分別複製到群組7的對應頁（亦 即，分別為區塊2 4、2 5、2 6與5 6的各頁）。 若接著接收到對於邏輯記憶體位址6 7的讀取指令，則 主控制單元7再度確認其對應到邏輯區域0，因此檢查圖 6 ( d )之記憶體位址對映表中的對應列。此時，其可從欄3 3 發現對應群組為7，且欄3 7中的旗標指示此群組係為不規 則。欄3 8指示群組係在圖6 ( c )之乾淨表的列2中（亦即， 最後一列）。因此，主控制單元從圖6 ( c )之乾淨表提取此 列之區塊（亦即區塊2 4、2 5、2 6、5 6 )。其係從群組7的 第二區塊之第四頁（亦即區塊2 5 )讀取資料，產生一或多 個編碼有該資料之資料封包，並經由介面3而將封包傳出 裝置。 如果再度接收到對於邏輯記憶體位址6 7之寫入指令， 主控制單元7再度檢查圖6 ( d )之記憶體位址對映表中的對 22 312/發明說明書(補件)/93-08/93115289 200525438 應位置。此時，其發現對應群組為7，且欄3 7中的旗標指 示此群組係為不規則。因此，主控制單元從欄3 8提取對應 列數（亦即2 )，並從圖6 ( c )的乾淨表獲得此列的區塊（亦 即區塊2 4、2 5、2 6、5 6 )。其檢查群組7的第二區塊的第 四頁（亦即區塊2 5 )，查看資料是否儲存在其中（按照以 上說明之歷史，當然有資料）。因此，將群組之其他頁中所 儲存的資料移動到現在位於貯列3 5上端之群組的對應頁 (亦即群組4 )，並將W R I T E指令的資料寫到此群組之第二 區塊第四頁。然後，在欄3 3的最上面一列插入數字4，將 對應於群組4的（空白）旗標複製到欄3 7的最上面一列， 將對應於群組4的（空白）資料複製到攔3 8的最上面一列， 將索引7插入表之區段3 5的最後一列（已將其他列上移一 列），將對應旗標複製到欄3 7的最後一列，並將對應資料 複製到攔38的最後一列。 請注意，此步驟流程幾乎相同於圖4。然而，應瞭解， 步驟3與5現在較為複雜。區塊並非僅由邏輯位址與記憶 體位址對映表（例如圖3 )來確認，而是利用記憶體位址 對映表（例如圖6 ( b )與6 ( d ))來獲得一對應群組，並判斷 群組之區塊（依據規則，或者，若記憶體位址對映表的欄 3 7存在有旗標，則由圖6 ( c )的乾淨表之欄3 8所指示之 列），藉以達到確認。再者，在此例中，步驟8、9之參照 第一貯列區塊應解釋為參照第一貯列區塊群組（亦即，記 憶體位址對映表之區塊3 5的頂端之群組）。 這可說明第二具體例如何運作邏輯位址區域與個別區 23 312/發明說明書(補件)/93-08/93115289 200525438 塊群組之間的對映關係。一邏輯上獨立的問題在於具體例 如何將任何給定之邏輯位址區域中的邏輯位址對映於對應 區塊群組中的個別頁。 一種可能性係用於吾人稱為「水平」之對應。這表示區 塊的連續頁對應於連續邏輯位址。每一區塊（群組之最後 區塊除外）的最後一頁對應於群組之下一區塊之第一頁的 所對應的邏輯位址之前的連續邏輯位址。因此，例如’略 大於單一區塊之頁數之資料量將會以下列方式寫入記憶 體，亦即資料的起始處係寫入一邏輯位址所指定的一頁， 然後寫入區塊的連續頁，直到區塊耗盡，然後其餘部分的 資料係寫入下一區塊的第一頁。 然而，這並非唯一的可能性。在本發明第二具體例的較 佳形式中，主控制單元可運作使得邏輯對應關係區塊群組 之頁的位址邏輯對應係為「垂直」的。具體言之（假設， 舉例而言，一特定群組中有四個區塊），前四個邏輯位址可 對映到每一區塊的第一頁（亦即，第一邏輯位址對映於群 組之第一區塊的第一頁；第二邏輯位址對映於群組之第二 區塊的第一頁；等等），接下來四個邏輯位址可對映於每一 區塊的第二頁（亦即，第五邏輯位址對映於群組之第一區 塊的第二頁；第六邏輯位址對映於群組之第二區塊的第二 頁；等等）。 換言之，主控制單元7將四個連續邏輯位址組視為分別 對應於個別區塊的個別頁。沿個別區塊之頁水平計算測 量，關聯於一特定邏輯位址組的頁均具有相同偏移值（亦 24 312/發明說明書(補件)/93-08/931〗5289 200525438 即，此等頁形成實體位址空間的一 「攔」）。 圖6 ( e )顯示一特定資料量欲寫入群組2之一位置 (亦即區塊4、5、6與7 )。相對於對應於區塊4第 邏輯位址，寫入資料之起始邏輯位址具有一偏移為 即，寫入資料之起始邏輯位址係為群組之第一頁之 頁。這些頁在圖6 (c )中係垂直地計算（亦即，首先 欄的頁往下算，接著由下一欄往下算）。因此，具有 1 7的頁係以「A」表示。 在寫入操作中，來自舊群組之資料係複製到斜線 所指示的群組2中的位置。然後，寫入封包中的資 入斜線區域34中（亦即從位置A開始）。然後，舊 區域3 4之後的無斜線區域3 6中的任何資料係複製 34 ° 現在說明本發明之第三具體例。第三具體例類似 具體例，但有一項（重要）差異。在第三具體例中 W R I T E指令使得記憶體位址對映表所定義的對映關 變，並且使得W R I T E指令所含有之資料欲寫入到成 於邏輯位址之新區塊之一位置，此時，將舊區塊其 複製到新區塊之操作係部分地懸置一預定時間，以 是否有接收到任何關於記憶體空間之相同區域的新 指令。 具體而言，假設接收到一 WR I TE指令，指示資料 到某一邏輯位址。假設邏輯位址係位於目前對應於 之邏輯位址區域中。進一步假設邏輯位址對映於區 3丨2/發明說明書(補件)/93-08/93115289 的情況 一頁之 1 7。亦 後的1 7 由第一 偏移為 區域32 料係寫 區塊中 到區域 於第一 ，在一 係改 為關聯 餘資料 便查看 WRITE A欲寫 區塊0 塊0的 25 200525438 頁4。進一步假設（圖3之）貯列2 5頂端的擦除區塊係為 區塊3。圖7 ( a )顯示包含區塊0與3之部分實體記憶體。 亦即，區塊0具有標不為X的貢料儲存在頁0到3、標示 為Y之資料儲存在頁4、標示為Z之資料儲存在頁5到7， 然後區塊的其餘部分係處於擦除狀態（顯示為「〇」）。 根據第一具體例，此W R I T E指令會立即使得區塊1與3 的實體記憶體變成如圖7 (b )所示。亦即，新資料A儲存在 頁4，資料X與Z儲存在區塊3中的頁數對應於其先前在 區塊0之頁數。區塊0將會被擦除（代表其之索引將會位 於圖3之區段2 5的底部）。 然而，本發明之第三具體例中，實體記憶體一開始係重 新寫入成如圖7 (c )所示。亦即，資料A寫入區塊3的頁4， 資料X複製到頁0至3，但資料Z尚未複製到區塊3的頁5 至7。系統藉由一計時器在此種組態維持一段時間期間。 如過在此期間結束前，沒有接收到另外之關於對應於區塊 3之頁5的邏輯位址之W R I T E信號，則完成寫入操作，使 資料儲存如圖7 ( b )所示。然而，在此期間内，若接收到一 W R I T E指令，指示資料B欲儲存到現在對應於區塊3之頁5 的邏輯位址，則使資料儲存如圖7 ( d )所示。然後計時器重 新啟動以定義新的時間期間。 若在此期間結束前，沒有收到另一關於對應於區塊3之 頁6的邏輯位址之W R I T E信號，則完成寫入操作，使得資 料儲存如圖7 ( e )所示。然而，若在此期間接收到一新W R I T E 指令，指示資料C欲儲存到現在對應於區塊3之頁6的邏 26 312/發明說明書(補件)/93-08/93 U 5289 200525438 輯位址，則將此資料B寫到區塊3的頁6，並重新啟動計 時器。 此過程可持續到區塊3的最後一頁，或者，直到時間期 間經過，卻沒有接收到一 W R I T E指令指示資料欲儲存在接 續前一 W R I T E指令所指定之位置之頁。請注意，這表示資 料A、B、...可比第一具體例更快速地寫到記憶體裝置中， 因為複製資料的需求減少。例如，在上述一連串步驟中’ 不論後續接收到多少關於連續頁之W R I T E指令，資料X只 需要在開始時複製一次。 流程圖係顯示於圖8，其與圖6之差異僅在於步驟8至 1 0取代成步驟8至1 3。在圖8的步驟8中，舊區塊中（亦 即區塊0 )，只有所接收之W R I T E指令相關之頁以前的頁數 被複製到新區塊（亦即區塊3 )，而W R I T E指令中的資料係 寫到對應於邏輯位址之新區塊中的頁。步驟9中，判斷新 區塊的最後一頁是否已被寫入。若是，則裝置進行到步驟 1 3。否則，在步驟1 0中，裝置判斷在一預定時間之内是否 接收到一關於新區塊之下一連續頁的新W R I T E指令。若 是，則具體例在步驟1 1中將資料寫到該處，並回到步驟9。 若否，則在步驟1 2中，具體例複製舊區塊之其餘頁（亦即， 關於所接收到W R I T E指令之最後一頁之後的所有頁，如果 有的話）。步驟1 3對應於圖4的步驟1 0 :擦除舊區塊（區 塊0 )，並更新記憶體對映位址表。 請注意，當具體例進行到步驟1 0的時候，若接收到一 READ指令，其係關於目前圖8之流程的目標邏輯位址區域 27 312/發明說明書(補件)/93-08/93 ] 15289 200525438 中的一邏輯位址，則裝置應從實體記憶體中的正確位置讀 取資料（亦即，如果邏輯位址對應於步驟8中寫入的位址， 或者，如果邏輯位址對應於先前步驟9中寫入之位址，則 從新區塊讀取；否則從舊區塊讀取）。 在本具體例的某些形式中，如步驟1 0中，若其判斷一 接收到的新W R I T E指令指示資料欲寫入任何非為新區塊之 下一連續頁之邏輯位址，則裝置亦會從步驟1 〇進行到步驟 1 2。在此種情況中，新W R I T E指令的處理可在圖4之流程 完畢之後開始進行。 請注意，計時器典型地係設定成數毫秒的期間，例如約 3ms。若在接收到最後WRITE指令之後的預定期間内，裝置 與主機的連接切斷，則會有資.料遺失的危險。然而，將預 定期間設定成毫秒的級次，則不會發生此問題，因此所有 資料將可安全地儲存。請注意，本發明第三具體例若將預 定期間限制成零，則簡化成第一具體例。 現在將說明本發明之第四具體例。如同第三具體例，第 四具體例使用一計時器。 此例中，主控制單元7包括一模式辨識單元，其接收主 控制單元從W R I T E指令所提取的邏輯位址資料。在一特定 操作階段中，若圖案辨識單元注意到一特定邏輯位址比預 期還要頻繁地出現，則將該邏輯記憶體位址寫入「經常使 用邏輯位址」空間，例如，定義於主控制單元之RAM位址 中。更一般的情況，經常使用邏輯位址空間可含有複數個 此種高頻率之識別邏輯位址。模式辨識單元可予以程式 28 312/發明說明書(補件)/93-08/93115289 200525438 化，能夠在邏輯位址的頻率減少時，將邏輯位址從此空間 刪除，及/或每當一邏輯位址被鑑定為具有更高使用頻率 時，在空間中將其取代。因此，空間可持續儲存最經常發 生在W R I Τ E指令中的邏輯位址。 主控制單元7提供一快取RAM記憶體用於經常使用位址 空間的中的每一位置。當接收到一關於經常使用邏輯位址 空間中所儲存的一位址之W R I Τ E指令時，主控制單元不會 一開始就將W R I Τ E指令中所包含的資料寫入快閃記憶體裝 置。而是將該資料寫入到對應快取記憶體中。然後，主控 制單元7等候一段由計時器所決定之時間。在該時間内， 若沒有接收到其他WR I TE指令（或者，在一種形式之具體 例中，若接收到關於另一區塊之封包），則主控制單元依據 上述本發明第一至第三具體例中任何一種步驟，而將快取 記憶體中的資料寫入到快閃記憶體中。另一方面，在預定 期間中，若接收到關於相同邏輯位址之另一 W R I Τ E指令， 則主控制單元將W R I Τ E指令中所包含的資料寫入其快取記 憶體的相同位置（亦即，覆寫到第一寫入封包所寫入的資 料）。然後將計時器重新啟動。 因此，由此可知，若裝置接收到大量之關於相同邏輯記 憶體位址之W R I Τ E指令，其平均時間間隔低於計時器所設 定的預定時間，則此等WR I TE指令產生對記憶體裝置9的 (計算昂貴）寫入操作次數將會很低。 主控制單元7之部分結構係顯示於圖9。主控制單元7 包含一區段5 1用於將一 W R I Τ E指令分成一邏輯位址及欲寫 29 312/發明說明書(補件)/93-08/93115289 200525438 到該邏輯位址之資料。邏輯位址係傳送到一模式辨識單元 5 3，其可利用它來持續更新一經常使用位址空間5 5。主控 制單元具有一開關5 7，其判斷所接收之WR I TE指令之邏輯 位址是否在經常使用位址空間5 5中。若否，則資料與邏輯 位址立即寫入到單元5 7中，單元5 7依據第一具體例之方 法將其寫入快閃記憶體9。若是，則資料被寫入一快取記 憶體5 9，且設定計時單元6 1開始運作。若計時單元61中 的計時器達到預定期間之結束而未受到重設，則資料及對 應邏輯位址係藉由開關5 7而從快取記憶體5 9傳送到單元 5 7。請注意，雖然圖9 ( a )僅顯示一單一計時單元6 1，但該 計時單元6 1通常針對經常使用邏輯位址空間中的每一個 別邏輯位址設有一個別計時器，並且，針對每一此等邏輯 位址設有一個別之快取記憶體位置。 若接收到一 R E A D指令，一單元6 3會判斷邏輯位址是否 為經常使用位址空間中所儲存的一位址，若是，則判斷對 應計時器是否正在運作。若是，其從對應快取記憶體5 9 讀取資料；否則，其利用一單元6 7依據記憶體位址對映表 所定義的對應關係而從快閃記憶體9讀取資料（亦即，依 據第一具體例之方法）。在任一種情況中，其將資料編碼成 一封包，並透過介面3傳出裝置。 此具體例之流程圖係為圖3之流程圖，但圖9 ( b )之步驟 係插入圖3的步驟2與3之間（由單元5 1與5 7執行），圖 9 ( c )之步驟係插入圖3之步驟2與5之間（由單元6 3執 行）。在步驟7與9中，寫到頁中的資料係為最後接收到之 30 312/發明說明書(補件)/93-08/93115289 200525438 關於該邏輯位址的W R I T E指令。 每當單元5 3從經常使用邏輯位址空間（亦即更新單元 5 5 )移除一邏輯位址時，快取記憶體5 9之對應位置中的資 料係依照圖3之步驟5至1 0而寫到記憶體9。 在本發明第三及/或第四具體例之任一者中，計時器可 配置成使得預定期間僅為數毫秒，例如約3ms。若在接收 到最後W R I T E指令之後的預定期間内，裝置與主機的連接 切斷，則會有資料遺失的危險。然而，將預定期間設定成 毫秒的級次，則不會發生此問題，因此所有資料將可安全 地儲存。請注意，本發明第三與第四具體例若將預定期間 限制成零，則簡化成第一具體例。 請注意，上述之具體例沒有任何一者需要一區塊定位表 (雖然其他具體例可能利用到此種表）。 雖然此處僅詳細說明本發明之數個具體例，熟習此項技 術者可在本發明之範圍内進行許多可能的變化。例如，第 二、第三與第四具體例之特徵可輕易地以任何組合方式結 合，甚至較佳結合所有上述特徵（包括區塊群組之頁的垂 直填入）。因此，本發明之具體例可形成邏輯位址區域對應 到複數個區塊所組成之個別群組，其中一特定邏輯位址區 域内的邏輯位址係對應於一區塊群組中的欄，其中一第一 計時器信號係用於懸置一舊群組到一新群組之資料複製， 且其中一第二（選擇性地不同）計時器信號係用於懸置一 W R I T E指令中所包含之資料寫入到快閃記憶體裝置9中。 再者，上述具體例中，僅具有一單一 NAND快閃記憶體 31 312/發明說明書(補件)/93-08/93115289 200525438 裝置。然而，本發明並不限於此種態樣，而可具有多於一 個之N A N D快閃記憶體裝置，依據上述本發明之原理運作。 例如，每一 N A N D記憶體裝置可關聯於邏輯位址空間之一特 定個別部分，針對每一 NAND記憶體裝置，在該記憶體裝置 之區塊與邏輯位址空間之對應部分的個別區域之間具有一 可變對映關係。 如上所述，本發明可經由一 USB連接而實施，但其並不 限於此種態樣。較佳地，USB控制器所使用之USB標準係 為U S B 2 . 0版本，但本發明亦可以其他U S B標準版本實施， 例如未來所制定的任何版本。 裝置的總記憶體容量不限制於本發明之範圍内，但較佳 為至少1 Μ位元組，更典型為至少1 0 Μ位元組、至少1 0 0 Μ 位元組或甚至至少 1 G位元組。 【圖式簡單說明】 圖1顯示習知可攜式資料儲存裝置的第一構造圖； 圖2顯示圖1之習知裝置的NAND快閃記憶體裝置之實 體記憶體空間； 圖3顯示本發明第一具體例之記憶體位址對映表； 圖4係為本發明第一具體例所執行之步驟流程圖； 圖5顯示在一特定資料寫入操作之後的圖3之記憶體位 址對映表； 圖6包含圖6 ( a )至6 ( e )，其顯示本發明之第二具體例； 圖7包含圖7 ( a )至7 ( e )，其顯示本發明之第三具體例 在個別時間之實體記憶體狀態； 32 312/發明說明書(補件)/93-08/93115289 200525438 圖8係為圖7之具體例的操作流程圖；及 圖9包含圖9 ( a )至9 ( c )，其例示本發明之第四具體例。 (元件符號說明） 1 可攜式儲存裝置 2 USB控制器 3 USB介面 4 USB介面 5 主機電腦 6 頁 7 主控制單元 8 匯流排 9 快閃記憶體 10 區塊 11 控制資料儲存區 12 線 2 1 左欄 23 右欄 2 5 貯列區塊 31 左爛 3 2 斜線區域 33 中間欄 3 4 斜線區域 35 區段 3 6 無斜線區域 312/發明說明書(補件)/93-08/93115289 33200525438 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a portable data storage device, and a method for using the device and retrieving written data. [Previous Technology] In the past few years, the provision of data storage devices that contain flash memory and can be connected to a computer's bus has received increasing attention. The leading technical document in this field is W 0 0 1/6 1 6 9 2 which reveals a one-piece device that was later marketed as "Thumbdrive". In one of this document, the male USB plug installed on the casing of this device is directly connected to the female USB socket in the brain, enabling the computer to transfer data back and forth to the portable storage device under the control of the USB controller Flash memory. Various improvements have been proposed for needle devices. For example, W 0 0 3/0 0 3 2 8 2 can be provided with a fingerprint sensor. Only after the fingerprint sensor compares the use of the fingerprint with the pre-stored data to verify the identity of the user, the device will be taken from the device. Stored data. The contents of these documents are described for reference. The structure of such a portable storage device is shown in FIG. 1. The portable storage is labeled 1 and has a housing, indicated by a dashed line. It includes a controller 2 controlling a USB interface 3 (for example, a USB plug), which is connected to a USB interface 4 (for example, a ϋ S B socket) of the host computer 5. The data transmitted from the computer 5 to the USB interface 3 passes through the USB controller 2 to a main control unit 7. There are various types of data packets. Includes WRITE data package, which contains 312 / Invention Specification (Supplement) / 93-08 / 93115289 A string of trademarks stored under a system. This display can be stored by the user under the electrical system. USB storage can be directly transmitted from the host. There are 6 200525438 WRI T E instructions that write the data volume in multiples of 5 1 2 bytes to a specific logical address. It also includes a R E A D data packet, which contains a R E A D instruction to read data from a specific logical address. The W RI TE instruction generally contains a logical address of the location where the first part of the data must be written, an indication of how much data is to be written, and the data to be written. Passing a W RI ET instruction may require several data packets. Similarly, a READ instruction indicates the logical address to be read initially, and an indication of how much memory to read from there. The main control unit 7 executes these instructions by controlling a NAND flash memory 9. The main control unit 7 can control the N A N D flash memory 9 by transmitting command symbols using one or more lines marked as 12 in the schematic diagram. Typically, these lines 12 and 2 include a line for transmitting a WR I TE signal when data is to be written to the flash memory 9, and a line for transmitting data when the flash memory is to be transmitted to the main control unit 7. READ signal, multiple lines are used to transmit an address signal, indicating the position where data should be written in memory, or the position where data should be read from memory, and an ENABLE signal, which must be set to a certain value, fast Flash memory can work. When the main control unit 7 needs to store the data in the flash memory 9, it transmits the data via an 8-bit bus 8 while transmitting the W RI TE command, the E N A B L E signal and the address. The address is a physical address (that is, a specific address in the memory unit 9), and the physical address is based on a pair stored in the RAM memory in the main control unit 7 or accessible to the main control unit 7. The mapping table corresponds to the logical address. In response to a READ command, the data will be transmitted from the device. It is transmitted from the NAND flash memory 9 in a 5 12-byte packet, and is transmitted to the main control unit 7 via the 8-bit bus 8. . Main control 312 / Invention specification (Supplement) / 93-08 / 93] 15289 200525438 The control unit transmits a 5 1 2-byte packet to the USB controller 2, which transmits the packet from the device 1 to the host through the USB interface 3. 5. This device is known to supply power through the USB interface 3. When the USB interface 3 is removed from the USB socket of the computer, the power of the device is turned off. All data stored in the RAM of the main control unit 7 will disappear. FIG. 2 shows the memory space of the NAND flash memory 9. The structure of this device can store 5 1 2 byte sections of data in each "page" 6 (please note that there are other possibilities, such as storing 2 kilobytes per page), and each page also contains a An individual control data storage area 11 is used to store control data (typically 16 bytes). The data is arranged in "block" 10 (that is, the columns in Fig. 2). For example, each block 10 has 6 4 pages 6. There are three limitations of the conventional N A N D flash memory: 1. Any particular page is either in the "erased" state or in the "unerased" state. In the "erased" state, data can be written to the page. In the "unerased" state, the page stores Data, and different data cannot be written on this page. These pages can only transition from the unerased state to the erased state in the unit of block (b 1 〇ck-by-b 1 〇ck), that is, all unerased pages of a particular block must be changed once Erase and lose all data stored in it. 2. A particular block or page has a limited life cycle. In other words, the transition from the erased state to the unerased state can only be performed a limited number of times, such as 10, 0 0 0 or 10, 0 0 times. This will limit the life of the memory device. 3. N A N D Flash memory sometimes has "corrupted" blocks, which means that data cannot be reliably written to it. 8 312 / Invention Manual (Supplement) / 93-08 / 93115289 200525438 As mentioned above, the address of the data written in or read out of the NAND memory device 9 is the data packet received by the USB interface 3. A logical address determined in the encoding. Conventionally, the main control unit must access a table for storing addresses in the logical address space and locations in the physical memory space that are not in the memory device block in the dirty table (e.g. dirtytab 1 e) ( Which is a mapping relationship between "physical addresses" in memory. Specifically, each block is mapped to a different area of the logical address space, and has the same number of addresses as the number of pages. This antipodal system is fixed. Therefore, the damaged block is not associated with any logical address. In addition to the damaged block, there are other blocks that are not associated with logical addresses. These are "reserved" blocks, which are used to store other data that may be needed by the portable storage device. For example, the dirty address table itself is stored in a reserved block. The main control unit 7 includes a file management system, including a block positioning table, which indicates that each block is in an erased or unerased state. , And how many blocks are in an erased or unerased state. When the main control unit 7 receives data at a position in a block in the memory, the main control unit 7 uses the block positioning table to find out whether the block is in an erased state. Conventionally, if the block is found in an unerased state, it will copy any data in the block that it does not want to be overwritten to a different location, erase the block, and then store the new block to be stored in memory. Write the data back to the block and copy the data to a different location. SUMMARY OF THE INVENTION The present invention provides a novel and practical portable data storage device. 9 312 / Invention Specification (Supplement) / 93-08 / 93115289 During the operation of setting, change the mapping relationship between regions between logical bits. A pair of memory regions is maintained over time. Generally, the known operations on the host computer are statistically related, which means that if the logical relationship is made, some physical addresses will be easily and quickly damaged. The relationship between physical addresses indicates a decrease. In essence, according to the relationship of the present invention, when an instruction is received to link a page, the logical address can be changed and the new block in the erased state is associated with the block, and any stored block in the old block. Therefore, the old data only needs to be copied twice. This makes the device's temporary mapping relationship based on a memory for speed, the memory address mapping (for example, in the main control unit itself). Data is stored in the flash memory itself. Multi-page control data storage area can store 10 200525438 In summary, the present invention proposes: the mapping relationship between the area of address space and the physical memory, the 'logical address area' and the entity record, but this mapping relationship This has several advantages. First, the inventors have noticed that the logical address generated by the system tends to have a fixed address and a physical address are more commonly used than other addresses. Therefore, the logical address and the need to write can be changed. The mapping relationship between the logical address of the data writing operation and the physical address is written to the physical address in an unerased state, making the logical address one. The new data is written into the newly stored unerased data and also written into the new copy once, instead of exposing the knowledge as above. The overall operation is accelerated. Defined by the physical address mapping table between the logical address and the physical address. For better operation, it is stored in RAM memory (for example, the definition of the mapping data is also better so that when the power is turned off, there is no special, one of a specific block or 312 / Invention Specification (Supplement) ) / 93-08 / 93115289 200525438 Store instructions to indicate which logical location area the block is currently associated with. When the device is connected to a host computer and the main control unit is supplied with power, the main control unit uses this information to generate the mapping Table (which can be stored in its cache memory when the mapping relationship changes so that the physical address mapped to a specific logical address area changes from a first block to a second block, the mapping table And the mapping data stored in the flash memory device will be updated. In the case of data stored in the flash memory, the method is only to remove the data that defines the mapping relationship from the first block before erasing The first block is copied to the second block. As mentioned above, in the known system, the logical address space is smaller than the physical address space because some blocks are not associated with any logical addresses. These are reserved blocks With damage In the present invention, in addition to the reserved block and the damaged block, at any time, there is another set of blocks (herein referred to as "storage block") that can be used to map to a logical address area instead of the current The block mapped to the logical address area. When the mapping relationship needs to be changed, one of the storage block will be selected to become associated with a logical address area. The storage block is more queued up in the storage queue. Jia is in an erased state, rather than being erased when it becomes associated with a logical address area. Update of memory address mapping (that is, selecting an erased second block to replace the mapping) A first block in the relationship) is executed whenever a new WRI T E instruction is received to write data to a location that is not a physical address in an erased state. It can be received at This WRI T E instruction is executed immediately. Or, in a preferred modification of the present invention, the main control unit executes the instruction in accordance with a specific WRI T E instruction 11 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438. Write operation can be suspended for a period of time Period, only when an instruction that meets a predetermined first instruction similarity standard is received during that period. Just as the concept of the variable address mapping table mentioned above is partly subject to statistically relevant observations of logical addresses This improvement is inspired by the following observations, that is, the commands received in a relatively short period of time are sufficiently strongly related that collective processing will be more efficient than individual processing. This can improve the portable data storage device. Speed and / or life. This operation is suspended in order to confirm whether there is another related WRI T E instruction to the concept, which constitutes another independent aspect of the present invention. In addition to using it in combination with a variable pair, it can also It is used within the scope of the present invention. A first such relationship is that a dense continuous write instruction specifies that data is to be entered into the same continuous logical area. In response to this, the main control device receives a first instruction, which specifies that the data is written into a logical address area, and the memory address mapping relationship is mapped to a specific first area of a physical record. At this time, the main control device is preferably suspended at least so that the data stored in the first block that is not overwritten is copied to the second block. If during this period, the main control device does not receive packets containing consecutive pages of data to be written to the block, it may continue the operation of copying the data in the first block to the second block. Alternatively, if one or more packets are received during this period, and other data is specified to be written elsewhere in the logical address area, the data of all packets may be written in the block. In this case, only the first The other data of one block is copied to the second block. A second such relationship is that the present inventor has noticed that the master control 3 丨 2 / Invention Specification (Supplement) / 93-08 / 93115289 often missed the meeting, and because the mapping table will be written Write and receive data according to the first instruction of the memory. If the same is entered in some devices, 12 200525438 will often receive a packet specifying the exact same logic with the WRITE instruction within a short period of time. Whenever a specific example specified by these instructions is received, the memory address mapping relationship will not be reset immediately, and this operation is suspended for a period of time. During this period, a data cache memory (such as a RAM cache memory) operated by the capital control device is operated. If no instruction of the logical address is received within this time period, the main control device will start to flash memory as described above. However, during this period, if a command is received (or, in another specific example, the master control device writes data to its cache memory (and passes its clock) for something other than the same logic. If a READ command is received about the same logic, the data is read from the cache memory, not the memory device. Alternatively, the cache memory may be large enough to store the reset address. That is, the cache memory can be divided into a plurality of sections for storing data about a corresponding logical address, and is associated with a separate timer for starting from receiving the logical WRITE instruction Measure the time. Preferably, the data storage device can distinguish which logical bit is often written (that is, it executes the recognition algorithm based on the input instructions), so that it can choose to consider it necessary to perform the first two fetch operations. One or more logical locations in a group. The above description assumes that each region to be associated with a logical address has a unique mapping relationship, but this requires a memory address pair 3 丨 2 / Explanation Book (Supplement) / 93-08 / 93115289 When the content of the address is included, this post is better stored, and the internal information about the same information is written to the address of the WRITE), often the reset address will be reset quickly. Flash a number of logical sections, and the address of each section is specially designed to identify the fast block mapping table as described in 13 200525438 at least as many as the number of blocks that can store data. Another way is to associate the logical address area with individual block groups. For example, blocks can be divided into (for example) every four blocks into a group (so there are a total of, for example, 4 X 6 4 2 2 5 6 pages), the logical address area would be a multiple of the antipodal coefficient (for example, Four times larger). In this case, the memory address mapping table defines a one-to-one mapping relationship between each group and another logical address region. A group can be simply continuous blocks, but in the case of any damaged block, it is better to have a more complicated block setting method to group non-damaged blocks. Then, the block group can be regarded as a physical memory area, which is related to the area of the logical address space. The main control unit can access a grouping table indicating the grouping, so that when a logical address is specified, a corresponding group can be determined by using the memory address table, and the grouping table can be used to identify the blocks constituting the group. Since there are very few damaged blocks, most groups can be set according to simple rules (for example, the group is set as four consecutive blocks as individual groups), and the grouping table only stores data for individual blocks that do not follow this rule. This will reduce the size required for grouping tables. For convenience, the fact that a particular logical address area is associated with any of these special groups may include a flag in the mapping address table. Therefore, the memory mapping table will indicate when the grouping table needs to be referenced to determine the physical address associated with a particular logical address. The main control unit can associate the logical addresses in a specific logical address area with the blocks of the corresponding group, so that the continuous logical addresses correspond to the "columns" of the page. This concept of grouping blocks to logical address areas, and 14 312 / Invention Specification (Supplement) / 93. / 93115289 200525438 The concept of associating consecutive logical addresses in a logical address area with the page of the page constitutes another independent aspect of the present invention. In addition to using it in combination with a variable map, it can also be used in the present invention. Use within range. A specific aspect of the first aspect of the present invention is a portable data storage device, including: (i) a data interface for transmitting data packets to or from the device, (ii) an interface controller, (iii) A) a main control unit, and (iv) at least one NAND flash memory unit, the interface controller is configured to transmit the received data to the main control unit through the interface, and the main control unit is configured to recognize certain The data packet is encoded with a READ instruction and other data packets are encoded with a WRITE instruction: (a) When a READ instruction indicating a logical address is received, a memory address mapping table is accessed. The memory address mapping table is A logical address region in a logical memory space is associated with an individual first physical address region in a memory unit, and is read from the physical address in the memory unit corresponding to the logical address according to the address mapping table. Data, and transmit one or more data packets including the read data to the data interface, and (b) when a WR is received indicating a logical address and the data to be written to the logical address When the ITE instruction, according to the memory address mapping table, confirm whether the physical address mapped to the logical address is in the erased state, and: if yes, write the data to the physical address, or if not, modify the address pair Mapping table, associates a second physical address area with 15 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 logical address area containing logical addresses, according to the modified memory address mapping table, The data is written to a physical address corresponding to the logical address, and data stored in other locations in the first physical address area is copied to corresponding locations in the second physical address area. It should be understood that in the context of the intention, there may be W RI TE instructions containing information to be stored on multiple pages, or R E A D data packets requesting information from multiple pages. In other words, the above address may be, for example, the start address of a plurality of page portions of a physical address region. [Embodiment] Now, a preferred specific example of the present invention will be described with reference to the following drawings, which is only used as an example. A first specific example of the present invention will now be described. It may have the same physical structure as shown in FIG. 1, and therefore, the corresponding components of the specific example will be represented by the same component symbols as those used in FIG. 1. All the components shown can be contained in a single housing, such as a housing on which the USB connector 3 is mounted. The USB connector 3 (such as a USB plug) can be inserted into a USB socket 4 of one of the host computers 5 so as to directly connect to a host computer (such as a personal computer (PC)). Alternatively, a cable can be attached between the two. It should be noted that this device may also have features that are not explicitly shown in Figure 1, but are known to publicly available portable data storage devices, such as password protection, access control using fingerprint verification, and the like. The implementation of these features is known to those skilled in the art. FIG. 3 shows a memory address mapping table used in the first specific example. This table is stored in the volatile RAM of the main control unit 7. The left column 2 1 is the index indicating the logical address area, and the right column 2 3 is the physical address 16 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 The number of the block in the space. One-to-one mapping to these logical address areas. For simplicity, it is assumed that the number of logical address regions is 8 (labeled as indices 0 to 7) and the number of blocks is 16 (labeled as indices 0 to 15). In fact, these numbers will be much higher. Therefore, the amount of data that can be stored in each logical address area is 5 1 2 bytes (assuming this is the size of the page) multiplied by the number of pages per block (for example, 6 4). Each row in the right block stores only one index, which indicates a corresponding block. The number of logical address areas corresponds to the number of blocks used to store data at any one time. For example, since it assumes 64 pages per block, logical address 67 is about one page in logical address area 1. This is because the page in logical address area 0 has logical addresses 0, 1,. . . 6 3, and the page of logical address area 1 has logical addresses 6 4, 6, 5 ,. . . 1 2 7, so logical address 6 7 is the fourth address in logical address area 1. In the mapping relationship shown in FIG. 3, the logical address region 1 is mapped to the block 10. In addition to the blocks mapped in the logical address area, the physical address space includes several other blocks (8 in the example shown above). These include reserved blocks 6, 12 and 13 and "damaged" block 7 (not operational). Therefore, these addresses do not appear in the mapping table of FIG. 3 (although the specific example is better, it also has a dirty block table and a reserved block table for performing the conventional portable storage device in a conventional manner. Among others). This leaves several blocks (four in this embodiment) available for mapping into logical address regions. These blocks are called "storage blocks" and are shown as 2 5 in the memory address mapping table in FIG. 3. These blocks are in an erased state. When a block is removed from the top of the storage column, all other blocks are moved up by one column; then a new 17 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 block is inserted into the top of section 2 5 The next column. For convenience, its implementation may be configured with four positions in a memory, each storing an index, and having an index indicating one of the four positions. The positions indicated by the indicators are logically equal to the "top row" of block 25. Therefore, removing the index and the "top row" of section 25, and writing a new index to the "bottom row" of the section is a reflection of overwriting the new index to the position indicated by the indicator, and The cycle (r und-r 〇 bi η) method refers to the next position. The control data storage area 1 of the first page of each block mapped to a corresponding logical address area includes an index corresponding to the logical address (if the number of bits required to store this index is greater than the area of the first page The number of bits available in 1 1, then the index can be encoded and stored in more than one area 1 1 corresponding to the block). Therefore, if the power of the device is turned off (making the memory address mapping table in FIG. 3 disappear from the RAM), when the device is re-powered, the main control unit 7 can use the index stored in the control data storage area 11 and store it in its RAM Memory address mapping table. Now consider the operation of the first specific example with reference to the flowchart shown in FIG. In step 1, a command is received, and in step 2, the main control unit 7 judges whether it is an R E A D command or a W R I T E command. Assume that the instruction is a R E A D instruction. The data is to be read from logical addresses 6 7. In step 3, the main control unit 7 uses the memory address mapping table of FIG. 3 to determine the corresponding block (ie, block 10) corresponding to the corresponding logical address area containing the logical address, and the corresponding block in the block. The page at the logical address (that is, the fourth page). Then, in step 4, the reading operation is performed according to the conventional technique: The main control unit 7 issues a command to the memory unit 9 and extracts 18 from block 10 0. 312 / Invention Specification (Supplement) / 93-08 / 93. 15289 200525438 The data stored on the fourth page; this data is transmitted from the memory unit 9 to the main control unit 7 via the bus 8; the main control unit forms one or more packets and sends them out of the device. Assume that the main control unit receives a W R I T E instruction and wants to write some data from logical address 6 7. In step 5, the main control unit 7 determines the block and page corresponding to the logical address (as in step 3). In step 6, the main control unit determines that the page is in an erased or unerased state. This can be achieved using a file management system (e.g., using a block positioning table in the aforementioned conventional techniques). If the fourth page of block 10 is erased, according to conventional techniques, the main control unit 7 sends a write instruction to the memory 9 to cause the memory to store data in the fourth page of the block 10. On the other hand, if the fourth page of block 10 is unerased, in step 8, the main control unit instructs the memory unit to change the first three pages of block 10 and the last 60 of block 10. The data stored in the page is copied to a new block. This new block is the first block of block 25, which is block 4. Then, in step 9, the data contained in the W R T E instruction is written to page 4 of block 4. Then, in step 10, the memory address table is reset to the form shown in FIG. That is, block 4 is now associated with logical address area 1. Block 10 is erased and placed behind bank 25. Since there are four blocks in the bank, the main control unit is instructed to write data to unerased pages three times before block 10 can be reused. Please note that steps 8 to 10 can be performed in other orders depending on the implementation. Please note that another solution using a file management system is to make the device omit steps 6 and 7 and go directly from step 5 to step 8. In other words, whenever a write command is received at 19 312 / Invention Specification (Supplement) / 93-08 / 93 Π 5289 200525438, the copying steps 8 to 10 are performed. Fig. 6 shows a second specific example of the present invention. In the first specific example, each of the 8 logical address regions is mapped to a different block, and in the second specific example, each of the logical address regions (still eight in this embodiment) This is mapped to a corresponding block group (four blocks in this embodiment). In this embodiment, the number of blocks is equal to 6 4 and is indicated by indices 0 to 6 3. Blocks 60, 61, 62 and 63 are reserved blocks. Blocks 9, 17, 7, 8 and 2 7 are assumed to be damaged blocks. The damage group is specified in the "dirty table" shown in Fig. 6 (a). This table can be generated when the device is first powered by testing all the blocks and identifying the damaged blocks; in this way, it can be ensured that the defined reserved blocks will not contain damaged blocks. The damaged block table is then typically stored in one or more reserved blocks; alternatively, it can be regenerated each time the device is powered. The memory address mapping table is shown in Figure 6 (b). In this example, each logical address area 0 to 7 (left column 3 1) is mapped to a group number (middle block 3 3). A total of 12 groups can be used to map to individual logical address areas. These groups are marked with individual group indexes 0 to 1 1. Most groups (assuming the index is i) are composed of a group of blocks 4i-4, 4i-3, 4i-2, and 4i-1. However, some blocks are an exception to this simple rule, because according to this rule, a group contains one or more corrupted blocks. The block defining this group is set in the "clean table" as shown in Figure 6 (c). For example, group 1 is the first four blocks 0, 1, 2 and 3. Group 2 is the second group of four blocks 4, 5, 6, and 7. However, group 3 is not block 8, 20 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 9, 10, and 11 because block 9 is a damaged block as described above. However, the clean table in FIG. 6 (c) indicates that group 3 is composed of blocks 8, 59, 10, and 11. Group 4 is block 1 2, 1 3, 1 4 and 15 according to the general rules. Group 5 is again an exception to the general rule (because blocks 17 and 18 are damaged blocks), according to the clean table, it is composed of blocks 16, 5, 8, 57 and 19. Group 6 is normal again, that is, blocks 20, 21, 22, and 23. Group 7 is abnormal again (because block 2 7 is a damaged block), according to the clean table, it is block 2 4, 2 5, 2 6 and 5 6. Groups 8 to 11 are based on general rules. Therefore, in this embodiment, the clean table only defines the contents of three groups: groups 3, 5 and 7. In fact, in typical examples, the percentage of corrupted groups is very low, so the clean table is much smaller than the memory address mapping table. The maximum number of columns in a clean table is the number of corrupted groups. In order to indicate that group 3 does not follow the rules, the memory address mapping table contains a flag in the third column 37 and a corresponding indication in the fourth column 38. Which column of FIG. 6 (c) is to be referred to? To obtain the correct content of the group (in Fig. 6 (b), the values in the fourth column 38 are 0, 1, 2 respectively, these three values indicate the three columns of the clean table in Fig. 6 (c)). When the main control unit receives a WR I TE instruction to instruct it to write some data to the logical address 67, in this example, its defined logical address is in the logical address area 0 (because the logical address area 0 The addresses are logical addresses 0 to 2 5 5). In Figure 6 (b), the mapping relationship between the logical address and the group shows that the corresponding group is group 2. The corresponding flags in column 37 are not set, so there is no need to refer to the clean table to identify the block corresponding to group 2: according to the rule system 4, 5, 21 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 6 and 7. Therefore, logical address 6 7 is the fourth page of block 5. If the page is in the erased state, the data from the W R I T E instruction is written to the page. If this page is not in the erased state, the data in the W RI TE instruction is written to the fourth page of the second block of the group at the top of bank 25, which is group 7. Then, the memory address mapping table in FIG. 6 (b) is updated to FIG. 6 (d). The method is to move the group number at the upper end of the storage column (that is, the group number 7) to block 3 3 corresponding to the logic In the column of address area 0, the flag indicating that the block 7 is irregular is copied to the same column in the third column 37, and the corresponding data indicating the list in the clean table is copied to the new column 4 38 Column. Any data stored on the other pages of blocks 4, 5, 6, and 7 are copied to the corresponding pages of group 7 respectively (ie, pages of blocks 2 4, 2 5, 2 6 and 5 6 respectively) . If a read instruction for the logical memory address 67 is received next, the main control unit 7 confirms that it corresponds to the logical area 0 again, so check the corresponding column in the memory address mapping table of FIG. 6 (d). At this time, it can find from column 3 3 that the corresponding group is 7, and the flag in column 3 7 indicates that the group is irregular. Column 38 indicates that the group is in column 2 (ie, the last column) of the clean table of FIG. 6 (c). Therefore, the main control unit extracts the blocks of this column from the clean table of FIG. 6 (c) (that is, blocks 24, 25, 26, and 5 6). It reads data from the fourth page (that is, block 25) of the second block of group 7, generates one or more data packets encoded with the data, and sends the packets out of the device through interface 3. . If the write instruction for the logical memory address 6 7 is received again, the main control unit 7 checks the pair 22 312 / Invention Specification (Supplement) / 93-08 in the memory address mapping table of FIG. 6 (d) again / 93115289 200525438 should be in place. At this time, it found that the corresponding group was 7, and the flag in column 37 indicated that the group was irregular. Therefore, the main control unit extracts the corresponding number of columns (ie, 2) from column 38, and obtains the blocks of this column (ie, blocks 2 4, 2 5, 2, 6, 6, 5 from the clean table of FIG. 6 (c)). 6). It checks the fourth page (block 2 5) of the second block of group 7 to see if the data is stored in it (according to the history explained above, of course there is data). Therefore, move the data stored in the other pages of the group to the corresponding page of the group now located at the top of bank 3 5 (ie, group 4), and write the data of the WRITE instruction to the second of this group The fourth page of the block. Then, insert the number 4 in the top column of column 33, copy the (blank) flag corresponding to group 4 to the top column of column 37, and copy the (blank) data corresponding to group 4 to the block Insert the index 7 into the last column of section 3 5 of the table (the other columns have been moved up one column), copy the corresponding flag to the last column of column 3 7 and copy the corresponding data to the block The last column of 38. Please note that this step is almost the same as Figure 4. However, it should be understood that steps 3 and 5 are now more complicated. The block is not only confirmed by the logical address and memory address mapping table (such as Figure 3), but the memory address mapping table (such as Figures 6 (b) and 6 (d)) is used to obtain a corresponding group. Group, and determine the block of the group (according to the rules, or if there is a flag in column 3 7 of the memory address mapping table, the column indicated by column 3 8 of the clean table in Figure 6 (c)) To achieve confirmation. Furthermore, in this example, the reference to the first bank block in steps 8 and 9 should be interpreted as referring to the first bank block group (that is, the top of block 35 in the memory address mapping table). Group). This can explain how the second specific example operates the mapping relationship between the logical address area and the individual area 23 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 block group. A logically independent problem is the specific example of how to map logical addresses in any given logical address area to individual pages in the corresponding block group. One possibility is for the correspondence we call "level". This means that consecutive pages of a block correspond to consecutive logical addresses. The last page of each block (except the last block of the group) corresponds to the consecutive logical address before the corresponding logical address of the first page of the next block of the group. Therefore, for example, the amount of data slightly larger than the number of pages in a single block will be written to the memory in the following way, that is, the beginning of the data is written to a page specified by a logical address, and then written to the block Until the block is exhausted, and then the rest of the data is written to the first page of the next block. However, this is not the only possibility. In a preferred form of the second specific example of the present invention, the main control unit is operable so that the logical correspondence of the addresses of the pages of the logical correspondence block group is "vertical". Specifically (assuming, for example, there are four blocks in a particular group), the first four logical addresses can map to the first page of each block (ie, the first logical address pair The first logical page mapped to the first block of the group; the second logical address mapped to the first page of the second block of the group; etc.), the next four logical addresses can be mapped to each The second page of a block (that is, the fifth logical address maps to the second page of the first block of the group; the sixth logical address maps to the second page of the second block of the group ;and many more). In other words, the main control unit 7 regards four consecutive logical address groups as individual pages respectively corresponding to individual blocks. Calculate measurements along the page level of individual blocks. Pages associated with a particular logical address group all have the same offset value (also 24 312 / Invention Specification (Supplement) / 93-08 / 931〗 5289 200525438 ie, these, etc. Pages form a "block" of the physical address space). Figure 6 (e) shows a specific data volume to be written to one of the groups 2 (ie, blocks 4, 5, 6 and 7). Relative to the logical address corresponding to block 4, the starting logical address of the written data has an offset of, that is, the starting logical address of the written data is the page of the first page of the group. These pages are calculated vertically in FIG. 6 (c) (that is, the pages in the first column are counted down, and then the next column is counted down). Therefore, pages with 17 are represented by "A". In the write operation, the data from the old group is copied to the position in group 2 indicated by the slash. Then, the information is written in the slash area 34 in the packet (i.e., starting from position A). Then, any data in the non-slashed area 36 after the old area 34 is reproduced 34 °. A third specific example of the present invention will now be described. The third specific example is similar to the specific example, but with one (important) difference. In the third specific example, the WRITE instruction changes the mappings defined in the memory address mapping table, and makes the data contained in the WRITE instruction to be written to a position of a new block formed at a logical address. At this time, The operation of copying the old block to the new block is partially suspended for a predetermined time to see if any new instructions have been received for the same area of the memory space. Specifically, it is assumed that a WR I TE instruction is received, instructing the data to a certain logical address. It is assumed that the logical address is located in the logical address area currently corresponding to. It is further assumed that the logical address mapping is in the case of area 3 丨 2 / Invention Specification (Supplement) / 93-08 / 93115289 on page 1 of 7. The next 17 will be shifted from the first offset to the area 32. The data will be written in the block to the area at the first, and the first series will be changed to the related data. Check the WRITE A to write block 0, block 0, 25, 200525438, page 4. It is further assumed (Figure 3) that the erased block at the top of bank 25 is block 3. Figure 7 (a) shows part of the physical memory containing blocks 0 and 3. That is, block 0 has tribute materials not labeled X stored on pages 0 to 3, data labeled Y is stored on page 4, data labeled Z is stored on pages 5 to 7, and the rest of the block It is in the erasing state (displayed as "〇"). According to the first specific example, this W R I T E instruction will immediately make the physical memory of blocks 1 and 3 become as shown in FIG. 7 (b). That is, the new data A is stored on page 4, and the number of pages of data X and Z stored in block 3 corresponds to its previous page number in block 0. Block 0 will be erased (indicating that its index will be at the bottom of section 25 in Figure 3). However, in the third specific example of the present invention, the physical memory is initially rewritten as shown in FIG. 7 (c). That is, data A is written to page 4 of block 3, and data X is copied to pages 0 to 3, but data Z has not yet been copied to pages 5 to 7 of block 3. The system is maintained in this configuration for a period of time by a timer. If no W R I T E signal about the logical address corresponding to page 5 of block 3 is received before the end of this period, the write operation is completed and the data is stored as shown in Figure 7 (b). However, during this period, if a W RI TE command is received, instructing data B to be stored to the logical address now corresponding to page 5 of block 3, the data is stored as shown in Fig. 7 (d). The timer then restarts to define a new time period. If before this period ends, another W R I T E signal corresponding to the logical address corresponding to page 6 of block 3 is not received, the write operation is completed so that the data storage is as shown in Fig. 7 (e). However, if a new WRITE instruction is received during this period, the instruction data C is to be stored to the logic 26 now corresponding to page 6 of block 3 312 / Invention Specification (Supplement) / 93-08 / 93 U 5289 200525438 Address, write this information B to page 6 of block 3, and restart the timer. This process can continue to the last page of block 3, or until the time period elapses without receiving a W R I T E instruction indicating that the data is to be stored in the page specified by the previous W R I T E instruction. Please note that this represents data A, B,. . . It can be written to the memory device faster than the first specific example because the need for copying data is reduced. For example, in the above-mentioned series of steps', no matter how many W R I T E instructions for successive pages are received, the data X need only be copied once at the beginning. The flowchart is shown in FIG. 8, and the difference from FIG. 6 is only that steps 8 to 10 are replaced with steps 8 to 13. In step 8 of FIG. 8, in the old block (that is, block 0), only the previous page number of the page related to the received WRITE instruction is copied to the new block (that is, block 3), and the WRITE instruction The data for is written to a page in a new block corresponding to the logical address. In step 9, it is determined whether the last page of the new block has been written. If so, the device proceeds to step 13. Otherwise, in step 10, the device determines whether a new WRITE instruction for a continuous page under the new block is received within a predetermined time. If so, the specific example writes the data there in step 11 and returns to step 9. If not, in step 12 the specific example copies the remaining pages of the old block (that is, about all pages after the last page of the received W R T E instruction, if any). Step 13 corresponds to step 10 of FIG. 4: the old block (block 0) is erased, and the memory mapping address table is updated. Please note that when the specific example proceeds to step 10, if a READ instruction is received, it is about the target logical address area of the current flow of FIG. 8 27 312 / Invention Specification (Supplement) / 93-08 / 93 15289 200525438, the device should read data from the correct location in physical memory (that is, if the logical address corresponds to the address written in step 8, or if the logical address corresponds to The address written in the previous step 9 is read from the new block; otherwise, it is read from the old block). In some forms of this specific example, as in step 10, if it determines that a received new WRITE instruction indicates that data is to be written to any logical address that is not a consecutive page under the new block, the device will also From step 10 to step 12. In this case, the processing of the new WR I T E instruction may begin after the flow of FIG. 4 is completed. Please note that the timer is typically set to a period of several milliseconds, such as about 3ms. If the device is disconnected from the host within a predetermined period of time after receiving the last WRITE command, it will be eligible. Risk of material loss. However, by setting the predetermined period to the order of milliseconds, this problem does not occur, so all data will be stored safely. Note that the third specific example of the present invention is simplified to the first specific example if the predetermined period is limited to zero. A fourth specific example of the present invention will now be described. As in the third specific example, the fourth specific example uses a timer. In this example, the main control unit 7 includes a pattern recognition unit that receives the logical address data extracted by the main control unit from the W R ITE instruction. In a specific operation phase, if the pattern recognition unit notices that a specific logical address appears more frequently than expected, it writes the logical memory address into the "usually used logical address" space, for example, defined in the main control The RAM address of the cell. More generally, the frequently used logical address space may contain a plurality of such high-frequency identification logical addresses. The pattern recognition unit can be programmed 28 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438, which can delete the logical address from this space when the frequency of the logical address decreases, and / or whenever a logical bit When an address is identified as having a higher frequency of use, it is replaced in space. Therefore, the sustainable storage of space most often occurs at the logical address of the WRITE instruction. The main control unit 7 provides a cache RAM memory for each location in the frequently used address space. When receiving a WRI T E instruction about a bit stored in a logical address space, the main control unit will not write the data contained in the WRI T E instruction into the flash memory device at the beginning. . Instead, the data is written to the corresponding cache memory. Then, the main control unit 7 waits for a time determined by the timer. During this time, if no other WR I TE instruction is received (or, in a specific example of a form, if a packet about another block is received), the main control unit according to the first to third aspects of the invention described above In any of the specific steps, the data in the cache memory is written into the flash memory. On the other hand, if another WRI T E instruction about the same logical address is received during the predetermined period, the main control unit writes the data contained in the WRI T E instruction to the same location in its cache memory ( That is, overwrite the data written in the first write packet). Then restart the timer. Therefore, it can be known that if the device receives a large number of WRI T E instructions about the same logical memory address, and the average time interval is lower than the predetermined time set by the timer, these WR I TE instructions generate The number of (computingly expensive) write operations of 9 will be low. A part of the structure of the main control unit 7 is shown in FIG. 9. The main control unit 7 includes a section 51 for dividing a W RI TE instruction into a logical address and data to be written 29 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 to the logical address. The logical address is transmitted to a pattern recognition unit 5 3, which can use it to continuously update a frequently used address space 5 5. The main control unit has a switch 5 7 which determines whether the logical address of the received WR I TE instruction is in the frequently used address space 55. If not, the data and logical address are immediately written into the unit 57, and the unit 57 writes it into the flash memory 9 according to the method of the first specific example. If so, the data is written into a cache memory 5 9 and the timer unit 6 1 is set to operate. If the timer in the timing unit 61 reaches the end of the predetermined period without being reset, the data and the corresponding logical address are transferred from the cache memory 5 9 to the unit 57 by the switch 57. Please note that although FIG. 9 (a) only shows a single timing unit 61, the timing unit 61 is usually provided with a separate timer for each individual logical address in the frequently used logical address space, and for each Each of these logical addresses has a different cache location. If a R E A D instruction is received, a unit 63 will determine whether the logical address is a bit stored in the frequently used address space, and if so, determine whether the corresponding timer is running. If so, it reads data from the corresponding cache memory 5 9; otherwise, it uses a unit 6 7 to read data from the flash memory 9 according to the correspondence relationship defined by the memory address mapping table (ie, according to Method of the first specific example). In either case, it encodes the data into a packet and sends it out of the device through interface 3. The flow chart of this specific example is the flow chart of FIG. 3, but the steps of FIG. 9 (b) are inserted between steps 2 and 3 of FIG. 3 (performed by units 5 1 and 5 7), and of FIG. 9 (c). The steps are inserted between steps 2 and 5 of FIG. 3 (performed by unit 63). In steps 7 and 9, the information written to the page is the last received 30 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 W R T E instruction about the logical address. Whenever the unit 5 3 removes a logical address from the frequently used logical address space (ie, the update unit 5 5), the data in the corresponding position of the cache memory 59 is according to steps 5 to 10 of FIG. 3 And write to memory 9. In any of the third and / or fourth specific examples of the present invention, the timer may be configured so that the predetermined period is only a few milliseconds, for example, about 3ms. If the device is disconnected from the host within a predetermined period of time after receiving the last W R T E command, there is a risk of data loss. However, by setting the predetermined period to the order of milliseconds, this problem does not occur, so all data will be stored safely. Note that the third and fourth specific examples of the present invention are simplified to the first specific example if the predetermined period is limited to zero. Please note that none of the above specific examples require a block positioning table (although other specific examples may use such a table). Although only a few specific examples of the present invention are described in detail here, those skilled in the art can make many possible changes within the scope of the present invention. For example, the features of the second, third, and fourth specific examples can be easily combined in any combination, and even all of the above features (including the vertical filling of the page of the block group) are even better combined. Therefore, the specific example of the present invention can form a logical address region corresponding to an individual group composed of a plurality of blocks, where a logical address in a specific logical address region corresponds to a column in a block group. One of the first timer signals is used to suspend the replication of data from an old group to a new group, and one of the second (optionally different) timer signals is used to suspend the data contained in a WRITE instruction. The data is written into the flash memory device 9. Furthermore, in the above specific example, there is only a single NAND flash memory 31 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 device. However, the present invention is not limited to this aspect, but may have more than one N A N D flash memory device, which operates according to the principles of the present invention described above. For example, each NAND memory device may be associated with a specific individual portion of the logical address space. For each NAND memory device, between a block of the memory device and an individual region of a corresponding portion of the logical address space Has a variable mapping relationship. As described above, the present invention can be implemented via a USB connection, but it is not limited to this aspect. Preferably, the USB standard used by the USB controller is U S B 2. Version 0, but the present invention can also be implemented in other USB standard versions, such as any version formulated in the future. The total memory capacity of the device is not limited within the scope of the present invention, but is preferably at least 1 megabyte, more typically at least 10 megabyte, at least 100 megabyte, or even at least 1 megabyte. Bytes. [Brief description of the drawings] FIG. 1 shows a first structure diagram of a conventional portable data storage device; FIG. 2 shows a physical memory space of a NAND flash memory device of the conventional device of FIG. 1; FIG. 3 shows the present invention Memory address mapping table of the first specific example; FIG. 4 is a flowchart of steps performed by the first specific example of the present invention; FIG. 5 shows the memory address mapping table of FIG. 3 after a specific data writing operation; Figure 6 contains Figures 6 (a) to 6 (e), which shows a second specific example of the present invention; Figure 7 contains Figures 7 (a) to 7 (e), which shows a third specific example of the present invention in individual State of physical memory of time; 32 312 / Invention Specification (Supplement) / 93-08 / 93115289 200525438 Figure 8 is a flowchart of the specific example of Figure 7; and Figure 9 contains Figures 9 (a) to 9 (c ), Which illustrates a fourth specific example of the present invention. (Description of component symbols) 1 Portable storage device 2 USB controller 3 USB interface 4 USB interface 5 Host computer 6 Page 7 Main control unit 8 Bus 9 Flash memory 10 Block 11 Control data storage area 12 Line 2 1 Left column 23 Right column 2 5 Storage column block 31 Left bad 3 2 Slash area 33 Middle column 3 4 Slash area 35 Section 3 6 Slash-free area 312 / Invention specification (Supplement) / 93-08 / 93115289 33
200525438 3 7 欄 38 欄 5 1 區段 53 模式辨識單元 5 5 經常使用位址空間 5 7 開關（單元） 5 9 快取記憶體 6 1 計時單元200525438 3 7 column 38 column 5 1 section 53 pattern recognition unit 5 5 address space frequently used 5 7 switch (unit) 5 9 cache memory 6 1 timing unit
63 單元 6 7 單元63 units 6 7 units
312/發明說明書(補件)/93-08/93115289 34312 / Invention Specification (Supplement) / 93-08 / 93115289 34