TWI454907B - Flash memory device and operation method thereof - Google Patents

Description

Memory device and its operation method

The present invention relates to flash memory, and more particularly to an address mapping table for flash memory.

A typical flash memory device includes a flash memory and a controller for storing data for a host. The controller acts as a communication interface between the host and the flash memory. When the host wants to store data to the flash memory device, the controller receives the write command and the write data sent by the host, and then stores the write data to the flash memory according to the write command. When the host wants to read data from the flash memory device, the controller receives the read command issued by the host, and then reads the read data from the flash memory according to the read command and transmits it to the host.

When the host accesses the data of the flash memory device, the host refers to the data accessed by the host with a logical address. However, the flash memory system accesses data at its own physical address. Therefore, when the controller accesses the data of the flash memory according to the logical address issued by the host, the controller must convert the logical address into a physical address. Therefore, the controller must store the correspondence between the logical address and the physical address in an address mapping table as a basis for conversion between the logical address and the physical address.

Figure 1 shows an address correspondence table for recording the correspondence between logical addresses and physical addresses. According to the address correspondence table, the logical address X ₁ corresponds to Y ₁ , the logical address X ₂ corresponds to Y ₂ , and the logical address X _Z corresponds to Yz. Since the address correspondence table records the correspondence between all physical addresses Y ₁ ~Y _{Z of} the flash memory and the logical address, the controller can perform conversion between the logical address and the physical address according to the address correspondence table.

In general, the controller stores an address correspondence table in a random access memory (DRAM) included therein. Since the random access memory cannot store data in the unpowered state, the address correspondence table stored in the random access memory must be stored in the flash memory before the power of the flash memory device is removed. When the flash memory device is powered on again, the controller loads the address correspondence table stored in the flash memory into the random access memory for the controller to perform conversion between the logical address and the physical address.

However, when the power of the flash memory device is suddenly interrupted, the controller does not have sufficient time to store the address correspondence table stored in the random access memory in the flash memory due to the large amount of data in the address correspondence table. When the flash memory device is powered back on, the controller cannot read the address correspondence table from the flash memory to load the random access memory. Therefore, when the power of the flash memory device is suddenly interrupted, the controller cannot perform conversion between the logical address and the physical address due to the lack of the address correspondence table.

In the prior art, one method for preventing a sudden power failure condition is to back up each logical address in a corresponding physical storage unit of the flash memory, for example, in a free space of a physical page, when fast When the flash memory device is powered on again, the free space of the physical storage unit of all the flash memory is scanned to reconstruct the entire address correspondence table. This method takes a long time to reconstruct the address correspondence table, which is a normal system startup. Time is not allowed. Another method is to set a plurality of large-capacity capacitors in the flash memory device to keep the power supply for the flash memory device when the power is suddenly turned off, so that the controller has sufficient time to store the address correspondence table stored in the random access memory. It is stored in the flash memory, but this method will lead to an increase in system power consumption and will result in an increase in the physical volume of the flash memory device.

Therefore, the present invention provides a method for operating a flash memory device, which can pre-store the address correspondence table stored in the random access memory of the controller into the flash memory, thereby preventing the sudden power-off condition, and The above drawbacks of the prior art can be overcome.

In view of the above, it is an object of the present invention to provide a method of operating a memory device to solve the problems of the prior art. In one embodiment, the memory device includes a controller, a memory, and a flash memory. First, the address mapping table stored in the memory is divided into a plurality of mapping table units. Then, the correspondence between the logical address of the flash memory and the physical address recorded in the corresponding partial table is updated. Next, it is checked whether the access action of the controller to the flash memory conforms to a first specific condition. Whenever the access action of the controller to the flash memory meets the first specific condition, a current corresponding sub-table is sequentially selected from the corresponding sub-tables, and the current record is recorded in the flash memory. The corresponding sub-table and the corresponding time stamp are a corresponding sub-table data.

The invention further provides a memory device. In one embodiment, the memory device includes a flash memory, a memory, and a controller. The flash memory is for data storage. The memory stores a bitmap mapping table. The controller divides the mapping table into a plurality of mapping table units, and updates the correspondence between the logical addresses of the flash memory and the physical addresses recorded in the corresponding sub-tables. a relationship, checking whether the controller accesses the flash memory conforms to a first specific condition, and whenever the controller accesses the flash memory to meet the first specific condition, A corresponding corresponding sub-table is sequentially selected in the corresponding sub-table, and the current corresponding sub-table and the corresponding time stamp are recorded in the flash memory as a corresponding sub-table data.

The above and other objects, features, and advantages of the present invention will become more apparent and understood.

2 is a schematic diagram of an address mapping table 200 in accordance with the present invention. The controller of the flash memory device includes a memory. This memory is usually random access memory (DRAM). The address correspondence table 200 is divided into a plurality of mapping table units 201 to 20K, which are respectively stored in the memory of the controller. Each corresponding sub-table 201~20K stores a corresponding relationship between a certain number of logical addresses and physical addresses. In an embodiment, the corresponding sub-tables 201-20K each store a correspondence of a specific logical address range. For example, the corresponding sub-table 201 stores the correspondence relationship of the logical address ranges X _A1 to X _An , and the corresponding sub-table 202 stores the correspondence relationship of the logical address ranges X _B1 to X _Bn . In another embodiment, the corresponding sub-tables 201-20K each store a correspondence relationship of a specific entity address range. For example, the corresponding part table 201 stores the correspondence relationship of the entity address ranges Y _A1 ~Y _An , and the corresponding part table 202 stores the correspondence relationship of the entity address ranges Y _B1 ~Y _Bn . Since the corresponding sub-tables 201~20K are still combined into the complete address correspondence table 200, the controller can still perform conversion between the logical address and the physical address according to the address correspondence table 200, and is not subject to the corresponding sub-table 201~20K. The effect of separate storage.

Figure 3 is a block diagram of a flash memory device 300 in accordance with the present invention. In one embodiment, the flash memory device 300 includes a controller 302 and a flash memory 304. Controller 302 includes a memory 310. In one embodiment, the memory 310 is a random access memory (DRAM). In another embodiment, the memory 310 can also be disposed external to the controller 302 as a separate component of the controller 302. The memory 310 stores K corresponding sub-tables 311~31K, and the corresponding sub-tables 311~31K respectively store a corresponding relationship between a certain number of logical addresses and physical addresses. The corresponding sub-tables 311 to 31K are combined into a complete address correspondence table 330. The memory 310 further includes an operation record buffer 320 for storing a change in the correspondence between the logical address and the physical address in the entire address correspondence table 330 by the access operation of the controller 302 to the flash memory 304. That is, the information of the operation record (Operation Record) of the address correspondence table 330 is stored. In one embodiment, the storage space of each of the corresponding sub-tables 311 to 31K and the operation record buffer 320 occupies a storage space of one of the logic pages of the memory 310.

When the controller 302 performs data access to the flash memory 304, the controller 302 stores the operation record of the entire address correspondence table 330 in the operation record buffer 320 in a specific time interval due to the flash memory. The body 304 must be erased and then written. When the controller 302 performs data access to the flash memory 304, the corresponding relationship between the logical address of the accessed data and the physical address is changed, so the controller 302 will The correspondence between the changed logical address and the physical address in the entire address correspondence table 330 in a specific time interval, that is, the operation record is stored in the operation record buffer 320, and the related corresponding sub-tables 311 to 31K are updated. The correspondence between the logical address and the physical address. In one embodiment, the memory 310 is a random access memory (DRAM), and the stored content can be updated at any time. Therefore, the logical page corresponding to the sub-tables 311 to 31K can be K logical page addresses. Continuous logical page. In addition, the controller 302 continuously monitors whether its access operation to the flash memory 304 conforms to a particular condition. In an embodiment, the specific condition may be that the controller 302 accumulates a fixed amount of data for the flash memory 304, or each fixed period of time. Whenever the specific condition is met, the controller 302 writes one of the corresponding sub-tables 311~31K stored in the memory 310 and the current time stamp into the flash memory 304 to generate corresponding sub-table data. In addition, each time the specific condition is met, the controller 302 writes the operation record stored in the operation record buffer 320 and the current time stamp to the flash memory 304 to generate corresponding operation record data. The aforementioned "specific time interval" refers to the time interval between two adjacent conditions that meet the specific condition. In an embodiment, in the flash memory 304, each corresponding sub-table data and each operation record data respectively occupy a storage space of one of the flash memory pages, and corresponding to the same time. The corresponding sub-table data and operation record data of the stamp are stored in a data page whose addresses differ by a fixed value. In another embodiment, the specific condition that the controller 302 writes the operation record data into the flash memory 304 may be different from the specific condition that the corresponding part table data is written into the flash memory 304, so that the corresponding table 311~ The 31K and the operation log data are stored in the flash memory 304 at different frequencies.

For example, at time T ₁ , the controller 302 accumulates the amount of access data to the flash memory 304 to meet certain conditions, so the controller 302 first stores the data of the corresponding sub-table 311 and the time stamp T ₁ to the flash memory. The body 304 generates the corresponding part table data 351, and stores the operation record and the time stamp T ₁ stored in the operation record buffer 320 to the flash memory 304 to generate the corresponding operation record data 361. At time T ₂ , the controller 302 accumulates the access data amount to the flash memory 304 again to meet the specific condition, so the controller 302 first stores the data of the corresponding sub-table 312 and the time stamp T ₂ to the flash memory 304 to generate Corresponding to the sub-table data 352, the operation record and the time stamp T ₂ stored in the operation record buffer 320 are stored in the flash memory 304, and the corresponding operation record data 362 is generated. Please note that in the embodiment, the operation record data 362 is operated. It is an operation record of the entire address correspondence table 330 between the instant point T ₁ and the time point T ₂ in a specific time interval. Then, at time point T ₃ , the controller 302 accumulates the access data amount to the flash memory 304 again to meet the specific condition, so the controller 302 first stores the data of the corresponding sub-table 313 and the time stamp T ₃ to the flash memory 304. The corresponding part table data 353 is generated, and the operation record and the time stamp T ₃ stored in the operation record buffer 320 are stored in the flash memory 304, and the corresponding operation record data 363 is generated. The process continues until the time point T _K , the controller 302 first stores the data of the corresponding sub-table 31K and the time stamp T _K to the flash memory 304 to generate the corresponding sub-list data 35K, and then stores the operation record buffer 320. The operation record and time stamp T _{K are} stored in the flash memory 304, and the corresponding operation log data 36K is generated. At this time, all the corresponding sub-tables 311~31K are written into the flash memory 304 as the corresponding sub-table data 351~35K. Then, at time point T _K+1 , the controller 302 accumulates the access data amount to the flash memory 304 again to meet the specific condition, so the controller 302 again stores the data of the corresponding sub-table 311 and the time stamp T _K+1 to the fast. The flash memory 304 generates the corresponding part table data 35 (K+1), and then stores the operation record and the time stamp T _K+1 stored in the operation record buffer 320 to the flash memory 304 to generate the corresponding operation record data 35. (K+1). Since the corresponding sub-list data 35 (K+1) and the corresponding sub-table data 351 are the data corresponding to the sub-table 311, the time stamp T _{K+1 of} the corresponding sub-table data 35 (K+1) is more corresponding to the sub-table data 351 The time stamp T ₁ is late, so the corresponding data of the sub-table data 35 (K+1) is newer, and the position of the corresponding sub-table data 351 is replaced. The replaced corresponding sub-list data 351 becomes invalid data. In an embodiment, the corresponding sub-table data 351~35K are sequentially stored in the flash memory 304 according to the logical page ID of the corresponding sub-tables 311-31K in the memory 310, so When the corresponding part table data 35(K+1) corresponding to the part table 311 is generated again, the logical page address of the corresponding part table data 35 (K+1) is the same as the logical page address of the corresponding part table material 351, and The time stamp T _K+1 is later than the time stamp T ₁ of the corresponding part table data 351, so the corresponding part table data 351 can be marked as invalid. At this time, the corresponding sub-table data 352~35(K+1) stored in the flash memory 304 constitutes a backup of a complete address correspondence table. Further, since the part table data corresponding to 351 have the same time stamp data T operation recording operation of the record ₃₆₁₁ has been updated in the corresponding part table data 352 ~ 35 (K + 1) , and therefore the operation record information 361 also becomes invalid Information can also be marked as invalid.

4 is a flow diagram of a method 400 of storing a corresponding sub-table to flash memory in accordance with the present invention. First, the controller 302 divides the address correspondence table 330 stored in the memory 310 into a plurality of corresponding sub-tables 311 to 31K (step 402). Next, the controller 302 updates the correspondence between the logical address and the physical address recorded in the corresponding sub-tables 311 to 31K as time passes (step 404). Then, the controller 302 records in the operation record buffer 320 of the memory 310 that the access operation of the controller 302 to the flash memory 304 is caused by the correspondence between the logical address and the physical address in the entire address correspondence table 330. The data is changed, that is, the information of the operation record (Operation Record) of the address correspondence table 330 is stored (step 406). Next, the controller 302 checks if its data access to the flash memory 304 conforms to a particular condition (step 408). Since each time the controller 302 writes a block of the flash memory 304 to the data, the controller 302 obtains a blank block from a free block area of the flash memory 304 (free The block 302 is used for storing new data. Therefore, the controller 302 newly obtains a blank block from the flash memory 304 to indirectly indicate that the accumulated access data amount of the controller 302 to the flash memory 304 reaches a data amount of one block. Therefore, in an embodiment, the specific condition of step 408 is to check if the controller 302 newly acquires a blank block from the flash memory 304. In other embodiments, the specific condition may be that the length of the fixed time determines the frequency of the backup address correspondence table 330 to the flash memory 304 every time a fixed period of time is passed. In an industrial implementation, the frequency may be comprehensively considered. Depending on the system boot up time and the write bandwidth consumption: the higher the frequency, the greater the write bandwidth consumption of the flash memory 304, but at the same time, due to the shortened time interval. The amount of data recorded in the operation of the address correspondence table 330 becomes small, so that the speed of rebuilding the address correspondence table after the power is turned off is accelerated, so that the system startup time becomes shorter when the power is turned on again. This frequency can therefore be determined by the system designer based on system performance requirements.

Whenever a certain condition is achieved, the controller 302 selects a current corresponding sub-table from the corresponding sub-tables 311 to 31K (step 410), and records the current corresponding sub-table data and the corresponding time stamp in the flash memory 304. (Step 412). In an embodiment, in order to avoid recording the data of the current corresponding part table into the flash memory 304, the controller 302 performs the address corresponding to the record in the current corresponding sub-table by executing the access command of the host. To perform the change, the controller 302 configures at least two logical page storage spaces in the memory 310 for each corresponding sub-table of the corresponding sub-tables 311 to 31K to implement Ping-Pong buffering, that is, When the address corresponding to one logical page is written to the flash memory 304, the other logical page simultaneously receives the new address corresponding data. In addition, the controller 302 records the operation record data stored in the operation record buffer 320 and the corresponding time stamp in the flash memory 304 whenever the specific condition is achieved (step 414). In an embodiment, When the specific condition is achieved, the operation record data is written into the flash memory 304, and an action of storing the new operation record in the operation record buffer 320 may occur, so that the operation record buffer 320 is not yet written. The operation record data in the flash memory 304 is overwritten by the new operation record data. Another embodiment of the present invention configures at least two logic page storage spaces for the operation record buffer 320 in the memory 310. To implement Ping-Pong buffering, that is, when the operation record data of one logical page is written into the flash memory 304, another logical page simultaneously receives the new operation record data. Because each time a certain condition is achieved, the controller 302 only stores the data of one of the K corresponding sub-tables to the flash memory 304, so that the bandwidth of the access flash memory 304 is not excessively affected. It does not cause excessive delays in the execution of host access commands.

FIG. 5 is a flow chart of a method 500 for reconstructing a new address correspondence table according to the corresponding partial data stored in the flash memory according to the present invention. First, assume that the flash memory device 300 is powered off and then powered back on (step 502). Next, the controller 302 reads a plurality of corresponding part table data corresponding to the plurality of relatively latest time stamps from the flash memory 304 (step 504). In an embodiment, the specific step of performing step 504 is: the controller 302 compares time stamps of different materials that record the same corresponding sub-tables, and reads different corresponding sub-list data having relatively late time stamps. For example, in the flash memory 304 of FIG. 3, the corresponding sub-table data 351 and 35 (K+1) store the data corresponding to the sub-table 1, and the corresponding sub-list data 35 (K+1) has The relatively late time stamp T _K+1 , so the corresponding part table data 35 (K+1) is read by the controller 302. In addition, in the flash memory 304, the corresponding sub-table data 352 and 35 (K+2) store the data corresponding to the sub-table 2, and the corresponding sub-list data 35 (K+2) has a relatively late time stamp. T _K+2 , so the corresponding part table data 35 (K+2) is read by the controller 302. Therefore, the controller 302 reads out the corresponding sub-table data 353-35 (K+2) from the flash memory 304 in total. In another embodiment, since the corresponding part table data 351~35(K+2) is in the flash memory 304, the logical page ID in the memory 310 according to the corresponding part table 311-31K. The specific steps of step 504 are: firstly, the corresponding sub-table data with the absolute latest time stamp is located, and the corresponding sub-table data with the absolute latest time stamp and several previously stored data are stored. The corresponding sub-table data is read separately, wherein the total number of corresponding sub-table data read out is equal to the number of corresponding sub-tables. For example, in the flash memory 304 of FIG. 3, the corresponding sub-table data 35 (K+2) has the absolute latest timestamp T _{K+2 of} all corresponding sub-table data 351~35 (K+2). Therefore, the controller 302 reads the corresponding part table data 35 (K+2), and since the corresponding part table stored in the memory 310 has a total of K, it is also required to be before the corresponding part table data 35 (K+2). The stored (K-1) corresponding sub-table data are also read separately, that is, a total of a total of K corresponding sub-table data including the corresponding sub-list data 35 (K+2) are read out. Since the order in which the corresponding part table data is stored in the flash memory 304 is sequentially stored according to the logical page ID in the memory 310 of the corresponding part table 311-31K, the corresponding part table data 35 ( K+2) and a total of K corresponding sub-table data stored between them, namely 353~35 (K+2), which are the latest corresponding sub-table data.

Next, the controller 302 selects an earliest timestamp as the target time from the plurality of timestamps corresponding to the corresponding partial table data 353~35(K+2) (step 506), for example, corresponding sub-table data 353~35 ( The time stamp of K+2) ranges from T ₃ to T _K+2 , so the controller 302 takes the earliest time stamp T ₃ as the target time. Next, the controller 302 reads the operation log data 363 corresponding to the target time T ₃ from the flash memory 304 as the target operation log data (step 508). Next, the controller 302 updates the corresponding sub-table data 353-35 (K+2) according to the target operation log data 363 (step 510). Specifically, in step 510, the controller 302 compares the timestamps of the corresponding partial table data 353~35 (K+2) with the time stamp of the target operation record data 363, and the controller 302 only depends on the target. The operation log data 363 updates the corresponding sub-tab data whose corresponding time stamp is smaller than the time stamp of the target operation log material 363. For example, the corresponding part table data 353 ~ 35 (K + 2) of the stamp are equal to or greater than the target information recording operation of the time stamp 363 T _3, and therefore the controller 302 does not operate according to the target information recording table 363 to update any corresponding points data. Next, the controller 302 selects a timestamp T ₄ below the target time T ₃ as the target time from the time stamp corresponding to the corresponding part table data 353~35 (K+2) (step 514), self-flashing The memory 304 reads the operation record data 364 corresponding to the target time T ₄ as the target operation record data (step 508), and updates the corresponding part table data 353~35 (K+2) according to the target operation record data 364 (step 510), specifically, when step 510 is performed this time, since only the timestamp T _{3 of the} corresponding part table data 353 is smaller than the time stamp T _{4 of the} target operation record data 364 in the corresponding part table data 353~35 (K+2) Therefore, the controller 302 only updates the corresponding part table data 353 according to the target operation record data 364. The controller 304 will continue to perform the loops of steps 508-514 until the target time is greater than or equal to the timestamp corresponding to all of the corresponding partial data 353-35 (K+2) (step 512). Next, the controller 302 merges the plurality of update corresponding sub-table data obtained by performing the loop to obtain a latest address correspondence table (step 516). Finally, the controller 302 stores the latest address correspondence table back to the memory 310 for accessing the reference of the flash memory 302.

Figure 6 is a schematic illustration of an embodiment of data for flash memory storage in accordance with the present invention. The flash memory 300 of FIG. 3 stores only two types of data, including multiple corresponding sub-table data 351~35 (K+2) and multiple operation record data 361~36 (K+2). In Fig. 6, the flash memory 600 stores three types of data, including multiple corresponding sub-table data 651~65 (K+2), multiple operation record data 661~66 (K+2), and newly acquired data. The physical address of the blank block is 671~67 (K+2). According to an embodiment of step 408 of FIG. 4, each time the controller 302 newly obtains a blank block from the blank area of the flash memory, the controller 302 stores a corresponding part table data and an operation record data to the fast. Flash memory 600. In addition, the controller 302 further stores the newly obtained physical address of the blank block and the target time stamp to the flash memory 600. Thus, when the flash memory device is powered off and then powered back on, the controller 304 reconstructs the latest address correspondence table according to the flowchart of FIG. 5, when performing the loop to steps 508-514, and the target time setting of step 514 is performed. When the absolute time T _K+2 is absolute, the controller 302 reads the operation record data corresponding to the target time T _K+2 from the flash memory 600. However, since the previous flash memory device power failure may occur at any time, if the power failure occurs in the corresponding sub-segment data 65 (K+2) and the newly acquired blank block physical address 67 (K+2) has been stored to When the flash memory 600 is flashed and the operation log data 66 (K+2) has not been stored, the controller 302 cannot read the operation log data 66 (K+2) whose target time is T _K+2 . Generally speaking, when the controller 302 stores the data to the newly acquired blank block, the correspondence between the logical address corresponding to the stored data and the physical address is stored to be stored outside the stored data of the blank block. In the free space, the controller 302 can read the physical address of the blank block corresponding to the absolute latest timestamp T _K+2 from the flash memory 600, and read the blank block according to the physical address, Since the time stamp T _K+1 to T _K+2 , the access operation of the controller 302 to the flash memory 600 is limited to the blank block corresponding to the latest time stamp T _K+2 , so The correspondence between the logical address stored in the free space of the blank block and the physical address can rebuild the operation record data 66 (K+2). In an embodiment, the corresponding partial table data 651-65 (K+2) and the newly acquired blank block addresses 671-67 (K+2) corresponding to the same time stamp are respectively stored in the flash memory 600. In the page, the data page addresses of the flash memory 600 are sequentially stored. The operation record data 661~66 (K+2) are respectively stored in a data page of the flash memory 600, and are also sequentially stored according to the data page address of the flash memory 600. In addition, in an embodiment, the corresponding sub-table data 651~65 (K+2), the newly obtained blank block physical address 671~67 (K+2), and the operation record data 661~66 (K+ 2) A plurality of blocks stored in the flash memory 600 having a specific logical address range. Since the controller 302 frequently records the above data to the flash memory 600 at a high frequency, it is easy to cause excessive wear of the block storing the above data, so that the block corresponding to the logical address range can be worn average (wear The -leveling function is automatically replaced with blocks that are less worn or have lower erase counts to maintain data correctness.

Fig. 7 is a view showing the correspondence between the corresponding part table data and the operation record data stored in the flash memory 304 in accordance with Fig. 3 of the present invention. FIG. 7 shows a data storage situation of a physical address range of the flash memory 304, and the corresponding sub-table data or operation record data is stored in the physical address range of the flash memory 304. Referring to the description of an embodiment at the end of FIG. 3, the controller 302 repeatedly stores the corresponding corresponding sub-list data and the operation record data in the flash memory 304, corresponding to the old time stamp corresponding sub-table data and operation record data. It is marked as invalid data, and only the corresponding sub-table data corresponding to the new time stamp and the operation record data are valid data can be reconstructed by the method 500 of FIG. 5 to reconstruct a new address correspondence table. In the physical address range shown in Figure 7, for example, the valid data stored is valid corresponding sub-list data, and the block that stores the valid corresponding sub-table data is a delimiter, which is stored in the block. Specific styles of information to define the end of valid correspondence table data. In an embodiment, the partition block is a vacant block, and does not store any data. Therefore, when the flash memory device 300 is powered on again, the last stored page of the end of the effective corresponding part table data can be found according to the partition block. In an embodiment, the method is as shown in step 504 of the foregoing fifth figure. The corresponding table data having the absolute latest time stamp is extracted, and the K storage pages corresponding to the number K of the corresponding sub-tables into which the address correspondence table 330 is divided in the memory 310 are subtracted from the last storage page. To find the first storage page of the beginning of the effective corresponding part table data, to start performing the "reading a plurality of corresponding part table data corresponding to the plurality of relatively late time stamps" of step 504 of FIG. 5 for reconstructing the latest address corresponding table. In an embodiment, the operation record data corresponding to the timestamp corresponding to the corresponding part table data is stored in a physical address that is different from the entity address range shown in FIG. 7 by a fixed value, and the storage manner and the corresponding part table are stored. The data is stored in a similar manner and will not be described again.

The method for operating the flash memory device of the present invention backs up the address correspondence table stored in the random access memory of the controller to the flash memory in advance, and can reconstruct the power failure after any sudden power failure occurs. The latest address correspondence table. In addition, since the present invention divides the address correspondence table into a plurality of corresponding sub-tables, the data of the present invention for each backup to the flash memory is limited to a current corresponding sub-table and an operation record data, which is greatly reduced. The write bandwidth consume of the flash memory 304 does not cause excessive delay in the execution of the host access command; since the amount of data required to reconstruct the latest address correspondence table is reduced, The invention also shortens the system boot up time. In addition, since the data of the backup flash memory only has corresponding sub-table data corresponding to the new time stamp and the operation record data is valid data, the corresponding time-sampling sub-table data and the operation record data of the old time stamp are marked as invalid data. The block in which the invalid data is located can be erased to release the free block, so the method of the present invention only needs to occupy the limited storage space of the flash memory.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

(Fig. 2)

200. . . Address correspondence table

201, 202, ..., 20K. . . Corresponding table

(Fig. 3)

300‧‧‧ memory device

302‧‧‧ Controller

304‧‧‧Flash memory

310‧‧‧ memory

311-31K‧‧‧corresponding table

320‧‧‧Operation Record Buffer

330‧‧‧ Address correspondence table

351~35(K+2)‧‧‧ corresponding table data

361~36(K+2)‧‧‧ operation record data

(Figure 6)

600‧‧‧flash memory

651~65(K+2)‧‧‧ corresponding table data

661~66(K+2)‧‧‧ operation record data

671~67(K+2)‧‧‧ Newly obtained the address of the blank block

Figure 1 shows an address correspondence table for recording the correspondence between logical addresses and physical addresses;

Figure 2 is a schematic diagram of an address correspondence table according to the present invention;

Figure 3 is a block diagram of a flash memory device in accordance with the present invention;

4 is a flow chart of a method for storing a corresponding sub-table to a flash memory according to the present invention;

FIG. 5 is a flow chart of a method for reconstructing a new address correspondence table according to the corresponding partial table data stored in the flash memory according to the present invention;

Figure 6 is a schematic diagram of an embodiment of data for flash memory storage in accordance with the present invention;

Figure 7 is a schematic diagram showing the correspondence between the corresponding sub-table data and the operation record data stored in the flash memory according to the present invention.

300. . . Memory device

302. . . Controller

304. . . Flash memory

310. . . Memory

311-31K. . . Corresponding table

320. . . Operation record buffer

330. . . Address correspondence table

351~35(K+2). . . Corresponding table data

361~36(K+2). . . Operational record data

Claims (22)

A method for operating a memory device, wherein the memory device comprises a controller, a memory and a flash memory, the method comprising the steps of: mapping an address corresponding to the address stored in the memory (mapping) The table is divided into a plurality of mapping table units; updating the correspondence between the logical address of the flash memory and the physical address recorded in the corresponding partial table; checking the controller for the flash memory Whether the access operation of the body meets a first specific condition; and each time the access action of the controller to the flash memory conforms to the first specific condition, a current correspondence is sequentially selected from the corresponding sub-tables The table is divided, and the current corresponding sub-table and the corresponding time stamp are recorded in the flash memory as a corresponding sub-table data. The method for operating a memory device according to claim 1, wherein the method further comprises the step of: recording an operation record of the controller corresponding to the address correspondence table in an operation recording buffer of the memory; Whenever the controller accesses the flash memory to meet a second specific condition, the data stored in the operation record buffer and the corresponding time stamp are recorded as an operation record in the flash memory. Operation record. The method for operating a memory device according to claim 2, wherein the first specific condition and the second specific condition are that the controller obtains a blank block from a spare area of the flash memory. (spare block) for storing information. The method for operating a memory device according to claim 3, wherein the method further comprises the steps of: recording the current corresponding sub-table and the corresponding time stamp, and recording the controller in the flash memory; The newly obtained physical address of the blank block and the corresponding timestamp. The method of operating a memory device according to claim 2, wherein the first specific condition and the second specific condition are separated by a fixed period of time. The method for operating a memory device according to claim 2, wherein in the flash memory, the corresponding part table data and the operation record data respectively occupy a page and the corresponding time stamp is the same The corresponding sub-table data and the operation record data are stored in two pages with a fixed value of the address. The method for operating a memory device according to claim 2, wherein the method further comprises the following steps: when the memory device is powered off after being powered off, reading from the flash memory corresponds to a plurality of relative a plurality of latest corresponding sub-table data of the late time stamp; reading, from the flash memory, a plurality of latest operation record data corresponding to the plurality of relatively latest time stamps of the latest corresponding sub-table data; respectively The operation record data sequentially updates the latest corresponding sub-table data to obtain a plurality of update corresponding sub-table data; and merges the update corresponding sub-table data to obtain a latest address correspondence table. The operating device of the memory device as described in claim 7 The method, wherein the updating step of the latest corresponding sub-table data further comprises the steps of: comparing a time stamp of a target operation record data in the latest operation record data with a time stamp of the latest corresponding sub-table data; operating according to the target Recording data updates the latest corresponding corresponding table data in the latest corresponding part table data corresponding to the time stamp of the target operation record data; and selecting a timestamp corresponding to the timestamp of the target operation record data The latest operation record data is the next target operation record data; wherein, in the time series, the next time stamp is after the time stamp of the target operation record data. The method for operating a memory device according to claim 7, wherein the method further comprises the following steps: when the memory device is powered off after being powered off, and the time corresponding to the latest corresponding sub-table data cannot be read. When the latest operation record data corresponding to the absolute latest timestamp is stamped, the physical address of a blank block corresponding to the absolute latest timestamp is read from the flash memory; and the physical address is read according to the physical address The blank block; and reconstructing the latest operation record data corresponding to the absolute latest timestamp according to the correspondence between the logical address stored in the blank block and the physical address. The method for operating a memory device according to claim 9, wherein the physical address of the blank block corresponding to the absolute latest time stamp is simultaneously recorded with the corresponding partial data corresponding to the absolute latest time stamp. To the flash memory. The method for operating a memory device according to claim 1, further comprising the steps of: comparing time stamps of different corresponding sub-table data corresponding to the same corresponding sub-table, and corresponding sub-table data having relatively early time stamps. Marked as invalid. A memory device includes: a flash memory for storing data; a memory storing a mapping table; and a controller dividing the address mapping table into a plurality of a corresponding mapping table unit, updating the correspondence between the logical address of the flash memory and the physical address recorded in the corresponding sub-table, and checking the access operation of the controller to the flash memory Whether a first specific condition is met, and each time the access action of the controller to the flash memory meets the first specific condition, a current corresponding sub-table is sequentially selected from the corresponding sub-tables, and The current corresponding sub-table and the corresponding time stamp are recorded in the flash memory as a corresponding sub-table data. The memory device of claim 12, wherein the controller records an operation record of the controller corresponding to the address correspondence table in an operation recording buffer of the memory, and whenever the controller When the access operation of the flash memory conforms to a second specific condition, the controller records the data stored in the operation record buffer and the corresponding time stamp in the flash memory as an operation record data (operation record) ). The memory device of claim 13, wherein the first specific condition and the second specific condition are that the controller is from the flash memory The spare area of the body obtains a spare block for storing data. The memory device of claim 14, wherein the controller records the current corresponding sub-table and the corresponding time stamp, and records the blank block newly obtained by the controller in the flash memory. The physical address and the corresponding timestamp. The memory device of claim 13, wherein the first specific condition and the second specific condition are separated by a fixed period of time. The memory device of claim 13, wherein in the flash memory, the corresponding sub-table data and the operation record data respectively occupy a page, and the correspondence corresponding to the time stamp is the same The sub-list data and the operation record data are stored in two pages with a fixed value of the address. The memory device of claim 13, wherein when the memory device is powered off after being powered off, the controller reads a plurality of latest ones corresponding to the plurality of relatively latest time stamps from the flash memory. Corresponding to the sub-table data, the plurality of latest operation record data corresponding to the plurality of relatively latest time stamps corresponding to the latest corresponding sub-table data are read from the flash memory, and the latest operation record data is sequentially updated according to the latest operation record data. The latest corresponding sub-table data is obtained to obtain a plurality of update corresponding sub-table data, and the update corresponding sub-table data is combined to obtain a latest address correspondence table. The memory device of claim 18, wherein the controller compares a time stamp of a target operation record data in the latest operation record data with a time stamp of the latest corresponding part table data, according to the target operation record The data update corresponds to the corresponding timestamp in the latest corresponding sub-table data. The latest corresponding sub-list data with a small time stamp of the target operation record data, and the latest operation record data corresponding to a time stamp below the time stamp of the target operation record data is the next target operation record data; In the time series, the next timestamp is after the timestamp of the target operation record data. The memory device of claim 19, wherein when the memory device is powered off and then powered back on, and the controller is unable to read an absolute time of the timestamp corresponding to the latest corresponding table data. When the latest operation record data corresponding to the stamp is recorded, the controller reads the physical address of a blank block corresponding to the absolute latest time stamp from the flash memory, and reads the blank block according to the physical address And reconstructing the latest operation record data corresponding to the absolute latest timestamp according to the correspondence between the logical address and the physical address stored in the blank block. The memory device of claim 20, wherein the physical address of the blank block corresponding to the absolute latest timestamp is simultaneously recorded to the fast corresponding data corresponding to the absolute latest timestamp. Flash memory. The memory device of claim 13, wherein the operation record buffer of the memory comprises at least two logic pages, wherein an operation record of one logical page is recorded to the flash memory, Another logical page receives a new operational record.