TW200522258A - Method of forming a dual damascene copper wire - Google Patents

Abstract

The present invention provides a method for forming at least one wire on a substrate. The substrate includes at least one conductive region. An insulating layer is disposed on the substrate. At least one recess in the insulating layer exposes the conductive region. A barrier layer is formed on a surface of the insulating layer and the recess first. A continuous and uniform conductive layer is then formed on a surface of the barrier layer. A seed layer is thereafter formed on a surface of the conductive layer. Finally, a metal layer filling up the recess is formed on a surface of the seed layer.

Description

200522258 V. Description of the invention (1) [Technical Field] The present invention provides a method for manufacturing a double inlaid copper wire, particularly a method capable of providing good copper gap-filling capability and expanding a process window. manufacturing method of double inlaid copper wire. [Previous technology] The dual damascene process is a method that can simultaneously form a metal wire and a plug above and below a stacked structure in a dielectric layer. The dual damascene structure mainly includes an upper trench and a lower contact. A via hole is used to connect different components and wires in each layer of the semiconductor wafer and to isolate the other components from each other by using an inner dielectric material (in ^ er-1 ayerdie 1 ectrics) around it. Because copper has a smaller resistance than aluminum, it can carry a larger current in a smaller area, allowing manufacturers to produce faster, denser circuits, and improve the efficiency of about 30-4 0% of the chip, so The use of double inlay structure to fill copper to produce double inlay. Embedded copper wire has become a mainstream technology. As the development of integrated circuits becomes more sophisticated and complex, how to effectively reduce the complexity of the process and increase the yield of the dual mosaic structure without increasing the cost of production is a very important issue in the current integrated circuit manufacturing process. Please refer to Fig. 1 to Fig. 7. Fig. 1 to Fig. 7 are schematic diagrams of a conventional method for making a pair of inlaid copper wires. As shown in Figure 1, the semiconductor wafer 1 〇 contains

200522258 V. Description of the invention (2) A substrate 12, a conductive layer 14 is disposed in a predetermined area of the surface layer of the substrate 12, and the surface of the conductive layer 4 is covered with silicon nitride (si 1 icon nitride)的 保护 层 16。 The protective layer 16. Since other components on the surface of the substrate 12 are not the focus of the dual damascene process, for convenience of explanation, other components on the surface of the substrate 12 are not shown in Figure 1 and other illustrations. In addition, the surface of the semiconductor wafer 10 further includes a low dielectric constant material layer 18, a protective layer (passivati 〇η 1 aye Γ) 2 〇, a low dielectric constant material layer 22, and a hard cover curtain layer 2 4 Sequentially stacked on the surface of the protective layer. The low dielectric constant material layers 18 and 22 are generally formed of a spin coating low dielectric constant material such as, for example, HSQ or FLARE τ 惭. Due to the characteristics of low dielectric constant materials (especially organic low dielectric fragile), the surface coverage must be 18, u, 丨, 丨 "^ 18 surface coverage is composed of denser materials Silicon nitride layer, to reinforce the low dielectric constant material layer (especially organic low dielectric constant material) has capacitive characteristics, so it must be a protective layer composed of a dense material of the low dielectric constant material layer, such as ( The dielectric constant material layer 18 is hard and broad. M Silicon nitride layer is used to reinforce the low dielectric constant and low dielectric constant 'constant material layer 18 is hard and broad. M ^ For example

—. Photoresist layers 2 6 and 2 6 and another lithography process is performed for subsequent etching or oxynitride or oxynitride as shown in Figure 2. A low dielectric constant structure is formed on the wafer 1 0 Table 1 0 Table One access to a pair of inlays in the semiconductor manufacturing process in 200522258 V. Description of the invention (3) -------------------- One access to low dielectric is formed in the photoresist layer 26 Electric constant material port 27. Since the opening 27 is used to define a pattern of contact holes in the lower layer of the structure 1 ^ ^ 1 and m 肷, the degree of opening 27 must be smaller than the width of the opening ", and the opening 27 is provided in the opening 25 "Internal" to facilitate the subsequent use of self-aligned contact etching process to form a double damascene structure. As shown in Figure 4, then a first etching process, such as an isotropic (an isotropic) In a dry etch process, the low-dielectric-constant material layer 22 and the protective layer 20 not covered by the photoresist layer 26 are removed vertically along the opening 27 to form a low-dielectric-constant material layer ^ The surface opening 2 8. Then a photoresist stripping process (1 ^ 3131: stripping) is performed to completely remove the photoresist layer 26. As shown in Figure 5, then proceed to a second remaining etching process, using protection Layers 20 and 16 are used as stop layers. At the same time, the low-dielectric constant material layer 22 and the low-dielectric constant material layer 18 that are not covered by the hard mask layer 24 are removed at the same time. Removal of the protective layer 2 which is not covered by the hard curtain layer 24; and The protective layer 16 forms a double-mosaic upper trench (^^ 11 (: 11) 30) that penetrates the low dielectric constant material ^ 2 2 and the protective layer 20 at the same time, and self-aligns below the upper trench 30 A via hole 31 of a double damascene structure penetrating the low dielectric constant material layer 18 and the protective layer 16 to the surface of the conductive layer 丨 4 is formed.

200522258 V. Description of the invention (4) In the first step, a deposition process is performed to form a resistive p-early layer 32 on the semiconductor wafer. The barrier layer 32 is formed by nitriding to avoid copper (Cu) or copper in the conductive layers. # W = Scattered into the stone, the barrier layer 32 may also be made of nitride and titanium. / Titanium (Ta / Ti / TiN) and other composite materials, to cover the double-mosaic structure with metal ㉟ • double-mosaic structure between the = a force. After that, a re-sputter process is performed to remove a part of the barrier layer 32 covering the surface of the conductive layer 14 so that the surface of the conductive layer 4 is exposed. A physical vapor deposition (physica [vapor deposit ion, PVD) process is further performed to form a copper seed layer 34 on the surface of the semiconductor wafer 10, so that the copper seed layer 34 is covered and exposed. The conductive layer 14 and the barrier layer 32 come out. The purpose of making the copper seed layer 34 is not only to provide a current-conductive path, but also to provide a copper nucleation layer in advance so that subsequent electrical bell copper can be formed on it. Nuclear and growth. Then, an electric copper plating (ECP) process is performed to form a metal layer 36 on the surface of the copper seed layer 34, and the metal layer 36 fills the upper trench 30 and the lower contact hole 31. As shown in FIG. 7, a chemical mechanical polishing process is then performed, using the barrier layer 32 as the polishing end point (611 (|-? 〇 丨 111 :), removing the area covering the upper trench 30 and the lower contact hole 31 The metal layer 3 6 and the copper seed layer 3 4 ′ make the surface of the metal layer 3 6 remaining in the upper trench 30 and the lower contact hole 31 approximately the same as the surface of the barrier layer 3 2 outside the upper trench 30. Qi Qi.

200522258 「T: Lai Ming⑸Ss ————------------------------ A ^-Finally, a protective layer 38 is formed on the surface of the semiconductor wafer 10 , Such as nitride nitride layer, to complete the production of dual-mosaic copper wire.

Although low-dielectric constant materials and low-resistance copper wires form a perfect match based on the physical properties of the materials, they can effectively reduce the RC delay during signal transmission between wires due to the miniaturization of the component size. (RC de 1 ay) effect. However, such a perfect combination of materials encountered a severe neck in the manufacturing process. Because the copper seed layer 34 is produced by the physical vapor deposition process, and the thin film produced by the physical vapor deposition process cannot provide a good step coverage so as to produce overhangs (〇 \ ^ 61 * 118118) Phenomenon, which in turn causes the copper seed layer 34 to be discontinuous and non-uniform (not con ti nuous and no t un if or m), and finally causes voids to be subsequently filled into the metal layer 36 of the dual damascene structure, that is, the industry The so-called copper filling (C ugap-fi 1 1 ing) problem, and the poor adhesion of the copper crystal layer 34 to the barrier layer 32 (ρ ο 〇radhesi ο nf 〇rce), often makes the metal layer 36 Peeling (pee 1 i ng) occurred during the subsequent chemical mechanical polishing process, which affected the yield of the dual-inlaid copper wire. Please refer to Fig. 8. Fig. 8 is a schematic diagram showing a defect caused by a conventional double-inlaid copper wire. As shown in Figure 8, the phenomenon of overhanging the copper seed layer 42 is most likely to occur at the opening of the contact hole 44 and is prone to discontinuities at the bottom of the contact hole 44. Therefore, the growth of the lower layer and the bottom layer is often caused when copper plating Slower and unable to be bottom up fill behavior. Therefore, after the electroplating is completed, holes 48 will be generated in the metal layer 46.

Page 12 200522258 V. Description of the invention (6) Therefore, how can a new method of making double-inlaid copper wires be developed, which can be used for small line width without increasing the complexity of the process? ) And the double-inlaid structure with high aspect ratio, the copper conductive layer is successfully filled, and the double-inlaid copper wire with low resistance, low surface roughness, and excellent adhesion is produced. Important subject. [Content] Therefore, the main object of the present invention is to provide a method for manufacturing a dual-inlaid copper wire to solve the above-mentioned problems in the conventional technology. A preferred embodiment of the present invention is to provide a method for fabricating at least one wire on a substrate, the substrate including at least one conductive region, an insulating layer disposed on the substrate, and the insulating layer including at least A groove exposing the conductive area. The method includes the following steps: firstly forming a barrier layer on the surface of the insulating layer and the groove, then forming a continuous and uniform conductive layer on the surface of the barrier layer, and then forming a barrier layer on the surface of the conductive layer The seed layer finally forms a metal layer on the surface of the seed layer, and the metal layer completely fills the groove. Because the method for making a dual-inlaid copper wire according to the present invention is to form a conductive layer with excellent conductivity and better step coverage under the copper seed layer, in order to reduce the thickness of the copper seed layer and further improve the copper crystal. Seed layer

Page 13 200522258 V. Description of the invention (7) —------------ —------------! Hanging phenomenon, therefore, the continuity of the copper seed layer With uniformity, the adhesion of the seed layer to the barrier layer will be improved. In addition, j M itself has excellent continuity, uniformity, and good electricity generation: = ability. In the subsequent copper bonding process, the overall conductivity unevenness = ^ = will be significantly improved, making the current distribution very Uniform, and then change the copper filling capacity. At the same time, the process window of the subsequent copper electric clock process “under the current conduction of the conductive layer is very uniform ^ $” can also be significantly enlarged. = In addition, when the copper seed layer is an alloy layer, the alloy atoms in it will attach to the grain boundaries, which will effectively prevent the copper atoms from expanding along the grain boundaries. ^ The reliability of the product can be greatly improved (rel iabi 1 i ty) performance. : [Implementation method] # Please refer to Fig. 9 to Fig. 15, which are schematic diagrams of a method for making more than one inlaid copper wire according to the present invention. As shown in FIG. 9, the semiconductor 100 includes a substrate 102, a conductive layer 104 is disposed in a predetermined area of the substrate 102, and a surface of the conductive layer i04 is covered with a protective layer s (passivation layer) 10. 6. Since the conversion of the surface layer of the substrate 102 is not the focus of the dual mosaic process, it is not shown in Figures 9 to 10/70 for easy explanation. In addition, the surface of the semiconductor wafer is additionally packaged with a number of material layers 108, a protective layer 112, and a low dielectric constant. A low dielectric r and a hard layer u 6 are sequentially stacked on the protective layer 10 6 surface. Accompanied by 1 f e m of silicon nitride, 1 is used as the last name to terminate the reed (… "toplayer), to avoid touching the bottom U in the contact hole, because

200522258 ---------------------_ _ 1 -------------------------- --- * V. Description of the invention (8) —— — __________________________ ________________, which is bad for over etch for over etch. ^ The material of the lower layer severely breaks the low-dielectric constant material layer 108. Low-dielectric lightning ^ * Spin-coated low-dielectric constant material, material η: The material layer I " is usually made by "possibly by chemical vapor deposition" It is formed, but constant materials (especially organic low dielectrics are often formed. Due to the low dielectric properties, it must be a low dielectric thunder number material) with a protective layer composed of dense materials that are easily brittle. The 1 / \ 08 surface is covered by the hardness of the lower dielectric constant material layer 108. Similarly, the H layer is reinforced by 114 and the surface is also covered with the low-constant material layer 116, and the hard cover curtain layer 116. The structure of the engraved mask. After the stacked structure shown in Fig. 9 is formed by lice silicon or lice silicon oxide, the handle is inserted into the shirt ^ and the etching process is in the hard cover sound Π fi / ^ JJ t tt # ,, Φ ,, f // ^ 5; enter the upper groove of the opening, the opening, the opening. It is shown that in the middle of the light, the layer 118 is 27, 118, and the opening of the other lithographic surface is ny, a layer of low dielectric constant material. u 4 Khan] Mouth ii 7. Due to the opening n_Jit / W_i4, the lower contact hole has a mosaic structure ^ ο 117 # ^^^; / Γΐΐ5ίΓ Continue to use self-alignment within $ 1 1 5 to facilitate later The quasi-contact etching is performed to form a dual damascene structure.

200522258 I. Description of the invention (9) Xiang Qiangan's name: Cheng Cheng: J ί;-f 'engraving process, for example-Fei etc. 11W ϋ t 1 \ On / 117 vertical downward removal without photoresist layer , N low ”electric suspension material layer 1 1 4 and protective layer i 丨 2, and then re-entered the opening 122 on the surface of the low dielectric constant material layer 108. Then striPPing),. ^, Ϊ́ ^^ 三"Shown / Next, a second # engraving process is performed, using protection 1, ^ compliance layer 10 6 as the stop layer (st op 1 ay er), and at the same time

^ Into the low dielectric constant material layer 1 1 4 and Luo covered by the mask layer 116, the material layer 1 0 8 is removed, and then the non-hard mask layer 1 1 6 is removed.

=== Bao Zun layer 112 and protective layer 1 〇6, to simultaneously form "the upper layer trench that penetrates the dual damascene structure of the low second I constant material layer 114 and the protective layer n 2 is" standing "and voluntarily under the upper layer 124 Align and form a contact hole 1 2 6 that penetrates the low-second constant material layer 108 and the protective layer 106 until the surface of the conductive layer 104 and the mosaic structure on the surface. In fact, the protective genus 1 1 2 ′ in the middle is also used as an etch stop layer at the same time, so that the surname of the groove 1 2 4 is precisely controlled and consistent. If this etch stop layer is not added, due to non-uniformity, dry load effect (micro-rolling effect) and aspect ratio dependence etching effect (ARDE effect) ), Etc., often make the depth of the trenches 1 2 4 difficult to control and inconsistent.

Page 16 200522258 V. Description of the invention (10) As shown in FIG. 14, a deposition process is then performed to form a barrier layer 1 2 8 on the surface of the semiconductor wafer 100. The barrier layer 1 2 8 is used to prevent the copper (copper, Cu) or tungsten (tungsten, W) in each conductive layer from diffusing into the silicon. The barrier layer 1 2 8 may be a silicon nitride layer. It may be a titanium nitride layer (TiN layer), a nitride nitride layer (TaN layer), or a nitride button / tantalum (Tatalum) compound metal layer for adding Subsequent adhesion between the metal layer on the dual mosaic structure and the dual mosaic structure. Thereafter, a sputtering process is repeatedly performed to remove a part of the barrier layer 1 2 8 covering the surface of the conductive layer 104 so that the surface of the conductive layer 104 is exposed. A chemical vapor deposition process or an atomic layer deposition process is performed to form a continuous and uniform conductive layer 132 on the surface of the barrier layer 128. The conductive layer 132 covers the exposed conductive layer 132. The conductive layer 132 is usually a layer or a tungsten layer, and the thickness of the conductive layer 132 is between 5 and 400 angstroms (A). In fact, any film with a temperature lower than 400 ° C, which has good conductivity and step coverage, and excellent adhesion to the barrier layer 1 2 8 may be used as the conductive layer. 1 32. Then, a physical vapor deposition process is performed to form a copper seed layer 134 with a thickness of 5 to 2000 angstroms on the semiconductor wafer surface, and θθ covers the conductive layer 132 with a seed layer 134. The copper seed layer 134 is made of pure copper, or is made of a copper alloy. The purpose of making the copper seed layer i 34 is

Page 17 200522258 V. Description of the invention (11) — ~ — In addition to the current supply path of k, another important purpose is to provide copper nucleation layer in advance, so that the subsequent electroplated copper can be formed on it. Nuclear and growth. Then, a copper plating process is performed to form a metal layer 1 3 6 on the surface of the copper seed layer i 34, and the metal layer 1 3 6 fills the upper trench 1 2 4 and the lower contact hole 1 2 6. 'Because the conductive layer 1 3 2 has been previously formed on the copper seed layer 1 3 4: the conductive layer 1 3 2 formed by the chemical vapor deposition process or the atomic layer deposition process has a better step coverage. Moreover, the thickness of the copper seed layer 1 3 4 can be correspondingly reduced, thereby improving the overhang phenomenon generated when the copper seed layer 1 34 is formed by the physical vapor deposition process, and further the copper seed layer ^ layer 1 3 The continuity and uniformity of 4 and the improvement of the adhesion of the barrier layer. In addition, the conductive layer 132 has a very good uniformity of current conduction. In the subsequent copper electroplating process, the phenomenon of overall uneven conduction will be significantly improved, so that the distribution of current is uniform and the copper filling ability is improved. As shown in FIG. 15, a chemical machine is then used to remove the metal layer 136, the copper seed layer 134, and the conductive layer covering the upper layer. The trench 124 and the lower contact hole 126 are used as the polishing end point. 1 3 2 ′ and the surface of the metal layer 1 3 6 remaining in the upper trench 1 2 4 and the lower contact hole 1 2 6 is approximately tangent to the surface of the barrier layer i 2 8 outside the upper trench j 2 4. Finally, a protective layer 138, such as a silicon layer, is formed on the surface of the semiconductor wafer 100 to complete the fabrication of the dual-inlaid copper wire.

Page 18, 200522258 V. Description of the invention (12) It is worth mentioning that the conductive layer 104 is not limited to the shape and position shown in FIGS. 9 to 15 because the conductive layer 104 may be a transistor ( transist 〇r) source, a transistor gate, a transistor drain, i〇wer level wire, a landing pad Or it is a resistor, so its shape and position can be changed accordingly. In addition, the method of the present invention can be applied to a trench first dual-embedding process as shown in FIGS. 9 to 15 as well as a via first dual-embedding process. The pattern of the copper plug is etched first, and then the pattern of the copper wire is etched. The other parts are similar to the embodiment of the present invention. At the same time, the method of the present invention can also be applied to a self-aligned dual-embedding process. The hard mask layer of silicon nitride is formed in the interlayer dielectric layer, and the contacts are etched in the hard mask layer. The rest of the graphics required for the hole are similar to the dual-embedding process for the trench first and the dual-embedding process for the dielectric window first. In addition, the method of the present invention can also be applied to a silicon-on-insulator substrate (SOI substrate). Because the method of making a dual-inlaid copper wire in the present invention is formed before the copper seed layer A conductive layer with excellent conductivity and better step coverage to reduce the thickness of the copper seed layer and further improve the overhang of the copper seed layer. In this way, the continuity and uniformity of the copper seed layer , And the ability of the copper seed layer to adhere to the barrier layer will be improved. Plus

Page 19, 200522258 V. Description of the invention (13) The conductive layer itself has excellent continuity, uniformity and good current conduction capacity. In the subsequent copper electroplating process, the overall conductivity unevenness will be significantly improved. Make the current distribution uniform, and then improve the copper filling ability. When the method of the present invention is applied in actual production, the copper filling ability of the dual-mosaic structure with small line width and high aspect ratio can be improved, and a dual-surface embedded copper wire with low resistance, low surface roughness, and excellent adhesion can be produced. Compared with the conventional technology, the method for making a dual-inlaid copper wire according to the present invention is to form a conductive layer with excellent conductivity and better step coverage under the copper seed layer to reduce the thickness of the copper seed layer. , And thus improve the overhang of the copper seed layer. Therefore, the continuity and uniformity of the copper seed layer, and the adhesion ability of the copper seed layer to the barrier layer will be improved. In addition, the conductive layer itself has excellent continuity, uniformity, and good current conduction capacity. Therefore, in the subsequent copper electroplating process, the overall conductivity unevenness will be significantly improved, making the current distribution very uniform. This improves copper filling capacity. At the same time, under the premise that the current conduction of the conductive layer is very uniform, the process window of the subsequent copper electroplating process can also be significantly enlarged. In addition, when the copper seed layer is an alloy layer, the alloy atoms therein will be adsorbed on the grain boundaries, thereby effectively preventing the diffusion of copper atoms along the grain boundaries, which will greatly improve the reliability of the product (re 1 iabi 1 ity) Performance 0 The above description is only a preferred embodiment of the present invention.

Page 20 200522258 V. Description of the invention (14) Equal changes and modifications made within the scope of the invention shall all fall within the scope of the invention patent. 200522258 ‘· Simple illustration of the diagrams Simple illustration of the diagrams Figures 1 to 7 are schematic diagrams of a conventional method for making a pair of inlaid copper wires. FIG. 8 is a schematic diagram showing defects caused by a conventional double-inlaid copper wire. Figures 9 to 15 are schematic diagrams of a method of making a double inlaid copper wire according to the present invention. Explanation of the symbols of the drawing 12 substrate 16 protective layer 2 0 protective layer 24 hard cover curtain layer 28 opening 31 contact hole 3.4 copper seed layer 3 8 yoke layer 44 contact hole 48 hole 102 substrate 1 0 6 protective layer 1 1 2 protection Layer 115 Opening 10 Semiconductor wafer 14 Conductive layer 18 Low dielectric constant material layer 22 Low dielectric constant material layer 26 Photoresist layer 30 Trench 32 Barrier layer 3 6 Metal layer 4 2 Copper seed layer 4 6 Metal layer 1 0 0 Semiconductor wafer 1 04 Conductive layer 1 0 8 Low dielectric constant material layer 1 1 5 Low dielectric constant material layer

Page 22 200522258 Brief description of the drawings 1 1 6 Hard cover curtain layer 1 1 8 Photoresist layer 1 2 4 Trench 1 2 9 Barrier layer 1 3 4 Copper seed layer 1 3 8 Protective layer 117 Opening 122 Opening 1 2 6 contact hole 132 conductive layer 1 3 6 metal layer

Page 23

Claims (1)

200522258 1 _ 26. Patent application scope 1. A method for making at least one wire on a substrate, the substrate includes at least one conductive region, an insulating layer is disposed on the substrate, and the insulation The layer includes at least one recess that exposes the conductive region. The method includes the following steps: forming a barrier layer on the insulating layer and the surface of the recess; and forming a barrier layer on the barrier layer A continuous and uniform conductive layer is formed on the surface; a seed layer is formed on the surface of the conductive layer; and a metal layer is formed on the surface of the seed layer, and The metal layer completely fills the groove. m 2. The method according to item 1 of the scope of patent application, wherein the substrate comprises a semiconductor wafer or a silicon-on-insulator substrate (SOI substrate). The method of item 1, wherein the conductive region comprises a source of a transistor, a gate of a transistor, and a drain of a transistor. (lower level wire), an ian (jing pad), or an electric PJL (resistor). 4 · The method of item 1 in the scope of patent application, wherein the groove is a dual damascene Structure contact holes (via hole). Page 24 200522258 VI. Application for Patent Scope 5. The method according to item 1 of the patent application scope, wherein the barrier layer includes a silicon nitride layer (titanium nitride layer), a titanium nitride layer (TiN) layer), a nitrogen nitride layer (tantalum nitride layer, TaN layer), or a tantalum nitride / group (tantalum, Ta) composite metal layer. 6. The method according to item 1 of the patent application, wherein the conductive layer is an aluminum layer or a tungsten layer 0 7. The method according to item 1 of the patent application, wherein the conductive layer is The thickness of the layer is between 5 and 400 Angstroms (A). 8. As the method of claim 7, the method of forming the conductive layer includes chemical vapor deposition (CVD) or It is atomic layer deposition. 9. The method according to item 1 of the scope of patent application, wherein the seed layer is a copper layer formed by a physical vapor deposition (PVD) process. 10. The method according to item 1 of the scope of patent application, wherein the seed layer is a copper alloy layer formed by a physical vapor deposition process. Page 25 200522258 VI. Application for Patent Scope 1 1. The method according to item 1 of the patent application scope, wherein the thickness of the seed layer is between 5 and 2000 angstroms (A). 12. The method according to item 1 of the scope of patent application, wherein the metal layer is formed by an electric copper plating (ECP) process. 13. A method of making at least one dual damascene wire (wire) on a substrate, the substrate including at least one conductive region, an insulating layer disposed on the substrate, and the insulating layer The method includes at least one trench pattern and a via hole pattern stacked on top of each other and exposing the conductive region. The method includes the following steps: the insulating layer, the trench pattern, and the contact hole pattern. A barrier layer is formed on the surface; a continuous and uniform conductive layer is formed on the surface of the barrier layer; a seed layer (seed 1) is formed on the surface of the conductive layer ayer); and forming a metal layer on the surface of the seed layer, and the metal layer completely fills the trench pattern and the contact hole pattern. 14. The method according to item 13 of the scope of patent application, wherein the substrate includes a semiconductor wafer or a si 1 icon-on-insulator substrate (SOI substrate). Page 26, 200522258 VI. Application scope of patents '1 5 · The method of item No. 13 of the scope of patent application', wherein the conductive region ^ waits, ^ contains the source of a transistor, the transistor ^ A gate, a transistor drai η, a lower layer conductor, a lower level wire, a landing pad, or a resistor. 16 · The method according to item 13 of the patent application scope, wherein the barrier layer comprises a silicon nitride layer, a titanium nitride layer (TiN layer), and a tantalum nitride layer Layer (tantalum nitride layer, TaN layer) or a nitride group / group (tantalum, Ta) composite metal layer. 1 7. The method according to item 13 of the patent application scope, wherein the conductive layer is an aluminum layer or a tungsten layer. 1 8. The method according to item 13 of the scope of patent application, wherein the method for forming the conductive layer includes chemical vapor deposition (CVD) or atomic layer deposition, and the conductive layer The thickness is between 5 and 400 Angstroms (A). 19. The method according to item 13 of the scope of patent application, wherein the seed layer is a copper layer formed by a physical vapor deposition (PVD) process, and the thickness of the seed layer is interposed Between 5 and 2 0 0 0 Angstroms Page 27 Ί C j 200522258 6. Scope of patent application (A). 20. The method according to item 13 of the patent application range, wherein the seed layer is a copper alloy layer formed by a physical vapor deposition process, and the thickness of the seed layer is between 5 and 2 0 0 Egypt (A). 2 1. The method according to item 13 of the scope of patent application, wherein the metal layer is formed by an electric copper plating (ECP) process.