TW200521271A - A method and structure for wafer of semiconductive material - Google Patents
A method and structure for wafer of semiconductive material Download PDFInfo
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200521271 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關一種形成一半導體材料晶圓的方法與結 構,其特別是關於一種形成具有犧牲層之晶圓的方法與結 【先前技術】 C Z單晶成長程序乃源自1 9 1 8年即由c Z 0 c h r a 1 s k i之結 晶速度理論為名’真正用於矽單晶成長約在1 g 5 2年由τ e a 1 及B u e h 1 e r首度發表,經由不斷的技術改良以便成長更大 尺寸及更完美的晶體,至今所廣為使用的Μ法長零差排 (Dislocation-free)石夕單晶乃由Das h首度開發成功之方 法。 此一方法概可分為以下之步驟:(1)原料堆放(p〇ly200521271 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method and structure for forming a semiconductor material wafer, and more particularly, to a method and structure for forming a wafer with a sacrificial layer [prior art] ] The CZ single crystal growth process is derived from the crystallization speed theory of c Z 0 chra 1 ski in 1918, named 'True for silicon single crystal growth in about 1 g 5 2 years by τ ea 1 and Bueh. 1 er was published for the first time. Through continuous technological improvements to grow larger and more perfect crystals, the widely used M-method long-distance dislocation-free Shi Xi single crystal was first developed by Das h. Ways to success. This method can be divided into the following steps: (1) raw material storage (p〇ly
Charging) (2)炼融(Meltdown) (3)長頸部(Necking) 及晶冠(Crown) (4)長主體(Body) (5)收尾(Tail growth)。 (1 )原料堆放及(2 )炼融一將一個全新的石英掛竭放入 石墨坩堝内,再將多晶矽塊及合金料放入石英坩堝裡。為 減少石夕塊與掛瑪磨擦造成的石英碎粒,放料過程需小心, 挑直徑大的矽塊放置堝底及堝側,合金料放置料堆中心。 然後關閉爐體,抽真空,測漏氣率,在高於u 加熱至完全熔化,再保持一段時間,以便融熔 勻混合。若以塊狀及粒狀多晶原料混合使用,則在塊狀原 料即將完全熔化前,再將顆粒狀原料由爐側緩緩加入,以 達預定的總原料量《再保持一段時間,以利氣體揮發,液Charging) (2) Meltdown (3) Necking and Crown (4) Body (5) Tail growth. (1) Stacking of raw materials and (2) Smelting. Put a brand-new quartz into a graphite crucible, and then put polycrystalline silicon blocks and alloy materials into the quartz crucible. In order to reduce the quartz particles caused by the friction between Shixi block and hanging horse, care must be taken in the discharging process. Pick a silicon block with a large diameter and place it on the bottom and side of the pot, and place the alloy on the center of the stack. Then close the furnace, evacuate, measure the leak rate, heat it above u to completely melt, and keep it for a while to melt and mix. If the block and granular polycrystalline raw materials are mixed and used, before the block raw materials are completely melted, the granular raw materials are slowly added from the furnace side to achieve a predetermined total amount of raw materials. Gas volatility, liquid
第7頁 200521271 五、發明說明(2) 體溫度、坩堝溫度及熱場達成穩定平衡態。 (3 )長頸部至(5 )收尾一融熔液面溫度的微調,大夕曰 靠晶體浸入液面,觀察其融化狀況而完成。以 + &夕疋 „, ,«(!. 7xl. 7x2. tcm) ^ 〇. 3cm。若此晶種浸泡處被輕易炼化’則需降低 輸出功率。若即刻有樹枝狀多晶從浸泡處向·… 增高輸出功率。在適當溫度下,晶種旋轉上 曰,則需 端拉出直徑0. 5〜0. 7cm的新單晶體,稱之為「:晶種浸泡 頸子的直徑生長速度及内部品質好壞,全^ 頊子」。此 月的技藝所控帝i。長頸子的目的是除去晶者經年累 時導致的塑性變形之缺陷,例如差排 機械加工成形 孔洞(Vacancy),或者晶種觸接融 〇cati〇n)及 缺陷。 4加熱導致的 之後,成長完的鑄塊(ingot)被切叫成去 =狀晶圓後,便可於晶圓上成長元件所需的\為若干片的 :片晶圓的得來不易,因此,當晶圓於後^;構。正因為 外在因素造成晶圓邊緣甚至本體產生碎-製程中若因為 透過儀器方可檢視到•,往往已經 j且碎裂處必須 。 許夕的資源與成本 ‘、【發明内容】 對於上述缺失,欲避免晶圓於製程中 情形’本發明之主要目的係在提供 J 土邊緣碎裂的 ::方法與結使其於形成晶圓鑄塊j半導體材料晶 層的步驟與結構,以避免晶圓產生邊緣。=形成犧 ’鬏的情形。Page 7 200521271 V. Description of the invention (2) The body temperature, crucible temperature and thermal field reach a stable equilibrium state. (3) Fine adjustment of the melt surface temperature from the long neck to the end of (5). Day Xi Yue finishes by immersing the crystal in the liquid surface and observing the melting condition. + &; 疋 疋 ,, «(!. 7xl. 7x2. Tcm) ^ 0.3cm. If this seed is soaked, it is necessary to reduce the output power. If there is an immediate dendritic polycrystal from the soak To increase the output power. At an appropriate temperature, the seed crystal rotates, and a new single crystal with a diameter of 0.5 to 0.7 cm needs to be pulled out at the end, which is called ": seed crystal soaking neck diameter growth rate and The internal quality is good or bad. This month's skills are controlled by Emperor i. The purpose of the long neck is to remove the defects of plastic deformation caused by the crystals over time, such as differential row machining and forming holes (Vacancy), or seed contact melting (cacation) and defects. 4After heating, the ingot that has been grown is cut into a wafer. After the ingot is grown, you can grow several components on the wafer. The number of wafers is not easy. Therefore, when the wafer is later constructed. It is because of external factors that the wafer edge or even the body is broken-if • can be viewed through the instrument during the manufacturing process, it is often j and the crack must be. Xu Xi's Resources and Costs "[Summary of the Invention] For the above-mentioned shortcomings, to avoid the situation of wafers in the manufacturing process, the main purpose of the present invention is to provide J: the edge of the soil is fragmented :: methods and knots for forming wafers Steps and structure of crystal layer of semiconductor material in ingot j to avoid wafer edge. = A situation where sacrifices are formed.
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本發明之另一目的係在提供一種形成具有介電層犧牲 層之晶圓的方法與結構,利用簡易的步驟,可應用於各種 尺寸的晶圓。 為達到上述目的’本發明提出一種形成一半導體材 晶圓的方法’先形成半導體材料的一鑄塊(ing〇t),复 係具有一第一表面;之後,形成一第一介電層於第一表、 上,其係具有一第二表面,其中第二表面大於第一表面 再形成一第二介電層於第二表面上,其係具有一第- ’ ,其中第三表面大於第二表面。 ^ 二表面 本發明之另一實施態樣係在提出一種半導體曰^ ,包含一片狀核心,其由一半導體材料形成,其中圓結構 心具有一第一外周邊;一第一環狀部分與此第—片狀核 鄰,並以一第一介電材料形成,其中第一環狀部=周邊相 第二外周邊大於第一外周邊;一第二環狀部分^ $具有〜 邊相鄰,其係以一第二介電材料形成,其中第二如二外周 具有一第三外周邊大於第二外周邊。 一㉟狀部分 底下藉由具體實施例配合所附的圖式詳 女旦路姑丰於nn t 一 . 說明 .. 容易瞭解本發明之目的、技 效0 的、技術内容、 特點及其所達 ’當更 四、【實施方式】Another object of the present invention is to provide a method and structure for forming a wafer with a sacrificial layer of a dielectric layer, which can be applied to wafers of various sizes with simple steps. In order to achieve the above object, the present invention proposes a method for forming a semiconductor material wafer. First, an ingot of semiconductor material is formed, which has a first surface. Then, a first dielectric layer is formed on On the first table, it has a second surface, wherein the second surface is larger than the first surface and a second dielectric layer is formed on the second surface, and it has a first-', wherein the third surface is larger than the first Two surfaces. ^ Two-surface Another aspect of the present invention is to propose a semiconductor, including a piece of core, which is formed of a semiconductor material, wherein the center of the circular structure has a first outer periphery; a first annular portion and This first sheet-shaped core is adjacent to each other and is formed of a first dielectric material, wherein the first annular portion = peripheral phase, and the second outer periphery is larger than the first outer periphery; a second annular portion ^ $ 有 〜 It is formed of a second dielectric material, wherein the second outer periphery has a third outer periphery larger than the second outer periphery. A detailed description is provided below with a detailed description of the accompanying drawings and the attached drawings. Women's dan Lugu Feng Yu nn t. Explanation: It is easy to understand the purpose, technical effect, technical content, characteristics and achievement of the present invention. 'Dang Geng IV. [Implementation]
種形成半導體材料晶圓的方 鱗塊之時’增加形成犧牲層 避免晶圓產生邊緣碎裂的情 於各種不同尺寸的晶圓。When forming a square scale of a semiconductor material wafer, the formation of a sacrificial layer is increased to avoid edge chipping of the wafer due to various wafer sizes.
結構 與結 此方Structure and knot
200521271 五、發明說明(4) 如第一 A圖所示,其係盘士 ^ - jfc. jg, 、#本發明成長一半導體躊塊的 側面不思圖’於一鑄塊支擇萝番 1 · X 1 0ttr . , 衣直(1 ngot support mi住一半導體材料的禱塊1〇。此 鐺二ϊ Ϊ當綱形如習知的 ^ ,鑄塊1 〇之半導體材料可以為矽或砷化鎵 等-般作為曰曰圓的半導體材料,不限於上述。於一實施 例中’成長的鑄塊1 〇可作為4忖至i 2时晶圓所需的铸塊, 《、不限於此,A於12吋的晶圓亦不脫離本發明方法與結構 第一 B圖為本發明將鑄塊置入一反應室中形成一第一 介電層的側面不意圖,如圖所示,成長後的鑄塊丨〇具有一 枉狀部分(P 1 1 1 ar)表面1 4,此表面丨4形成一外周邊。鑄 塊10經過研磨(polishing)處理後,置入一反應室16中 藉以形成一第一介電層24,請同時參閱第二圖所示,亦 即,鑄塊1 0於反應室1 6中被加熱,於表面丨4上形成一氧化 層1 8,例如一氧化矽,其厚度可視所需而定。 之後,參照第一 C圖所示,為本發明將鑄塊置入一反 應室中一第二介電層的側面示意圖。對於已覆蓋氧化層的 鑄塊10,於相同的反應室16或另一反應室中,形成一第二 介電層26於第一介電層24表面上,請同時參閱第二圖所示 較佳者,係利用化學或物理氣相沉積方式,於氧化層表 面上沉積一氮化層,例如一氮化矽,其厚度可視所需而定 之後,如第一 D圖所示,其係為本發明將具有第一與200521271 V. Description of the invention (4) As shown in the first figure A, it is Panshi ^-jfc. Jg, # # The present invention grows a side view of a semiconductor block, and chooses Luofan in a casting block 1 · X 1 0ttr., Yi Zhi (1 ngot support mi live a prayer block of a semiconductor material 10. This clang ϊ Ϊ When the outline is like the conventional ^, the semiconductor material of the ingot 10 can be silicon or arsenic Gallium and the like are generally used as round semiconductor materials and are not limited to the above. In one embodiment, the 'grown ingot 10' can be used as the ingot required for the wafer at 4 忖 to i 2. A 12-inch wafer does not depart from the method and structure of the present invention. The first diagram B is the side view of the invention where the ingot is placed in a reaction chamber to form a first dielectric layer. As shown in the figure, after growing, The ingot has a surface (P 1 1 1 ar) surface 1 4 which forms an outer perimeter. After the ingot 10 is polished, it is placed in a reaction chamber 16 to form A first dielectric layer 24, please also refer to the second figure, that is, the ingot 10 is heated in the reaction chamber 16 and is formed on the surface 4 The thickness of the oxide layer 18, such as silicon monoxide, may be determined as needed. Then, referring to FIG. 1C, a schematic side view of a second dielectric layer in which the ingot is placed in a reaction chamber according to the present invention is shown. For the ingot 10 covered with an oxide layer, a second dielectric layer 26 is formed on the surface of the first dielectric layer 24 in the same reaction chamber 16 or another reaction chamber. Please refer to the second figure for comparison. The best one is to deposit a nitride layer, such as a silicon nitride, on the surface of the oxide layer by chemical or physical vapor deposition. After the thickness is determined as required, as shown in the first D diagram, it is The invention will have a first and
第10頁 200521271Page 10 200521271
五、發明說明(5) 不意圖。利用 (sawing), 其厚度可視所 第二介電層的柱狀鑄塊切割成為晶圓的側面 傳統的技術,將鑄塊1 0的柱狀部分進行切割 以成為若干片片狀晶圓(slip wafer) 20, 需而定。 第二圖為本發明之晶圓的正視示意圖,‘& 如圖所示,曰 圓20具有一片狀核心22、環狀第一介電層24與产心哲一曰曰 電層26。片狀核心22係由柱狀鑄塊切片而成,计 1 "八 7 圍 目 t . 一外周邊3 0,此片狀核心2 2的外周邊3 0與環狀^二入八有 24相鄰;環狀第一介電層24係具有一内緣與—外周^電2 中,内緣緊鄰片狀核心2 2的外周邊3 0,因此環狀^ 一丄其5. Description of the invention (5) Not intended. Using sawing, the thickness of the columnar ingot of the second dielectric layer can be cut into the side of the wafer. The conventional technique is to cut the columnar portion of the ingot 10 into a number of wafers. wafer) 20, subject to availability. The second figure is a schematic front view of the wafer of the present invention. As shown in the figure, the circle 20 has a sheet-shaped core 22, a ring-shaped first dielectric layer 24, and an electric core layer 26. The lamellar core 22 is sliced from a column-shaped ingot, which is counted as 1 " eight 7 girth t. An outer periphery 30, the outer periphery 3 of this lamellar core 2 2 and a ring ^ two into eight 24 Adjacent; the ring-shaped first dielectric layer 24 has an inner edge and-the outer periphery ^ electricity 2, the inner edge is close to the outer periphery 30 of the sheet core 2 2, so the ring ^
層2 4的内緣與外周邊3 〇大致相等。其次,由於第一介^ 24覆蓋於桎狀鑄塊丨〇上具有一厚度,即第一 c圖中的;1第1一^ 介電層2 4表面將大於鑄塊1 〇的表面,因此環狀第一介電層 2 4的外周邊3 2將大於片狀核心2 2的外周邊3 〇。知门二 1 ,丨你_人 子目同地,環 狀第二介電層2 6係具有一内緣與一外周邊,其内緣緊鄰環 狀第一介電層24的外周邊32,而環狀第二介電層'26的外^ 邊34將大於環狀第一介電層24的外周邊32。 "The inner edge of the layer 24 is approximately equal to the outer periphery 30. Secondly, since the first dielectric layer 24 covers the 桎 -shaped ingot 丨 0 with a thickness, that is, in the first c figure; 1 the first ^ dielectric layer 24 surface will be larger than the surface of the ingot 10, so The outer periphery 32 of the annular first dielectric layer 24 will be larger than the outer periphery 30 of the sheet-like core 22. Zhimen II1, you_renzimu. In the same place, the ring-shaped second dielectric layer 26 has an inner edge and an outer periphery, and the inner edge is close to the outer periphery 32 of the ring-shaped first dielectric layer 24. The outer edge 34 of the annular second dielectric layer '26 will be larger than the outer periphery 32 of the annular first dielectric layer 24. "
綜上所述,於片狀核心2 2外周邊有環狀第〜介電層2 4 與環狀第二介電層26所保護,提供製程中夾具挾持之^, 可避免夾具因過於接近片狀核心22處,造成其外力可能導 致晶圓的邊緣碎裂。因此,本發明之環狀第一介電層24與 環狀第二介電層2 6可作為犧牲層之用,保護晶圓,減少晶 圓於製程中損毀報廢的比率。 以上所述之實施例僅係為說明本發明之技術思想及特To sum up, the outer periphery of the sheet core 2 2 is protected by a ring-shaped first dielectric layer 2 4 and a ring-shaped second dielectric layer 26, which can provide jig holding during the manufacturing process, which can prevent the jig from being too close to the sheet. At the core 22, the external force may cause the edge of the wafer to chip. Therefore, the ring-shaped first dielectric layer 24 and the ring-shaped second dielectric layer 26 of the present invention can be used as a sacrificial layer to protect the wafer and reduce the rate of damage to the wafers during the process. The embodiments described above are only for explaining the technical ideas and features of the present invention.
第11頁 200521271 五、發明說明(6) 點,其目的在使熟習此項技藝之人士能夠瞭解本發明之内 容並據以實施,當不能以之限定本發明之專利範圍,即大 凡依本發明所揭示之精神所作之均等變化或修飾,仍應涵 蓋在本發明之專利範圍内。 【圖號說明】Page 11 200521271 V. Description of the invention (6) The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. When the scope of the patent of the present invention cannot be limited, it means Equal changes or modifications made by the disclosed spirit should still be covered by the patent scope of the present invention. [Illustration of drawing number]
10 鑄 塊 12 鑄 塊 支 撐 裝置 14 表 面 16 反 應 室 20 晶 圓 22 片 狀 核 心 24 第 一 介 電 層 26 第 二 介 電 層 30 外 周 邊 32 外 周 邊 34 外 周 邊 第12頁 200521271 圊式簡單說明 第一A圖為本發明於成長一半導體鑄塊的平面示意圖。 第一 B圖為本發明將鑄塊置入一反應室中形成一第一介電 層的平面示意圖。 第一 C圖為本發明將鑄塊置入一反應室中一第二介電層的 平面示意圖。 第一 D圖為本發明將具有第一與第二介電層的柱狀鑄塊鋸 開成為晶圓的側面示意圖。 第二圖為本發明形成之晶圓結構的正視示意圖。10 Ingot 12 Ingot support 14 Surface 16 Reaction chamber 20 Wafer 22 Flaky core 24 First dielectric layer 26 Second dielectric layer 30 Outer periphery 32 Outer periphery 34 Outer periphery Page 12 200521271 An A diagram is a schematic plan view of a semiconductor ingot growing in the present invention. FIG. 1B is a schematic plan view of the present invention where the ingot is placed in a reaction chamber to form a first dielectric layer. FIG. 1C is a schematic plan view of a second dielectric layer in which an ingot is placed in a reaction chamber according to the present invention. FIG. 1D is a schematic side view of the present invention sawing a columnar ingot having first and second dielectric layers into a wafer. The second figure is a schematic front view of a wafer structure formed by the present invention.
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