TW200516727A - Nonvolatile memories and methods of fabrication - Google Patents

Nonvolatile memories and methods of fabrication

Info

Publication number
TW200516727A
TW200516727A TW093123005A TW93123005A TW200516727A TW 200516727 A TW200516727 A TW 200516727A TW 093123005 A TW093123005 A TW 093123005A TW 93123005 A TW93123005 A TW 93123005A TW 200516727 A TW200516727 A TW 200516727A
Authority
TW
Taiwan
Prior art keywords
gate layer
layer
control gate
over
control
Prior art date
Application number
TW093123005A
Other languages
Chinese (zh)
Other versions
TWI247390B (en
Inventor
Yi Ding
Original Assignee
Mosel Vitelic Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/631,552 external-priority patent/US6962852B2/en
Application filed by Mosel Vitelic Inc filed Critical Mosel Vitelic Inc
Publication of TW200516727A publication Critical patent/TW200516727A/en
Application granted granted Critical
Publication of TWI247390B publication Critical patent/TWI247390B/en

Links

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

To fabricate a nonvolatile memory, a select gate (140) is formed over a semiconductor substrate. A dielectric (810,1010,1030) is formed over the select gate. A floating gate layer (160), e.g. doped polysilicon, is formed over the select gate. The floating gate layer is removed from over at least a portion of the select gate. A dielectric (1510), e.g. ONO, is formed over the floating gate layer, and a control gate layer (170) is formed over this dielectric. The control gate layer has an upward protrusion over the select gate. Then another layer (1710), e.g. silicon nitride, is formed on the control gate layer, but the protrusions of control gate layer are exposed. The exposed portion of the control gate layer is etched selectively until the control gate layer is removed from over at least a portion of the select gate. Then another layer (1910) is formed on the exposed portion of the control gate layer. This is thermally grown silicon dioxide in some embodiments. Then the silicon nitride is removed. The control gate layer, the ONO, and the floating gate layer are etched selectively to the silicon dioxide to define the control and floating gates. Other embodiments are also provided.
TW93123005A 2003-07-30 2004-07-30 Nonvolatile memories and methods of fabrication TWI247390B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/631,552 US6962852B2 (en) 2003-03-19 2003-07-30 Nonvolatile memories and methods of fabrication

Publications (2)

Publication Number Publication Date
TW200516727A true TW200516727A (en) 2005-05-16
TWI247390B TWI247390B (en) 2006-01-11

Family

ID=34273237

Family Applications (1)

Application Number Title Priority Date Filing Date
TW93123005A TWI247390B (en) 2003-07-30 2004-07-30 Nonvolatile memories and methods of fabrication

Country Status (3)

Country Link
JP (1) JP2005051244A (en)
CN (1) CN100395881C (en)
TW (1) TWI247390B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10535574B2 (en) 2017-09-20 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Cell-like floating-gate test structure
US11264292B2 (en) 2017-09-20 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Cell-like floating-gate test structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100751418B1 (en) * 2007-02-08 2007-08-22 엘지전자 주식회사 Gas Burner and Heating device using the same
CN111373533B (en) * 2018-05-17 2023-09-29 桑迪士克科技有限责任公司 Three-dimensional memory device including hydrogen diffusion barrier structure and method of fabricating the same

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940006094B1 (en) * 1989-08-17 1994-07-06 삼성전자 주식회사 Nonvolatile semiconductor memory device and fabricating method thereof
JPH06120515A (en) * 1992-10-09 1994-04-28 Oki Electric Ind Co Ltd Method for writing-in and erasing data of semiconductor non-volatile memory
US5445983A (en) * 1994-10-11 1995-08-29 United Microelectronics Corporation Method of manufacturing EEPROM memory device with a select gate
US5856943A (en) * 1996-03-18 1999-01-05 Integrated Memory Technologies, Inc. Scalable flash EEPROM memory cell and array
US6005807A (en) * 1998-09-16 1999-12-21 Winbond Electronics Corp. Method and apparatus for self-aligned memory cells and array using source side injection
US6091104A (en) * 1999-03-24 2000-07-18 Chen; Chiou-Feng Flash memory cell with self-aligned gates and fabrication process
US6962851B2 (en) * 2003-03-19 2005-11-08 Promos Technologies, Inc. Nonvolatile memories and methods of fabrication

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10535574B2 (en) 2017-09-20 2020-01-14 Taiwan Semiconductor Manufacturing Co., Ltd. Cell-like floating-gate test structure
US11088040B2 (en) 2017-09-20 2021-08-10 Taiwan Semiconductor Manufacturing Company, Ltd. Cell-like floating-gate test structure
US11264292B2 (en) 2017-09-20 2022-03-01 Taiwan Semiconductor Manufacturing Company, Ltd. Cell-like floating-gate test structure

Also Published As

Publication number Publication date
CN1585109A (en) 2005-02-23
CN100395881C (en) 2008-06-18
TWI247390B (en) 2006-01-11
JP2005051244A (en) 2005-02-24

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