TW200512725A - A method of determining a merging bit in an optical storage device - Google Patents

A method of determining a merging bit in an optical storage device

Info

Publication number
TW200512725A
TW200512725A TW092126903A TW92126903A TW200512725A TW 200512725 A TW200512725 A TW 200512725A TW 092126903 A TW092126903 A TW 092126903A TW 92126903 A TW92126903 A TW 92126903A TW 200512725 A TW200512725 A TW 200512725A
Authority
TW
Taiwan
Prior art keywords
sum
digital
determining
storage device
optical storage
Prior art date
Application number
TW092126903A
Other languages
English (en)
Other versions
TWI277064B (en
Inventor
Tsung-Huei Ren
Original Assignee
Ati Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ati Corp filed Critical Ati Corp
Priority to TW092126903A priority Critical patent/TWI277064B/zh
Priority to US10/707,837 priority patent/US6853319B1/en
Publication of TW200512725A publication Critical patent/TW200512725A/zh
Application granted granted Critical
Publication of TWI277064B publication Critical patent/TWI277064B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M5/00—Conversion of the form of the representation of individual digits
    • H03M5/02—Conversion to or from representation by pulses
    • H03M5/04—Conversion to or from representation by pulses the pulses having two levels
    • H03M5/14—Code representation, e.g. transition, for a given bit cell depending on the information in one or more adjacent bit cells, e.g. delay modulation code, double density code
    • H03M5/145—Conversion to or from block codes or representations thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G11B2020/1461—8 to 14 modulation, e.g. the EFM code used on CDs or mini-discs
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
    • G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
    • G11B2020/1469—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof modulation code with one or more merging bits between consecutive codewords

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Theoretical Computer Science (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
TW092126903A 2003-09-29 2003-09-29 A method of determining a merging bit in an optical storage device TWI277064B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW092126903A TWI277064B (en) 2003-09-29 2003-09-29 A method of determining a merging bit in an optical storage device
US10/707,837 US6853319B1 (en) 2003-09-29 2004-01-16 Method of determining a merging bit in an optical storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW092126903A TWI277064B (en) 2003-09-29 2003-09-29 A method of determining a merging bit in an optical storage device

Publications (2)

Publication Number Publication Date
TW200512725A true TW200512725A (en) 2005-04-01
TWI277064B TWI277064B (en) 2007-03-21

Family

ID=34102253

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092126903A TWI277064B (en) 2003-09-29 2003-09-29 A method of determining a merging bit in an optical storage device

Country Status (2)

Country Link
US (1) US6853319B1 (zh)
TW (1) TWI277064B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI395226B (zh) * 2008-11-07 2013-05-01 Silicon Motion Inc 測試儲存裝置的方法及其系統

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007026601A (ja) * 2005-07-21 2007-02-01 Sony Corp 情報記録処理装置、および情報記録処理方法、並びにコンピュータ・プログラム

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210711A (en) * 1992-02-26 1993-05-11 Sony Corporation Of America Very fast variable input multi-bit adder
KR100294893B1 (ko) * 1999-03-09 2001-07-12 윤종용 개선된 ｄｃ 억압 능력을 갖는 ｒｌｌ 코드 생성 방법 과 생성된 ｒｌｌ 코드 변복조 방법
KR100669623B1 (ko) * 2001-03-12 2007-01-15 엘지전자 주식회사 디지털 데이터 변환방법
KR100421004B1 (ko) * 2001-04-20 2004-03-03 삼성전자주식회사 코드 생성 및 배치 방법

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI395226B (zh) * 2008-11-07 2013-05-01 Silicon Motion Inc 測試儲存裝置的方法及其系統

Also Published As

Publication number Publication date
US6853319B1 (en) 2005-02-08
TWI277064B (en) 2007-03-21

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees