TW200507225A - Damascene structure and process at semiconductor substrate level - Google Patents

Damascene structure and process at semiconductor substrate level

Info

Publication number
TW200507225A
TW200507225A TW092134639A TW92134639A TW200507225A TW 200507225 A TW200507225 A TW 200507225A TW 092134639 A TW092134639 A TW 092134639A TW 92134639 A TW92134639 A TW 92134639A TW 200507225 A TW200507225 A TW 200507225A
Authority
TW
Taiwan
Prior art keywords
semiconductor substrate
damascene structure
substrate level
contact region
opening
Prior art date
Application number
TW092134639A
Other languages
English (en)
Other versions
TWI268595B (en
Inventor
Horng-Huei Tseng
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW200507225A publication Critical patent/TW200507225A/zh
Application granted granted Critical
Publication of TWI268595B publication Critical patent/TWI268595B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846Layer combinations
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76861Post-treatment or after-treatment not introducing additional chemical elements into the layer
    • H01L21/76864Thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
    • H01L23/485Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW092134639A 2003-08-14 2003-12-09 Damascene structure and process at semiconductor substrate level TWI268595B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/640,757 US7049702B2 (en) 2003-08-14 2003-08-14 Damascene structure at semiconductor substrate level

Publications (2)

Publication Number Publication Date
TW200507225A true TW200507225A (en) 2005-02-16
TWI268595B TWI268595B (en) 2006-12-11

Family

ID=34136161

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092134639A TWI268595B (en) 2003-08-14 2003-12-09 Damascene structure and process at semiconductor substrate level

Country Status (2)

Country Link
US (2) US7049702B2 (zh)
TW (1) TWI268595B (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
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CN104916687A (zh) * 2014-03-13 2015-09-16 台湾积体电路制造股份有限公司 具有无角轮廓的接触件硅化物
CN104733326B (zh) * 2013-12-24 2018-06-05 矽品精密工业股份有限公司 半导体基板及其制法

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US7026243B2 (en) * 2003-10-20 2006-04-11 Micron Technology, Inc. Methods of forming conductive material silicides by reaction of metal with silicon
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US7153769B2 (en) * 2004-04-08 2006-12-26 Micron Technology, Inc. Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon
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US8471369B1 (en) * 2004-05-17 2013-06-25 National Semiconductor Corporation Method and apparatus for reducing plasma process induced damage in integrated circuits
US7241705B2 (en) * 2004-09-01 2007-07-10 Micron Technology, Inc. Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects
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US7217660B1 (en) 2005-04-19 2007-05-15 Spansion Llc Method for manufacturing a semiconductor component that inhibits formation of wormholes
US9202758B1 (en) * 2005-04-19 2015-12-01 Globalfoundries Inc. Method for manufacturing a contact for a semiconductor component and related structure
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US7361596B2 (en) * 2005-06-28 2008-04-22 Micron Technology, Inc. Semiconductor processing methods
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CN100407419C (zh) * 2005-10-28 2008-07-30 联华电子股份有限公司 高深宽比开口及其制作方法
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CN104733326B (zh) * 2013-12-24 2018-06-05 矽品精密工业股份有限公司 半导体基板及其制法
CN104916687A (zh) * 2014-03-13 2015-09-16 台湾积体电路制造股份有限公司 具有无角轮廓的接触件硅化物
TWI622087B (zh) * 2014-03-13 2018-04-21 台灣積體電路製造股份有限公司 半導體裝置及其製造方法
US10032876B2 (en) 2014-03-13 2018-07-24 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile
US10522631B2 (en) 2014-03-13 2019-12-31 Taiwan Semiconductor Manufacturing Company, Ltd. Contact silicide having a non-angular profile

Also Published As

Publication number Publication date
US20060163735A1 (en) 2006-07-27
US20050035460A1 (en) 2005-02-17
US7413991B2 (en) 2008-08-19
TWI268595B (en) 2006-12-11
US7049702B2 (en) 2006-05-23

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