TW200507225A - Damascene structure and process at semiconductor substrate level - Google Patents
Damascene structure and process at semiconductor substrate levelInfo
- Publication number
- TW200507225A TW200507225A TW092134639A TW92134639A TW200507225A TW 200507225 A TW200507225 A TW 200507225A TW 092134639 A TW092134639 A TW 092134639A TW 92134639 A TW92134639 A TW 92134639A TW 200507225 A TW200507225 A TW 200507225A
- Authority
- TW
- Taiwan
- Prior art keywords
- semiconductor substrate
- damascene structure
- substrate level
- contact region
- opening
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 4
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 239000002184 metal Substances 0.000 abstract 3
- 230000004888 barrier function Effects 0.000 abstract 1
- 239000004020 conductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/640,757 US7049702B2 (en) | 2003-08-14 | 2003-08-14 | Damascene structure at semiconductor substrate level |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200507225A true TW200507225A (en) | 2005-02-16 |
TWI268595B TWI268595B (en) | 2006-12-11 |
Family
ID=34136161
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW092134639A TWI268595B (en) | 2003-08-14 | 2003-12-09 | Damascene structure and process at semiconductor substrate level |
Country Status (2)
Country | Link |
---|---|
US (2) | US7049702B2 (zh) |
TW (1) | TWI268595B (zh) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104916687A (zh) * | 2014-03-13 | 2015-09-16 | 台湾积体电路制造股份有限公司 | 具有无角轮廓的接触件硅化物 |
CN104733326B (zh) * | 2013-12-24 | 2018-06-05 | 矽品精密工业股份有限公司 | 半导体基板及其制法 |
Families Citing this family (57)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7384727B2 (en) * | 2003-06-26 | 2008-06-10 | Micron Technology, Inc. | Semiconductor processing patterning methods |
US20050035455A1 (en) * | 2003-08-14 | 2005-02-17 | Chenming Hu | Device with low-k dielectric in close proximity thereto and its method of fabrication |
US7026243B2 (en) * | 2003-10-20 | 2006-04-11 | Micron Technology, Inc. | Methods of forming conductive material silicides by reaction of metal with silicon |
US6969677B2 (en) * | 2003-10-20 | 2005-11-29 | Micron Technology, Inc. | Methods of forming conductive metal silicides by reaction of metal with silicon |
US7153769B2 (en) * | 2004-04-08 | 2006-12-26 | Micron Technology, Inc. | Methods of forming a reaction product and methods of forming a conductive metal silicide by reaction of metal with silicon |
KR100519801B1 (ko) * | 2004-04-26 | 2005-10-10 | 삼성전자주식회사 | 스트레스 완충 스페이서에 의해 둘러싸여진 노드 콘택플러그를 갖는 반도체소자들 및 그 제조방법들 |
US8471369B1 (en) * | 2004-05-17 | 2013-06-25 | National Semiconductor Corporation | Method and apparatus for reducing plasma process induced damage in integrated circuits |
US7241705B2 (en) * | 2004-09-01 | 2007-07-10 | Micron Technology, Inc. | Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects |
KR100654124B1 (ko) * | 2004-11-18 | 2006-12-08 | 주식회사 하이닉스반도체 | 벙커 디펙트를 억제할 수 있는 반도체 소자 제조 방법 |
US7875547B2 (en) * | 2005-01-12 | 2011-01-25 | Taiwan Semiconductor Manufacturing Co., Ltd. | Contact hole structures and contact structures and fabrication methods thereof |
US20060157776A1 (en) * | 2005-01-20 | 2006-07-20 | Cheng-Hung Chang | System and method for contact module processing |
US7217660B1 (en) | 2005-04-19 | 2007-05-15 | Spansion Llc | Method for manufacturing a semiconductor component that inhibits formation of wormholes |
US9202758B1 (en) * | 2005-04-19 | 2015-12-01 | Globalfoundries Inc. | Method for manufacturing a contact for a semiconductor component and related structure |
US7371627B1 (en) | 2005-05-13 | 2008-05-13 | Micron Technology, Inc. | Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
US7120046B1 (en) | 2005-05-13 | 2006-10-10 | Micron Technology, Inc. | Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines |
US7361596B2 (en) * | 2005-06-28 | 2008-04-22 | Micron Technology, Inc. | Semiconductor processing methods |
US7888721B2 (en) | 2005-07-06 | 2011-02-15 | Micron Technology, Inc. | Surround gate access transistors with grown ultra-thin bodies |
US7768051B2 (en) | 2005-07-25 | 2010-08-03 | Micron Technology, Inc. | DRAM including a vertical surround gate transistor |
US7696567B2 (en) | 2005-08-31 | 2010-04-13 | Micron Technology, Inc | Semiconductor memory device |
US20070049006A1 (en) * | 2005-08-31 | 2007-03-01 | Gregory Spencer | Method for integration of a low-k pre-metal dielectric |
US7416943B2 (en) | 2005-09-01 | 2008-08-26 | Micron Technology, Inc. | Peripheral gate stacks and recessed array gates |
US7557032B2 (en) | 2005-09-01 | 2009-07-07 | Micron Technology, Inc. | Silicided recessed silicon |
US7687342B2 (en) | 2005-09-01 | 2010-03-30 | Micron Technology, Inc. | Method of manufacturing a memory device |
CN100407419C (zh) * | 2005-10-28 | 2008-07-30 | 联华电子股份有限公司 | 高深宽比开口及其制作方法 |
DE102005052001B4 (de) * | 2005-10-31 | 2015-04-30 | Advanced Micro Devices, Inc. | Halbleiterbauelement mit einem Kontaktpfropfen auf Kupferbasis und ein Verfahren zur Herstellung desselben |
JP2007281114A (ja) * | 2006-04-05 | 2007-10-25 | Sony Corp | 半導体装置の製造方法および半導体装置 |
US20070238280A1 (en) * | 2006-04-10 | 2007-10-11 | Hynix Semiconductor Inc. | Semiconductor device having contact plug and method for fabricating the same |
US7670946B2 (en) * | 2006-05-15 | 2010-03-02 | Chartered Semiconductor Manufacturing, Ltd. | Methods to eliminate contact plug sidewall slit |
JP2008117853A (ja) * | 2006-11-01 | 2008-05-22 | Toshiba Corp | 半導体装置およびその製造方法 |
US7923840B2 (en) * | 2007-01-10 | 2011-04-12 | International Business Machines Corporation | Electrically conductive path forming below barrier oxide layer and integrated circuit |
DE102007004884A1 (de) * | 2007-01-31 | 2008-08-14 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung einer Metallschicht über einem strukturierten Dielektrikum durch stromlose Abscheidung unter Anwendung einer selektiv vorgesehenen Aktivierungsschicht |
US7777344B2 (en) * | 2007-04-11 | 2010-08-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Transitional interface between metal and dielectric in interconnect structures |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US20090004851A1 (en) * | 2007-06-29 | 2009-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicidation process using electroless plating to deposit metal and introduce dopant impurities |
EP2162906B1 (en) * | 2007-06-29 | 2013-10-02 | Imec | A method for producing a copper contact |
KR101069432B1 (ko) * | 2007-10-26 | 2011-09-30 | 주식회사 하이닉스반도체 | 반도체소자의 콘택 형성방법 |
US8354347B2 (en) * | 2007-12-11 | 2013-01-15 | Globalfoundries Singapore Pte. Ltd. | Method of forming high-k dielectric stop layer for contact hole opening |
US7863176B2 (en) * | 2008-05-13 | 2011-01-04 | Micron Technology, Inc. | Low-resistance interconnects and methods of making same |
DE102009006881B4 (de) * | 2009-01-30 | 2011-09-01 | GLOBALFOUNDRIES Dresden Module One Ltd. Liability Company & Co. KG | Verfahren zur Hohlraumversiegelung in einem dielektrischen Material einer Kontaktebene eines Halbleiterbauelements, das dicht liegende Transistoren aufweist und Halbleiterbauelement mit derselben |
US8211325B2 (en) * | 2009-05-07 | 2012-07-03 | Applied Materials, Inc. | Process sequence to achieve global planarity using a combination of fixed abrasive and high selectivity slurry for pre-metal dielectric CMP applications |
US8164190B2 (en) * | 2009-06-25 | 2012-04-24 | International Business Machines Corporation | Structure of power grid for semiconductor devices and method of making the same |
US8610275B2 (en) * | 2010-07-14 | 2013-12-17 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor contact structure including a spacer formed within a via and method of manufacturing the same |
WO2013095433A1 (en) * | 2011-12-21 | 2013-06-27 | Intel Corporation | Electroless filled conductive structures |
US20140008799A1 (en) * | 2012-07-04 | 2014-01-09 | National Applied Research Laboratories | Method for fabricating metal line and device with metal line |
US9111939B2 (en) | 2012-07-27 | 2015-08-18 | Intel Corporation | Metallization of fluorocarbon-based dielectric for interconnects |
US9099439B2 (en) * | 2013-11-14 | 2015-08-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor device with silicide cap |
US9129842B2 (en) * | 2014-01-17 | 2015-09-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Formation of silicide contacts in semiconductor devices |
JP6373150B2 (ja) * | 2014-06-16 | 2018-08-15 | 東京エレクトロン株式会社 | 基板処理システム及び基板処理方法 |
TWI566365B (zh) * | 2014-07-07 | 2017-01-11 | 旺宏電子股份有限公司 | 接觸結構及形成方法以及應用其之回路 |
CN104269378A (zh) * | 2014-09-24 | 2015-01-07 | 上海华力微电子有限公司 | 源极局域互连结构的形成方法 |
US9589836B1 (en) * | 2016-03-11 | 2017-03-07 | Globalfoundries Inc. | Methods of forming ruthenium conductive structures in a metallization layer |
US10366982B2 (en) * | 2017-11-30 | 2019-07-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Structure with embedded memory device and contact isolation scheme |
CN109686657B (zh) * | 2018-11-29 | 2021-04-13 | 长江存储科技有限责任公司 | 晶圆间键合结构的形成方法、晶圆的键合方法 |
CN111261709B (zh) * | 2018-11-30 | 2024-08-30 | 长鑫存储技术有限公司 | 导电插塞结构、半导体器件及其形成方法 |
US11158537B2 (en) | 2020-01-23 | 2021-10-26 | International Business Machines Corporation | Top vias with subtractive line formation |
US11171084B2 (en) | 2020-04-06 | 2021-11-09 | International Business Machines Corporation | Top via with next level line selective growth |
US11515256B2 (en) * | 2021-01-27 | 2022-11-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor structure and manufacturing method thereof |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5884323A (en) * | 1995-10-13 | 1999-03-16 | 3Com Corporation | Extendible method and apparatus for synchronizing files on two different computer systems |
US5856226A (en) * | 1997-12-19 | 1999-01-05 | Texas Instruments-Acer Incorporated | Method of making ultra-short channel MOSFET with self-aligned silicided contact and extended S/D junction |
TW412792B (en) * | 1999-02-10 | 2000-11-21 | Applied Materials Inc | Etching back process for solving the plug loss |
US6211085B1 (en) * | 1999-02-18 | 2001-04-03 | Taiwan Semiconductor Company | Method of preparing CU interconnect lines |
TW541651B (en) | 2002-06-04 | 2003-07-11 | Nat Science Council | Copper interconnect damascene fabrication process of semiconductor device |
-
2003
- 2003-08-14 US US10/640,757 patent/US7049702B2/en not_active Expired - Lifetime
- 2003-12-09 TW TW092134639A patent/TWI268595B/zh not_active IP Right Cessation
-
2006
- 2006-02-17 US US11/357,697 patent/US7413991B2/en not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104733326B (zh) * | 2013-12-24 | 2018-06-05 | 矽品精密工业股份有限公司 | 半导体基板及其制法 |
CN104916687A (zh) * | 2014-03-13 | 2015-09-16 | 台湾积体电路制造股份有限公司 | 具有无角轮廓的接触件硅化物 |
TWI622087B (zh) * | 2014-03-13 | 2018-04-21 | 台灣積體電路製造股份有限公司 | 半導體裝置及其製造方法 |
US10032876B2 (en) | 2014-03-13 | 2018-07-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact silicide having a non-angular profile |
US10522631B2 (en) | 2014-03-13 | 2019-12-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact silicide having a non-angular profile |
Also Published As
Publication number | Publication date |
---|---|
US20060163735A1 (en) | 2006-07-27 |
US20050035460A1 (en) | 2005-02-17 |
US7413991B2 (en) | 2008-08-19 |
TWI268595B (en) | 2006-12-11 |
US7049702B2 (en) | 2006-05-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI268595B (en) | Damascene structure and process at semiconductor substrate level | |
FR2901406B1 (fr) | Processus d'amelioration de la formation d'un couvercle de ligne en cuivre | |
TW200511493A (en) | Method for forming a dielectric barrier in an integrated circuit structure, interconnect structure and semiconductor device and methods for making the same | |
GB2391388A (en) | Electronic structure | |
TW200608604A (en) | Metal gate structure for MOS devices | |
TW200636917A (en) | Interconnect structure and method of fabrication of same | |
MY195186A (en) | Nitride Structures Having Low Capacitance Gate Contacts Integrated with Copper Damascene Structures | |
TW200614518A (en) | Semiconductor device and method of manufacturing the same | |
TW200620544A (en) | A damascene interconnect structure with cap layer | |
EP1102315A3 (en) | A method to avoid copper contamination on the sidewall of a via or a dual damascene structure | |
TWI256677B (en) | Barrier material and process for Cu interconnect | |
TW200505033A (en) | Capacitor and method of fabricating the same | |
TW200518338A (en) | Semiconductor device and making thereof | |
TW200627629A (en) | Semiconductor device having ferroelectric capacitor and its manufacture method | |
TW200603331A (en) | Method of manufacturing a semiconductor device | |
TW200723448A (en) | Interconnect structure and fabrication method thereof and semiconductor device | |
TW200711038A (en) | Method of forming a semiconductor device having a diffusion barrier stack and structure thereof | |
SG128555A1 (en) | Integrated circuit system using dual damascene process | |
TW200620545A (en) | Robust copper interconnection structire and fabrication method thereof | |
ATE532212T1 (de) | Bordotierte titannitridschicht für halbleiter mit grossem aspektverhältnis | |
TW200518265A (en) | Copper damascene structure and semiconductor device including the structure and method of fabricating the same | |
TW200709337A (en) | Semiconductor devices and methods for forming the same | |
TW200735313A (en) | Semiconductor device and manufacturing method thereof | |
TW200514195A (en) | Copper wiring with high temperature superconductor(HTS) layer | |
TW200512869A (en) | Tungsten-copper interconnect and method for fabricating the same |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK4A | Expiration of patent term of an invention patent |