TW541651B - Copper interconnect damascene fabrication process of semiconductor device - Google Patents

Abstract

This invention discloses a copper interconnect damascene fabrication process. Through a selective chemical deposition method, a metal barrier layer is used to cover on copper interconnect after planarization. Therefore, electromigration resistance of the copper interconnect can be effectively improved, the influence of dishing recess on the degree of planarization can be reduced and leakage current at the interface between interconnect layers can be reduced. In addition, a dielectric layer with a low dielectric constant is used as a cap layer of the copper interconnect to further reduce the total effective dielectric constant of the copper interconnect system.

Description

541651 A7 B7 V. Description of the Invention (1) The invention relates to the damascene process of a semiconductor device, especially the copper wire damascene process using a low dielectric constant material as the dielectric layer. As the degree of accumulation increases, the distance between the metal wires of the semiconductor element is getting closer and closer. Due to the effect of the resistance value of the wire and the capacitance value formed by the dielectric between adjacent wires (RC delay), signal transmission The time delay is the main reason for the limited speed of the device. In addition, in order to increase the parasitic resistance and capacitance caused by the trend of narrowing line width on the process, copper (Cu) metal wires and low dielectric constant Intermetal Didectric (IMD) has been continuously developed and applied to deep sub-micron component manufacturing technology. Because copper metal wires are not easy to be etched by gas plasma (dry type), the production of copper metal wires Most of them use Cu damascene process, as shown in Fig. 1 (a) to Fig. 1 (d). Referring to Fig. 丨, the first inter-conductor layer of a semiconductor device is etched. ι〇4 and an etch stop layer 106 to form a via 110 and trenches 112 and 114 which can be connected to a metal wire layer 108. The trenches ι and ι4 are used as metal lines. ) Part is equivalent to the metal wire layer 108, but it belongs to different layers. Referring to FIG. 1 (b), a metal barrier layer 116 and a copper metal layer 118 are sequentially deposited. The metal barrier layer ιΐ6 is usually nitrogen. The composition of tantalum (TaN) is used to prevent the diffusion of steel atoms in the copper metal layer 118. Referring to FIG. 1 (c), planarization using chemical mechanical polishing (CMP) technology will be higher In the H: \ Hu \ tys \ NDL said \ 77788 \ 77788 amended doc -4- 541651 A7 _____B7 V. Description of the invention (2) The copper metal layer 1 1 8 of the conductor layer 1 0 4 and the metal barrier Layer 1 1 6 is removed. Referring to FIG. 1 (d), a silicon nitride (called capping) capping layer 12 is finally deposited on the copper metal layer 8 and the wire interlayer 104. In order to prevent the diffusion and oxidation of copper atoms in the copper metal layer 1 1 8. The dual damascene process is used to replace the current aluminum-copper metal. The line process belongs to the back-end of line (BEOL) process of wafer manufacturing. Even after it is used to complete the contact plug with silicon bottom layer (contactplug), and depending on the number of metal wire layers of the component design, it may require It is repeated many times. However, some problems are often encountered in the process of the conventional mosaic structure. First, when the CMP process is used to remove the excess copper metal layer 118, since the selected I slurry is mainly used to polish the copper metal layer 1 1 8, it is not suitable for the metal barrier layer i 丨The polishing rate of 6 is relatively slow, so that in regions with a large pattern area, such as the copper wire layer 118 filled in the trenches 1 12, 114, dishing 122, 124 phenomena often occur. Causes poor surface flatness. In addition, during the CMP process of removing the metal barrier layer 116, the surface of the wire interlayer 104 is easily damaged, and a serious interface leakage current phenomenon is generated. In addition, since the silicon nitride capping layer 12 () has a relatively low dielectric constant (about 7.9), the effective dielectric constant value of the overall damascene structure will be increased. In addition, the activation energy due to the migration of copper atoms on the Cu / si3N4 interface is lower than the activation energy.

The reaction activation energy on the Cu / TaN interface and its ability to resist electron migration are poor, which makes the silicon nitride cap layer 120 limited in the application of the copper wire process.

H: \ Hu \ tys \ NDL says \ 77788 \ 77788 fix doc ^ C

541651 A7-B7 V. Description of the invention (3) — ---- 1 Brief description The purpose of the present invention is to provide a high-reliability copper wire inlay process, which can effectively enhance the ability of the copper wire to resist electron migration, Reduce the influence of dish-shaped depressions on flatness and reduce the leakage current at the interface between wires. In addition, the use of a dielectric layer having a low dielectric constant as the capping layer of the copper wire can further reduce the overall effective dielectric constant of the copper wire system. The copper wire damascene process of the semiconductor element of the present invention includes the following steps: (a) forming at least one double damascene structure on a semiconductor substrate, which includes at least one dielectric layer and at least one metal wire layer as a wire interlayer, The salt dielectric layer includes a trench and a via hole as a wire channel; (b) depositing a first metal barrier layer on the dielectric layer and the metal wire layer to prevent copper metal from diffusing; (c) covering a A copper metal layer on the first metal barrier layer; (d) planarizing the surface by chemical mechanical polishing technology until the dielectric layer is exposed, and (e) forming a second metal barrier layer on the surface of the copper metal layer And a nitride layer on the surface of the dielectric layer; and (f) covering a dielectric cap layer. The upper metal barrier layer may be a tungsten nitride layer. The tungsten nitride layer and the nitride layer may be formed by first reacting only WF0 and SiH4 gas on the surface of the copper metal layer to form tungsten. Metal layer. Nitrogen (M2) or ammonia (NH3) plasma is used to perform the nitriding reaction, so that the tungsten metal layer becomes the nitrided crane layer, and a nitride layer is formed on the surface of the dielectric layer. The tungsten nitride layer can also be formed by directly reacting WF6, S1H4 and A or WF6, Si% and NH3. Because WF6 gas is not easy to react with insulating materials such as dielectrics, it can deposit tungsten metal on the surface of metal materials. The present invention selectively uses this characteristic of different growth latency on different materials to selectively deposit H: \ Hu \ tys \ NDL said \ 77788 \ 77788 modified doc -6- 541651 A7

On the copper metal layer after the tungsten nitride material is planarized, not only the problem that the dielectric constant of hafnium nitride is lower than that of nitrogen, but also the phenomenon of less electron migration. The simple tn of the extinguishable pattern The present invention will be described with reference to the following drawings, in which: Figure 1 (a) Figure 1 (d) is a conventional copper wire inlaying process; and Figures 2 (a) to 2 ( e) It is the copper wire inlaying process of the present invention. Symbol description of element_10 semiconductor element 102, 104 inter-wire layer 106 etch stop layer 108 metal wire layer 1 10 via hole 112, 114 trench 116 metal barrier layer 118 copper metal layer 120 silicon nitride cap layer 122, 124 dish 20 depressions 20 semiconductor elements 202, 204 dielectric layer 206 etch stop layer 208 metal wire layer 210 vias 212, 214 trenches 216 TaN metal barrier layer 218 copper metal layer 220, 222 dish-like depression 224 tungsten nitride layer 226 nitrogen Description of the preferred embodiment of the metallization layer 228 dielectric capping layer Figures 2 (a) to 2 (e) show the copper of the semiconductor device of the present invention

Binding

Production steps of the line process. Referring to FIG. 2 (a), a semiconductor device 20 is first etched with a dielectric layer 2 0, 2 0 4 as a wire interlayer, and a etch stop layer 2 0. HAHu \ tys \ NDL says \ 77788V77788 modified doc-" This paper size applies Chinese National Standard (CNS) A4 specification (210 X 297 mm) 541651 A7 B7 V. Description of the invention (5) to form a via hole that can be connected to a metal wire layer 208 ( via) 2 10 and trenches 212 and 214. The dielectric layers 202 and 204 are composed of a Silicate-based film with a low dielectric constant, such as: FSG (Fluorosilicate Glass), HSQ (Hydrogen silsesquioxane), MSQ (Methylsilsesquioxane), HOSP (Hybrid-Organic_Siloxane_ Polymer), and SiOC. Referring to FIG. 2 (b), a TaN metal barrier layer 2 16 and a copper metal layer 2 1 8 are sequentially deposited on the via hole 2 10 and the trench 2 1 2 and 2 1 4 in this order. Referring to FIG. 2 (c), a chemical mechanical polishing (CMP) technique is used for planarization to remove the copper metal layer 218 and the TaN metal barrier layer 216 that are higher than the dielectric layer 204. CMP has different polishing rates for the copper metal layer 2 18 and the TaN metal barrier layer 216, and dish-shaped depressions 220 and 222 are generated at the trenches 212 and 214. 2 (d), a tungsten nitride (WNX) layer 22 4 is selectively deposited on the copper metal layer 21 8 after CMP, and a surface of the dielectric layer 204 is nitrided to form a nitride layer 226. Since FSG is made of silicon monoxide, the nitride layer 22 6 is composed of silicon oxynitride (Si0N). In this step, not only can the dish-shaped depressions 2 2 0, 2 2 2 be reduced in depth, but also because the Cu / WN x interface has higher reaction activation than the conventional cu / s 丨 3 N 4 interface Yes, it can improve the ability to resist electron migration. Referring to FIG. 2 (e) ', a dielectric coating layer 2 2 8' is covered with a spin coating method to complete the fabrication of the structure after copper inlaying. The dielectric cap layer H: \ Hu \ tys \ NDL says \ 77788 \ 77788 modified doc-g _

541651 A7 B7 Fifth invention description (6 ~~) '228 can be composed of silicate film with low dielectric constant or silicon carbide (SiC) with a dielectric constant of 5 to replace the traditionally used dielectric constant of 8 Si3N4. The above-mentioned selective tungsten nitride layer 2 2 4 can be formed in a metal tungsten chemical vapor deposition machine (W-CVD) using the following two methods: (1) using a mixed gas of WF 6 and Si i 4 as a precursor (Precursor *), (the mixing ratio is WF6 · SiH4 = 40 ~ 100 seem: 60 ~ 150 seem, seem is a flow unit, ie cc / min), and the chemical reaction is performed at 300 ° C ~ 400 ° C ' A tungsten metal layer (not shown) is selectively formed on the surface of the copper metal layer 2 1 8 according to the following reaction formula (a): 2WF6 + 3SiH4 ^ 2 W + 3SiF4 + 6Η2 · · · (a) In the chemical vapor deposition reaction, S i Η 4 gas is first introduced into the reaction chamber (chamber) for about 1 to 3 minutes, and as a purging action, the WF6 gas is introduced. This prevents the surface of the copper metal layer 218 from being oxidized. The chemical deposition reaction is selective, and the tungsten metal layer will only be formed on the surface of the copper metal layer 218, but not on the dielectric layer 204. Next, a plasma of nitrogen (A) is performed on the tungsten metal layer. Or the treatment of ammonia gas (NH3) plasma to form the tungsten nitride layer 224. At the same time of the plasma processing step, the surface of the dielectric layer 204 will also be nitrided to form a nitride layer 22 6 'which can repair the dielectric layer H: \ Hu when it was previously polished by the CMP process. \ tys \ NDL says \ 77788 \ 77788 revised doc-9 _ This paper size applies to China National Standard (CNS) A4 (210X297 mm) I. Binding

Line 541651 A7 B7 V. Description of the invention (7) The damage caused by 204 is effective to reduce the leakage current at the interface of the dielectric layer 204. (2) Using a mixed gas of WF6, SiH4, and N2 (or NH3) (the ratio is WF6: SiH4: N2 = 40 ~ 100 seem: 60 ~ 150 seem: 20 ~ 50 seem), according to the following reaction formula (b) A chemical reaction is performed at 300 ° C. to 400 ° C. to form the tungsten nitride layer 2 2 4 and the nitride layer 2 2 6. 2WF6 + 3SiH4 + N2 ^ 2WN + 3SiF4 + 6H2 ··· 〇)) As in the first method described above, when carrying out this chemical vapor deposition reaction, S i 先 4 gas is first introduced into the reaction chamber for about 1 ~ 3 Minutes, after which WF6 gas and Ν24ΝΗ3 gas were introduced. The technical content and technical features of the present invention are disclosed as above. However, those skilled in the art may still make various substitutions and modifications based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various substitutions and modifications that do not depart from the present invention, and are covered by the following patent application scope. -10- H: \ Hu \ tys \ NDL says \ 77788 \ 77788 amended doc This paper size applies to China National Standard (CNS) A4 (210 X 297 mm)

Claims (1)

541651 Patent Application Scope—A copper wire inlay process for a semiconductor device, including the following materials, personnel, and semiconductors: at least one dielectric layer, a silicon layer, a spring layer, and a dielectric layer are formed on a semiconductor substrate. Including at least one trench and at least / dielectric / co-depositing a first metal barrier layer on the dielectric layer and the metal covering a copper metal layer on the first metal barrier layer; performing surface planarization to expose the dielectric So far; forming a second metal barrier layer on the copper metal layer and forming a mouse layer on the dielectric layer; and covering a dielectric cap layer. Interlayer Wire layer; Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 2. For the copper wire inlay process of the first patent application, the metal barrier layer is composed of tungsten nitride. 3. The copper wire inlaying process as described in item 2 of the patent application, where the layer is first formed by reacting WF6 and Sih gas to form a tungsten metal and reacting by nitrogen plasma. 4. For the copper wire inlaying process according to item 2 of the scope of patent application, the crane layer is first formed by the reaction of WFe and SiH4 gas to form a tungsten metal and the plasma reaction of ammonia gas. 5. The copper wire inlaying process as described in claim 2 of the patent scope. The plutonium layer is formed by the reaction of WF0, SiH4 and plutonium gas. 6 · If the copper wire inlaid process crane layer in item 2 of the patent application scope is formed by using WF0, SiH4 and NH3 gas reaction 7 · In the copper wire inlaid process layer and dielectric cap layer of the patent application 1 Material composition of low dielectric constant. 8 · If the copper wire inlaying process of item 1 of the scope of the application for patents, where H AHu \ tyS \ NDL says \ 77788 \ 77788 amended doc-11-This paper is a national standard specification of 公 公 297. Nitride layer, then the nitride layer, and then the nitride, the nitride, the nitride, the dielectric, and the dielectric I — 9 -----— order --------- C Please first (Read the back of the page, please note this page, fill in this page) 541651 A8 B8 C8 D8 Patent Application Scope ----- The Intellectual Property Bureau of the Ministry of Economic Affairs, the employee consumer cooperative printed layer is composed of silicate materials with low dielectric constant 9 · If the copper wire inlay process of item 1 of the scope of patent application, the capping layer is composed of carbonized carbide. 1 10. If the copper wire inlay process of item 1 of the scope of patent application, the metal barrier layer is made of nitride妲 Composition. 1 1. If the copper wire inlay process of item 1 in the scope of the patent application, the layer is composed of silicon oxynitride. 1 2 · If the copper wire inlay process of area 1 in the patent application, learn mechanical polishing technology to flatten 1 3 · If the copper wire inlaying process of item 3 of the patent application scope, the tungsten metal layer First, SiH4 gas is passed in for 1-3 minutes. 14. For the copper wire inlaying process of item 3 of the scope of patent application, the wF6 and SiH4 gas flow f is between 40-100 sccm and 60- 150 seem, and the reaction is carried out at 300-400 ° C. 1 5. According to the copper wire inlaying process of item 5 of the patent application, wherein the gas flow of the WF6, SiH4 and N2 is between 4 〇 1 〇〇sccm , 60-150sccm and 20-50sccm, and the reaction is carried out at 300-400 °. 16. If the copper wire inlaying process of the scope of application for item 丨, wherein the dielectric layer is composed of FSG. 1 7. If applied The copper wire damascene process of item 1 of the patent scope, wherein the dielectric layer is composed of HSQ. 1 8 · If the copper wire damascene process of item 丨 of the patent scope, the dielectric layer is composed of MSQ. Electricity where the first where the nitride is used in the formation (Please read the precautions of C & * before filling out this page) ▼ Install -------- Order --------- *: 5 ^^ 丨 541651 A8 B8 C8 D8 VI.Application Patent scope 19: The copper wire inlaying process of item 1 of the patent scope, wherein the dielectric layer is composed of Η 0 SP. 20. The copper wire inlaying process according to item 1 of the scope of the patent application, wherein the dielectric layer is composed of S i 0 C. (Please read the note of “Fer®” before filling out this page) Printed by H: \ Hu \ tys \ NDL in the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs \ 77788 \ 77788 amended doc CNS) A4 size (210 X 297 mm)