TW200428640A - Structure of integrated circuit with built-in inductor, and using P-N junction to block the parasitic current - Google Patents

Abstract

A device structure in the integrated circuit, it uses the built-in inductor to block the parasitic current and forms the shallow trench isolation as the grid structure in the sidewall, and forms P-N junction device. By using this P-N junction region, it can block the parasitic lost current generated in the substrate. There are active device regions, equipped with multiple active devices. P-N junction region is formed with ion implantation by using different types of dopants.

Description

200428640

[Technical field to which the invention belongs] The present invention belongs to the field of semiconductor technology, and particularly relates to a structure of a built-in inductor of an integrated circuit and a structure for blocking a parasitic current by using a P-N junction element. This description uses the shallow trench isolation of the grid structure to form a p_N junction element to block the loss of parasitic current. The invention can effectively improve the quality factor, avoid electromagnetic induction 'and improve the reliability of the component. [Prior technology] It is arranged directly above the field oxide layer, and electromagnetic induction causes electrical loss along the silicon substrate. The high-frequency quality factor

In the conventional integrated circuit, the inductance element is formed of aluminum or copper. The number of parasitic currents in the inductive element decreases due to the parasitic current in the axial direction of the inductive coil. The method of common -5 == 2 inductor can be found in the Republic of China Patent 2. 51 621 3 said (Announcement of January 1, 2003) that this case formed at least two inductors extending in the direction of the interconnect base of different metallization planes. The structure of this case is complicated, and the manufacturing process is difficult.] The high-f connection forms a spiral: making a multilayer inductor structure with high inductance and high quality factor (: two hlgh Q) can be found in γ factor ’(20G2 phase rib date announcement). This profit announcement 511274 uses multi-layer integrated circuit technology, and the spiral wire recognition radio frequency circuit is connected by a via window plug. The coil material is #: away :: between, and each coil is tungsten or aluminum. This case is a three-dimensional junction. Structure: ’Plug material Manufacture of inductive elements in integrated circuits ^^ The process is difficult.

200428640 V. Description of the Invention (2) Notice 44 1 0 86 (Announcement on June 16, 2001). This case uses a masking device to isolate the active area of the semiconductor element from the electromagnetic field generated by the inductance. The masking device contains a low-resistance flat plate perpendicular to the inductive element. This case can be used to receive radio signals. The device in this case uses multiple layers of metal to make the process complicated and difficult.

Fig. 1 is a schematic cross-sectional view of a conventional silicon wafer with a built-in inductance element. First, a silicon substrate 100 is divided into an active device region 101 and an isolation region 103. Forming a field oxide layer 10, a gate oxide layer 104, a first polycrystalline silicon gate layer 106, gate spacers 108, and a shallowly doped drain electrode (1 ight 1 y doped drai n (LDD) source / drain region 1 1 0, forming the required metal-oxide half field effect transistor structure, the gate and source of this transistor are plugged with 11 8 or 12 0 and the upper layer, respectively connection. Next, a dielectric layer ι14 is formed, and the inductive element n 6 is disposed above the dielectric layer directly above the field region oxide layer 102 of the silicon substrate 100 in a built-in manner. The coil material of this built-in inductance element can be metal or metal. The coil pattern can be formed by metal deposition or sputtering, and then formed by photoresist development and dry etching. If the coil material is copper metal, the dielectric layer 11 4 can be planarized by chemical mechanical polishing (CMp), and then the copper metal layer is sputtered on the surface of the dielectric layer, and a photoresist is applied, and then exposed by the photoresist. , Development, dry etching to form a copper coil pattern. The inductive element 1 1 6 includes a plurality of layers of inductor coils 1 1 6 a, a plurality of layers of inductor coils 11 6 a are electrically insulated by a dielectric layer 11 6 b, and a plurality of layers of inductor coils 11 6 a are connected by plugs 11 6 c are electrically connected to each other. The built-in power reduction element 1 1 6 will cause parasitic current to flow in the silicon substrate 1 00 along the axis of the inductor owing to electromagnetic induction, thus affecting the inductance element i 6 at high frequency 200428640. 2. Description of the invention (3) The performance under operation will have a decrease in quality factor (Q value). In view of this, the inventors have reduced the loss of parasitic currents and avoided the influence of electromagnetic induction. . [Summary of the Invention] The object of the present invention is to provide a structure with built-in inductors in integrated circuits and a structure that blocks parasitic currents by using PN junction elements, which can prevent the parasitic loss current of the inductive elements to improve the electrical performance and reliability of the elements . The invention relates to a built-in inductance element and a structure for blocking parasitic current by using a p-N junction element.

A structure of a built-in inductor of an integrated circuit and a parasitic current blocking structure using a p-N junction element according to the present invention includes an element structure including a built-in inductor element and a parasitic loss current generated by blocking the inductor element, and includes: a semiconductor substrate The substrate has an active device region, and a chemical vapor deposition oxide layer p_N bonded to a side surface of the active device region, such as a shallow trench isolation region with a grid structure, joins all parts, and the chemical vapor phase of the grid structure The deposited oxide p_N junction element is doped by a plurality of chemical vapor deposition oxide layers disposed on the substrate, a plurality of first conductivity type ions disposed below the deposited oxide layer, and a plurality of electrodes disposed on the substrate. The second = electric type ion doped region between the chemical vapor deposition oxide layers, the p ~ N junction region generated between the first conductive type ion doped region and the second conductive type ion doped region, Can resist parasitic loss current generated by inductive elements; a plurality of active elements are arranged in

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V. Description of the invention (4) Active element area; a dielectric layer is disposed on the active element and the chemical gas deposition oxide layer P-N junction element, and is used for covering the insulating element A plurality of inductive elements are disposed above the chemical vapor deposition oxide layer element, and the dielectric layer is used as an isolation insulating layer in between. The port includes a built-in inductive element and blocks the inductive element. The chemical vapor deposition oxide layer p-N junction element that generates parasitic pumping current, wherein when the first and second conductive type doped regions are P-type doped, the second conductive type doped ^ type doped.

The port includes a built-in inductance element and a gate-shaped P-N junction region element that blocks parasitic loss current generated by the inductance element. When the first conductivity type doped region is N-type doped, the second conductivity type is doped. The region is p-type doped. The semiconductor substrate is a silicon substrate. The doped region of the first conductivity type and the doped region of the second conductivity type are implanted in the ions of the first conductivity type and the ions of the second conductivity type from 65 ° C to 120 °. C is formed by an annealing step. The coil material of the built-in inductive element can be aluminum or copper. [Embodiment] Fig. 21 according to the present invention—the preferred example has a mouth of a built-in inductive element wafer. It is proposed to form a plurality of parallel M junctions by doping type,-the silica bottom 20 is located under the inductor, and has a current blocking effect. 200428640 V. Description of the invention (5) ef feet) , Can effectively block the parasitic loss current in the substrate. A shallowly doped drain-type metal-oxide-semiconductor field-effect transistor LDDFET structure 2 1 2 and a plurality of plugs 2 1 8 and 2 2 0 are formed on a silicon substrate.

First, in order to simply use a silicon substrate in this embodiment, those skilled in the art can obviously use other semiconductor substrates to form an active device region 001 on a semiconductor substrate 2000 (a silicon substrate 2000 in this embodiment). And an isolation region 2 0 3, this isolation region has a plurality of mutually parallel gas-phase precipitation-based oxide layers 206 ′ formed by a shallow trench isolation (STI shal low Trench I sol at ion) process. This emulsified layer 20 6 is composed of The shallow trench isolation chemical vapor deposition oxide layer is then planarized and formed. A silicon nitride layer is used as a mask (Mask, not shown in the figure) 'to form a gas phase > an oxide layer 2 0 6 on a portion of the substrate 200 below the isolation region 2 03 to form a chemical gas Prior to the phase deposition of the oxide layer, an ion implantation step is performed to form a doped region 208, and then a shallow trench isolation (STI) process is used for the vapor deposition step to generate a shallow trench insulation oxide layer 206.

Referring also to FIG. 2, after the silicon nitride layer is removed, a vapor deposition oxide layer 20 6 on the substrate 2000 is used as a mask; another different type of ion implantation 210 is performed, and then a 65 (TC ~ 120 (rc annealing (ann ^ HngM

Management. The ions are driven into the substrate 200. The ion-doped region 2 0 between the gas-phase oxide layer 2 0 8 and the meteorological oxide layer 2 6 must be different types of ions to produce a P-N junction. Office. Referring also to FIG. 2, an insulating dielectric layer 2 1 4 is formed on the substrate 200 above the transistor 21 2 and the gate-like p-N junction, and the dielectric layer 2 1 4 is a flattened dioxide. (S i 〇2) or other materials with low dielectric constant (丨 〇w κ)

200428640 V. Description of the invention (6) quality, mainly used for insulating and isolating the active component area 201 and isolation area 203 below and including the inductive passive component 216 above. Referring also to FIG. 2, the inductive element 216 is located above the gate-shaped parallel chemical vapor deposition oxide layer 206 of the substrate 200 with an insulating dielectric layer 2 1 4 for electrical isolation therebetween. The inductive element 2 1 6 includes a plurality of layers of inductance coils 216a surrounding a coil structure, and a plurality of layers of the inductance coils 216a are electrically insulated by a dielectric layer 2 1 6b, and each layer of the inductance coils 21 6a is connected to each other and is dug by The contact window plug 216c on the dielectric layer. The electromagnetic induction generated by the inductive element 216 will generate a parasitic loss current on the substrate 200 at the same time. In the present invention, a parallel chemical gas is deposited in the substrate 200 directly below the inductive element 216 to deposit an oxide layer 20 6 which can partially block the parasitic loss of electricity in the substrate 200 and prevent k from forming a quality factor q of the inductive element 216. The value decreases, which improves the performance of the inductive element under high frequency operation. Fig. 3 is a preferred embodiment of the present invention, which has a built-in inductor element and is not intended to be viewed from above. Among them, the chemical layer 206 located below the inductive element 216, and the ion-doped region _ below the oxide layer, the gate-type ion-doped region 21G constitutes the mutual flat-sensing element 2Π due to electromagnetic induction. ; Effectively block the parasitic loss current generated in the X direction due to the fact that iron has been connected. 1 dye 0 / ,, does not explain and explain the unique and unique features of the present invention and # Lian 浐 corrective to those who are familiar with this technology + men's and body yoke examples, the invention is not limited to the specific features of the schema 'Improvements' must be understood that the scope of benefits will cover all $ & ^ f formulas, and in the additional application, all modifications that do not fall within the spirit and scope of the present invention. Page 10 200428640 Brief Description of Drawings Figure 1 A schematic cross-sectional view of a conventional silicon wafer with a built-in inductance element. Figure 2 is a schematic cross-sectional view of a preferred embodiment of the present invention with a built-in inductor chip. FIG. 3 is a plan view of a chip with a built-in inductor element according to a preferred embodiment of the present invention. Description of component symbols: 100, 200 substrates 101, 201 active device regions 103, 203 isolation regions 102 field gasification layers 104 gate oxide layers 106 polycrystalline silicon gate layers 108 gate sidewall 110 LDD source / Drain region 118, 120, 218, 220 Plug 114 Dielectric layer 116, 216 Inductive element 116a, 216a Inductive coil 116b, 216b Dielectric layer 116c Plug 206 Oxidation layer 20 8, 210 Ion implantation doped region 212 LDD type Transistor

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Claims (1)

200428640 VI. Scope of patent application-Built-in inductor of integrated circuit and use of P_N element to block parasitic electrical structure ’& δ has built-in inductor element and block the inductor 2. The element structure of current loss includes at least: a semiconductor parasitic substrate; a semiconductor substrate with an active element region on the substrate, and a chemical vapor deposition oxide layer that actively forms a shallow trench isolation region such as a gate structure. The chemical vapor deposition oxide layer ρ_N of the grid structure described above is composed of a plurality of chemical vapor deposition oxidation sounds σ arranged on the substrate, and a plurality of first Conductive-type ions and a plurality of second-type ion-doped regions disposed between the chemical vapor deposition oxide layer, the first-conductive-type ion-doped regions and the second-type ion-doped regions The junction area generated between them can block the parasitic loss current generated by the element; a plurality of active elements are arranged in the active element region; a dielectric layer is arranged in the active element and the chemical vapor deposition oxide layer P-N junction element Above, for covering and insulating the components above and below; a plurality of inductive elements are arranged above the chemical vapor deposition oxide layer element, and in between Said dielectric layer as an isolation insulating layer. 2. The structure of the built-in inductor of the integrated circuit described in item 1 of the patent application and the use of P-N elements to block the parasitic current, which is characterized by including a built-in inductance element and blocking the inductance element from generating parasitics. Chemical vapor phase, especially accumulated oxide layer P-N junction element with current loss, wherein when the first conductivity type doped region is p-type 200428640 VI. Scope of patent application: The second conductivity type doped region of the impurity exchange type is N-type doped. The structure of the integrated circuit of the integrated circuit described in the first item of the patent scope and the structure using N elements to block the parasitic current are characterized in that they include a built-in power = and a grid-shaped p_N that blocks the parasitic loss current generated by the inductance element The junction region element, wherein when the first conductivity type doped region is N-type doped, the conductivity type doped region is p-type doped. ^ The structure of the built-in inductor of the integrated circuit described in item 1 of the patent application and the use of 70 pieces to block the parasitic current is characterized in that the semiconductor substrate is a broken substrate. = The structure of the built-in inductor and utilization of integrated circuits as described in item 丄 of the patent application, and the fN element to block parasitic current, characterized in that the first 'electric type doped region and the The doped region of the second conductivity type passes 650 after the ions of the first conductivity type and the ions of the second conductivity type are implanted. c to i200. c 彡 is formed by an annealing step. 6. The structure of the built-in inductor of the integrated circuit and the use of a PN element to block the parasitic current as described in item 丨 of the patent scope, wherein the coil material of the built-in inductor element may be aluminum metal. Or copper metal. Page 14