TW200428604A - Testing method for high density flip chip BGA - Google Patents

Abstract

A testing method for high density flip chip BGA package is provided with following steps: providing a metal substrate 302, forming an interconnect layer 304, forming a chip displacement opening 306 formed with a placement region, a dispensing region, and a vacuum region; forming bump openings 308 and plating a bump pad layer in the bump openings 310; inspecting for missing bump pads just plated for electrical opens 312 as part of the testing step; patterning the metal layer most far away from the metal substrate to form a trace 314; visual evaluating the trace 316, forming a solder mask layer 318 to expose ball pads, probing the ball pads for electrical shorts 319, adhering a flip chip, filling underfill 322 by dispensing in the dispensing region and vacuuming in the vacuum region; molding the chip 324 and ball mounting.

Description

200428604 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a high-density Flip Chip Ball Grid Array Package test process', and particularly to a simplification and savings Cost-effective high-density flip-chip ball grid array packaging test process. [Previous Technology] The development trend of chip packaging technology is toward reduction in size and increase in input / output contacts, so flip-chip (f 1 i P c h i p) technology has become one of the mainstream. The flip-chip technology mainly forms long bumps on external contacts (usually metal pads) on the wafer, and is electrically connected to the substrate through the bumps. With flip-chip technology, I / O contacts can be connected at high density, and low-inductance connections can be established. Conventional testing of package substrate flip-chip ball grid array type package substrates, because the pitch is small, test fixtures are very expensive and the test methods are more complicated. [Summary of the Invention] In order to solve the conventional problems, one of the objectives of the present invention is to propose a high-density flip-chip ball grid array packaging test process, and test in the packaging process, and some of the test steps can also be performed. As a step in the packaging process, it can simplify the test process and reduce the test cost. One of the objects of the present invention is to provide a high-density flip-chip ball grid array package testing process, which can be applied to package high-density flip-chip wafers with micro-pitch bumps. One of the objectives of the present invention is to propose a high-density flip-chip ball grid array package testing process, which can reduce the stress and strain on the wafer,

10394twf.ptd Page 6 200428604 2 C 'degree depends on accessibility and good prestige and issuance is five high-density and high-density species-9 out of Ti Mingfa's edition and the above-mentioned Chengda is a genus, with gold plate in the base Overlay, the gold layer is on the front line for continuous lifting: a package into a% / ο process surface tabulation test, the second test of the first package and a surface array matrix, a ball, a crystal, and the gold should be separated from the farthest layer In addition, the conductive layer and the conductive layer are connected in a continuous shape. The electrical shape of the layer is intersected by 1, and the number of secondary shapes. The first step is to cover the most important ones. unit. The appearance of the exposed state is as follows. The entire surface of the second surface connected to the surface of the meter and the second surface is used as the base metal wire. The base of the board mouth is set to be connected with the empty area of the system. The area with the glue opening point is placed in the center of the crystal, this area. The hollow layer of the electric layer and the extension of the base adhesive point of the plate area are exposed to the open area opposite to the corner, and the crystal is placed on the plate. The open edge of the crystal mouth is convex and multiple. Phase shaped area. In the field, the area is convex and the crystal is convexly measured in this layer. 〇 The standard layer is a test guide for a copy of the mining department. The exposed part of the exposed layer exposed by the detonation station is exposed on the exposed cover, and the inner and inner exposed layers of the exposed block are plated with a test circuit. The layer test line can be used to detect the situation and it is full-board. It is not the most important to use the Λ layer to determine whether the lack of gold nuggets is far from convex or not. The standard fruit refers to the structure of the polycrystalline wire of the junction product. The inner layer of the wire layer is welded to prevent the substrate from being placed on the substrate to form a substrate in the form of crystal gold. The film is far away from the film, and the most crystallized circuit is covered. One line is attached to the test section. Headstorm pads. In the case of the ball, the main surface of the welding layer has a sheet D with a convex block and a convex block to fill the bottom. Fill in one side and proceed. The main block is connected to the continuous electrical block layer. After the exposure, the empty ball of the storm will be drawn one by one and go forward. 〇The gap between the glue block and the convex rubber point is filled at the bottom of the rubber mouth. The crystal will be placed in the film. Stepping rubber zone 10394twf.ptd Page 7 200428604 V. Description of the invention (3) Step, electrically connect a plurality of solder balls to a solder ball pad. The above steps for electroplating the test index layer include electroplating copper, or sequentially electroplating copper, nickel, gold, or electroplating tin-lead, or electroplating tin, etc., and determine the bump pad by detecting the electroplating quality of the test index layer. Are there missing 'as a result of electrical testing. For example, ’can be judged by the thickness of the mineral layer (test indicator layer, that is, bump pad) or the color of the plating layer (test indicator layer, that is, bump 塾). In the step of forming the interconnection, the method includes: forming a thin film interconnection layer by a thin film deposition method, covering the first surface of the metal substrate, forming a first dielectric layer and a first wire layer, and the first A dielectric layer covers the first surface of the metal substrate, and a first wire layer covers the first dielectric layer. Then, a build-up interconnecting layer is formed by a lamination method, and the thin-film interconnecting layer is covered, including ... forming a second dielectric layer, forming a second wire layer covering the second dielectric layer, repeating this step number Times to form a laminated structure layer. In the above-mentioned step of forming the interconnect, the method further includes: forming a through hole outside the wafer placement area of the metal substrate, penetrating the first dielectric layer and the second dielectric adjacent to the first dielectric layer. Layer to contact the second wire layer closest to the metal substrate and the metal substrate, and simultaneously contact the first wire layer. The wiring pattern of the wire layer in the interconnect is wavy at the edge corresponding to the opening where the chip is placed. According to the features of the present invention, the wiring layer farthest from the metal substrate of the interconnect is in a state of full electrical connection, which is the state before the last patterning of the interconnect layer. Therefore, the last patterning of the interconnect layer

10394twf.ptd Page 8 200428604 V. Description of the Invention (4) 'Before and after the bump opening is formed, a test index layer can be formed in the bump opening by electroplating to form a bump pad, covering the On the wire layer exposed by the bump opening. At this time, if the electrical connection of the interconnect layer is correct (no leakage), each bump opening should be properly plated with a test indicator layer (bump pad). Based on this feature, the electroplating quality of the test index layer (bump pad) can be used as a result of the electrical test. For example, the thickness of the test index layer (bump pad) can be used, or the index layer (bump pad) can be visually tested. Color, you can know whether the electrical connection of the interconnect layer is missing, which can simplify the test process and cost. According to the features of the present invention, there is a φ pair of the dispensing area and the evacuation area extending diagonally from the diagonal of the wafer placement area. Therefore, the present invention is to perform the dispensing on one side of the wafer placement area and the vacuum on the opposite side to This method can shorten the time for filling the bottom glue, and can effectively prevent the occurrence of air bubbles. In the same way, because the dispensing area and the vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized and the reliability of the package can be improved. According to the features of the present invention, a through hole is used to make the second wire layer of the laminated interconnecting layer closest to the metal substrate contact the metal substrate, and at the same time contact the first wire layer, and then ground the metal substrate to obtain a good current. Conveying effect. According to the features of the present invention, each wire layer is wavy at the edge corresponding to the placement opening of the wafer, and has a buffering effect when the substrate is deformed, and the substrate's ability to withstand strain can be improved due to zero. In order to make the above and other objects, features, and advantages of the present invention more comprehensible

10394twf.ptd Page 9 200428604 V. Description of the invention (5) Obviously easy to understand. The following is a detailed description of a preferred embodiment, with the accompanying drawings' for detailed description as follows. [Embodiment] Please refer to the first in order FIG. 7 is a cross-sectional view showing a manufacturing process flow of a high-density flip-chip ball grid array test package according to a preferred embodiment of the present invention. At the same time, Fig. 8 is a block diagram showing a high-density flip-chip ball grid array test package process flow chart. As shown in step 302 of FIG. 8, please refer to FIG. 1 to provide a metal substrate 200 having a first surface 200 a and a second surface 200 b. Next, as in step 304 in FIG. 8, the interconnect layers 2 2 and 2 0 8 are formed (FIGS. 1 to 2). First, an interconnecting layer (thin-film interconnecting layer) 202 is formed by a thin film deposition method (see FIG. 1) and covers the first surface 200a of the metal substrate 200. For example, a dielectric layer (first dielectric layer) 204 is formed in a coating manner, and a conductive layer (first conductive layer) 206 is formed, for example, by a sputtering method and a semi-additive method. The dielectric layer 204 is coated on the first surface 200a of the metal substrate 200. The conductive layer 2 0 6 covers the dielectric layer 2 0 4. Then, a built-up method is used to form an interconnect layer (build-up interconnect layer) 208 (see FIG. 2), which is composed of a dielectric layer (second dielectric layer) and a conductive layer (second conductive layer) ) Are alternately formed and cover the interconnect layer 202. Continuing as in FIG. 1, a patterned dielectric layer (second dielectric layer) 210 is formed, which is covered on the interconnect layer 202, and a patterned conductive layer (second conductive layer) 212 is formed, which is covered on the dielectric. Layer 2 0 〇 In order to improve the current delivery of the wafer during the formation of the interconnect layer 208

10394twf.ptd Page 10 200428604 V. Description of the Invention (6) The effect is further listed in the following steps (see Figure 1). As exemplified in FIG. 1, a through hole 2 1 8 is formed in a manner of laser drilling and electroplating, and the wafer placement area 250 a is located at the wafer placement opening 2 500 of the metal substrate 2 0 (the details are shown in FIG. 9 described later). In addition, the first dielectric layer 204 and the second dielectric layer 210 adjacent thereto are penetrated to contact the second wire layer 212 and the metal substrate 200, and simultaneously contact the first wire layer 206. Here, the metal substrate 200 can be connected to the ground, and in accordance with the above-mentioned structure characteristics of the through hole 218, a short and wide ground connection can be formed, thereby greatly improving the current transmission efficiency of the chip. As shown in FIG. 2, the steps of forming the interconnect layer 208 by the build-up method are continued, and a patterned dielectric layer (second dielectric layer) 214 is formed, covering the wire layer 212, and then forming a wire. Layer (second wire layer) 216 overlying the dielectric layer 212. At this time, the wiring layer 216 is not patterned for the time being, so that the wiring layer 2 16 farthest from the metal substrate 200 is in a state of full electrical connection. Although the multilayer interconnecting layer 208 shown in FIG. 2 uses two layers of the second wire layer and the second layer of the second dielectric layer as examples, this is only an example, and the number of layers is not limited to this. According to the features of the present invention, the lead layer of the inner wiring farthest from the metal substrate (that is, the surface layer) is in a state of full electrical connection, which means the state before the last patterning of the inner wiring layer. Next, as shown in step 3 of FIG. 8, please refer to FIG. 3 to form a wafer placement opening 250 on the second surface 200 b of the metal substrate 200 to expose a part of the dielectric layer 204. Please refer to FIG. 9 at the same time. The wafer placement opening 250 has a wafer placement area 250a, a little glue area 250b, and a vacuum area 2 50 c. The reference numeral 2 60 indicates the chip to be attached in this area. Chip

10394twf.ptd Page 11 200428604 V. Description of the invention (7), (see Figure 7 for details). The shape of the wafer placement opening 2 50 is as follows. The wafer placement area 2 50 a is slightly larger than the flip-chip wafer 2 6 0 to be attached. The dispensing area 250 a and the evacuation area 250 b are the same as the wafer placement area. 250a is connected and is a pair of areas extending outward along the diagonal of the wafer placement area 250a. As shown in step 308 in FIG. 8, as in FIG. 3, a plurality of bump openings 252 are formed, and 204 are exposed in the exposed dielectric layer to expose a part of the wire layer 206. Methods of forming bump openings include, for example, laser drilling. As shown in step 3 1 0 in FIG. 8, please refer to FIG. 4. Electroplating a test index layer 2 5 4 in the bump opening 2 5 2, and covering the wire layer exposed by the bump opening 2 5 2. 206. At this time, since the lead layer 2 1 6 farthest from the metal substrate 200 is in a state of full electrical connection, it can be used as a basis for electroplating. Among them, the steps of the electroplating test index layer 2 5 4 include electroplating copper, or sequentially electroplating copper, copper, gold, or electric ore tin, or electric ore tin. The test index layer 2 5 4 is also As a bump pad. As shown in step 3 of FIG. 8, the electroplating quality of the test index layer 2 5 4 is detected as the result of the electrical measurement. Because if the electrical connection of each of the interconnecting layers 2 0, 2 0 8 is missing, the conductor layer 2 0 6 exposed by the corresponding bump opening 2 5 2 will not be plated with test indicators. Layer (bump pad) 2 5 4. Or, when the electrical connection of each of the inner wires 2 0, 2 and 8 is bad, correspondingly, the quality of the plating on the wire layer 2 06 exposed by the corresponding bump opening 2 5 2 is not good. Based on this feature, the thickness of the plating layer (the thickness of the test indicator layer (ie, the bump pad) 254) or the color of the mineral layer (the test indicator layer (ie, the bump pad)) 2 5 4 color) Discrimination of plating and electroplating

10394twf.ptd Page 12 200428604 V. Description of the invention (8) Quality. For example, if nickel and gold are applied to the plating test index layer (bump pad) 2 5 4, the plating quality (ie, the result of the electrical test) can be easily discriminated by color. In the above test, if it is a defective product, it can be sorted out first. If it is a good product, it can be continued as shown in Figure 3, step 3 1 4. Please refer to Figure 5, pattern the wire layer 216 farthest from the metal substrate 200. In order to form a circuit pattern 21 6a °, as in step 3 1 6 of FIG. 8, visually inspect the circuit pattern 2 1 6 a. So far, since the wiring patterns 216a here are farthest from the metal substrate 200 (that is, farthest from the flip-chip wafer 2 60), the distance between the wiring patterns 2 1 6a is large, and the wiring patterns can be visually inspected directly. Then, as shown in step 3 1 in FIG. 8, please refer to FIG. 6 to form a solder resist layer 220 covering the interconnect layer 208. The solder resist layer 220 has a plurality of openings 220 a to expose a part of the most The conductive wire layer 216 is far from the metal substrate 20 () to form a ball pad 2 2 2. After the step of forming the solder resist layer 2 2 0, the solder ball pad 2 2 2 can also be tested with a probe as in step 3 19 of FIG. 8 to perform a short-circuit test. After performing the above test steps, attach the wafer to the qualified substrate, as shown in step 3 2 0 in Figure 8, refer to Figure 7, and attach a flip-chip wafer 2 60 to the wafer placement opening 2 50. The wafer placement area is within 250 a. The flip-chip wafer 260 has an active surface 260a, and a plurality of bumps 262 are formed on the active surface 260a. Through a re-soldering step, the bump pads exposed by the bumps 262 and the bump openings 252 are electrically connected to the wire layer 206.接 者 ’Such as the step 3 2 2 in the figure 8 to perform a primer filling step, in

10394twf.ptd Page 13 200428604 V. Description of the invention (9) Wafer placement opening 2 5 0 dispense area 2 5 0 b for dispensing, and vacuum extraction area 2 5 0 c for vacuuming 2 7 0 fills in the gap between the bumps 2 6 2. According to the spirit of the present invention, it is not necessary to limit the shape of the wafer placement opening 250. The key is that the wafer placement area 250a is close to and slightly larger than the shape of the flip-chip wafer 260. The dispensing area 250a and the vacuuming area 250b are connected to the wafer placement area 250a, and are located on opposite sides of the wafer placement area 250a, respectively, to facilitate the vacuuming operation. As shown in step 324 in FIG. 8, as in FIG. 7, a glue step is performed. A piece of glue material 2 90 is filled into the wafer placement opening 2 50 to cover the bottom glue 2 7 0 to surround the chip-on-wafer. 2 6 0, and a part of the flip chip 2 6 0 is exposed. As shown in step 326 in FIG. 8, as in FIG. 7, a ball planting step is performed, and a plurality of solder balls 2 8 0 are electrically connected to the exposed portions of the solder resist 2 2 0 through the solder ball pad 2 2 2. As far as the conductive layer 216 is farthest away from the metal substrate 200, the flip-chip ball grid array package is completed. With the simplified test process described above, the most expensive and complicated electrical test steps (connected to the bumps of high-density flip-chip wafers) in conventional techniques can be visually inspected, which greatly saves test costs. Please refer to FIG. 10, which shows an example of a wiring pattern corresponding to the periphery of the chip placement opening of each wire layer. The first wire layer is taken as an example in the figure. It is worth noting here that the method for forming the above-mentioned wire layer (206, 21, 2, 1 16) includes, at the edge corresponding to the chip placement opening 2 50 (as shown by the dashed line 2 4 8 in the figure). Wavy line pattern. The reason for the formation of this wavy line pattern at the edge of the corresponding opening where each wafer layer is placed is: according to the features of the present invention, the crystal ball of the present invention

10394twf.ptd Page 14 200428604 V. Description of the invention (10). In the grid array package, the part outside the chip placement openings' includes a metal substrate, a thin film interconnect layer and a laminated structure layer. However, in the wafer There is no part of the metal substrate in the placement opening, so this packaging structure becomes the weaker part of the structure around the corresponding wafer placement opening. According to the spirit of the present invention, the use of a wavy elongated circuit pattern at the edges of the chip placement openings 250 is a buffering effect when the substrate is deformed (such as thermal expansion), so that the wires are not deformed and deformed. Destruction 'can thus increase the reliability of the product. It can be seen that the present invention does not need to be limited to this wavy shape, in short, such as a zigzag shape or other bent shapes. It can be known from the disclosure of the embodiments that the present invention has at least the following advantages: (1). Before the patterning of the wire layer (the last patterning step) farthest from the metal substrate (that is, the farthest from the flip chip), the present invention has: After the wire layer for the electrical connection of the bumps is exposed, the wire layer for the comprehensive electrical connection can be used as the basis for electroplating, and the test index layer (bump pad) can be electroplated. If the electrical connection of each interconnect layer is good, the plating quality of this test indicator layer (bump pad) is also good; if there is a situation of electrical leakage or poor electrical connection in the interconnect layer, there will be Failure to plate the test index layer (bump pad) or poor plating quality. In this way, in addition to being used as a subsequent bump pad connected to the bump, this test index layer (bump pad) can also be used as the result of electrical testing for its plating quality. (2) · Continuing the characteristics of (1), by properly selecting the material of the plating test index layer (bump pad), the result of the electrical test can be determined by the thickness of the plating layer or the color of the plating layer visually. The most expensive of the conventional techniques that can be visually inspected

10394twf.ptd Page 15 200428604 V. Description of the invention (11) and the most complicated electrical test steps (connected to the bumps of high-density flip-chip wafers), greatly saving test costs. (3). In the present invention, a pair of dispensing areas and vacuum-extracting areas extend diagonally across the wafer placement area. Therefore, the present invention performs dot victory in one corner of the wafer placement area, and performs vacuum evacuation in the opposite side. This method can shorten the time for filling the bottom glue, and can effectively prevent the occurrence of air bubbles. In the same way, because the dispensing area and the vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized, and the reliability of the package can be improved. (4) The present invention uses a through hole to contact the second wire layer of the laminated interconnecting layer closest to the metal substrate and the metal substrate, and directly connects the wire layer of the thin film interconnecting layer to the metal substrate through the through hole. Then, the metal substrate is grounded, so that the flip-chip wafer can obtain a good current transmission effect. (5) Each wire layer of the present invention is wavy at the opening where the corresponding wafer is placed, and has a buffering effect when the substrate is deformed, thereby improving the ability of the substrate to withstand strain and thus improving the reliability of the product. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

10394twf.ptd Page 16 200428604 Brief Description of Drawings Figures 1 to 7 show cross-sectional views of a high-density flip-chip ball grid array packaging test process flow diagram according to a preferred embodiment of the present invention; Figure 8 shows a process according to the present invention A block diagram of a high-density flip-chip ball grid array package test process flow diagram of a preferred embodiment; FIG. 9 illustrates an exemplary plan view of a wafer placement opening according to a preferred embodiment of the present invention; and FIG. 10 An exemplary plan view of one of the wiring patterns of each of the wiring layers according to the preferred embodiment of the present invention is shown. [Illustration of diagrammatic representation] 200: Metal substrate 202: Interconnect layers 204, 210, 214: Dielectric layers 206, 212, 216: Wire layer 2 0 8: Interconnect layer 21 6a: Circuit pattern 2 18: Through hole 220: solder mask 220a: opening 2 2 2: solder ball pad 2 4 8: edge of wafer placement opening 2 5 0: wafer placement opening 2 5 0 a: wafer placement area 2 5 0 b: dispensing area 250c: Evacuation area 2 5 2: Bump opening 2 6 0: Chip on wafer 2 54: Test index layer (bump pad) 2 6 0 a: Active surface 262: Bump 2 7 0: Primer 2 8 0 : Solder ball 2 9 0: Sealant read

10394twf.ptd Page 17

Claims (1)

200428604 VI. Scope of patent application ~ 1 · A high-density flip-chip ball grid array package testing process includes: providing a metal substrate with a first surface and a second surface; forming an interconnect layer, covering the The first surface of the metal substrate includes: forming a dielectric layer, forming a wire layer covering the dielectric layer, repeating this step several times to form the interconnect layer, and the distance from the metal substrate farthest from the metal substrate. The wire layer is in a state of comprehensive electrical connection; a wafer placement opening is formed on the second surface of the metal substrate to expose a part of the dielectric layer adjacent to the metal substrate, and the wafer placement opening has a wafer A placement area, a glue area, and a vacuum area, wherein the glue area and the vacuum area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area; A plurality of bump openings, in the dielectric layer exposed by the wafer opening, to expose a part of the wire layer; electroplating a test index layer in the bump openings to form a plurality of bumps Covering the wire layer exposed by the bump openings; detecting the plating quality of the bump pads as a result of electrical measurement; patterning the wire layer farthest from the metal substrate to Forming a circuit pattern; visually inspecting the circuit pattern; forming a solder resist layer covering the interconnect layer, the solder resist layer having a plurality of openings to expose a portion of the wire layer farthest from the metal substrate To form a plurality of solder ball pads; 10394twf.ptd Page 18 200428604 VI. Patent application scope Attaching a flip chip to the wafer placement opening, the flip chip has an active surface, and a plurality of bumps are formed on the active surface to make the convex The block is electrically connected to the wire layer exposed by the openings of the bumps; a primer filling step is performed, the glue is dispensed in the dispensing area of the opening where the wafer is placed, and the vacuum is evacuated in the evacuation area to A primer is filled into the gaps between the bumps; and a ball-planting step is performed to electrically connect a plurality of solder balls to the solder balls. 2. The high-density flip-chip ball grid array package testing process according to item 1 of the scope of patent application, wherein the step of forming the interconnect includes: forming a thin-film interconnect layer by a thin film deposition method, and covering the metal The first surface of the substrate forms a first dielectric layer and a first wire layer, the first dielectric layer covers the first surface of the metal substrate, and the first wire layer covers the first dielectric. And forming a laminated interconnecting layer 'overlaying the thin film interconnecting layer by a lamination method, including: forming a second dielectric layer' forming a second wire layer overlying the second dielectric layer, and repeating This step is performed several times to form the laminated structure layer. 3. The high-density flip-chip ball grid array package testing process according to item 2 of the scope of patent application, wherein in the step of forming the interconnect, the method further comprises: forming a through hole, and placing the wafer on the metal substrate Outside the region, penetrate the first dielectric layer and the second dielectric layer adjacent to the first dielectric layer to contact the second wire layer and the metal closest to the metal substrate 10394twf.ptd Page 19 200428604 6. Scope of patent application The substrate and contact the first wire layer at the same time. 4. The high-density flip-chip ball grid array package testing process as described in item 3 of the scope of patent application, wherein the method of forming the through hole includes laser drilling and electroplating. 5. The high-density flip-chip ball grid array package testing process as described in item 3 of the patent application scope, wherein the metal substrate is connected to ground. 6. The high-density flip-chip ball grid array package testing process as described in item 1 of the patent application scope, wherein the step of electroplating the test index layer includes electroplating copper. 7. The high-density flip-chip ball grid array package testing process as described in item 1 of the scope of patent application, wherein the step of electroplating the test index layer includes sequentially smelting copper, nickel, and gold. 8. The high-density flip-chip ball grid array package testing process as described in item 1 of the patent application scope, wherein the step of electroplating the test index layer includes electroplating tin fault. 9. The high-density flip-chip ball grid array package testing process as described in item 1 of the patent application scope, wherein the step of plating the test index layer includes tin plating. 10, The high-density flip-chip ball grid array packaging test process described in item 1 of the scope of the patent application, wherein the method of detecting the plating quality of the bump pads is visual inspection. 11. The high-density flip-chip ball grid array package testing process as described in item 10 of the scope of the patent application, wherein the method of detecting the plating quality of the bump pads includes using the thickness of the bump pads to discriminate. 10394twf.ptd Page 20 200428604 VI. Application for patent scope 12 2. The high-density flip-chip ball grid array packaging test process as described in item 10 of the scope of patent application, wherein the method for detecting the plating quality of the bump pads Including the use of the color of these bump pads for discrimination. 13. The high-density flip-chip ball grid array package testing process according to item 1 of the scope of patent application, wherein the method of forming the wire layers in the interconnect includes: at an edge corresponding to the opening where the wafer is placed. Form a wavy line pattern. 1 4. According to the high-density flip-chip ball grid array package testing process described in item 1 of the scope of patent application, after the step of forming the solder mask layer, the method further includes testing the solder ball pad with a probe to perform a short-circuit test. . 15. According to the high-density flip-chip ball grid array packaging test process described in item 1 of the scope of the patent application, a method for forming the bump openings includes a laser drill 孑 L. 16. The high-density flip-chip ball grid array packaging test process described in item 1 of the patent application scope further includes a glue step, filling the wafer placement opening with a glue material to cover the primer 'Enclose the flip-chip wafer and expose a portion of the flip-chip wafer. 10394twf.ptd Page 21