TW200428533A - Semiconductor devices having a metal silicide bi-layer and the method for fabricating the same - Google Patents

Abstract

A method for fabricating a semiconductor device having a metal silicide bi-layer. First, a silicon substrate having a gate and a source/drain region thereon is provided. Next, a conformable nickel layer and a conformable cobalt layer are deposited overlying the silicon substrate in sequence. Next, heat treatment is preformed on the substrate to form a cobalt/nickel silicide bi-layer. Finally, the cobalt layer and the nickel layer without siliciding are removed. A semiconductor device having a metal silicide bi-layer is also disclosed.

Description

200428533 V. Description of the Invention (l) Field of the Invention The present invention relates to a kind of metal silicide-a kind of self-made metal ^, in particular, a method for forming a semiconductor device having the above-mentioned double-layer structure and the prior art. · With the development of integrated circuits' accumulation degree. When the component size shrinks, it improves the ancient meaning of the element, which has been widely discussed recently. The nU resistance value has become the industry. I regard it as a metal silicide button. Low-resistance metal silicide is currently widely used. Π J is: the closed and source / non-poles of the component are used to reduce the connection; = product = road hanging method is made by self-aligned petrification technology (self_ali_d The most important thing is that the metal is first formed in a hair treatment so that the metal reacts with Shi Xi to form a metal silicide on the gate and source / drain. / Among all current metal silicide materials, the resistivity of titanium disilicide), cobalt disilicide (CoSi2), and nickel silicide (NiSi) is low, about 15 ~ 20 # 〇hm-cm. As far as titanium silicide is concerned, it has better thermal stability and titanium can effectively reduce nat i ve oxi de on the surface of the silicon substrate. However, in the manufacturing process, a two-stage tempering process is usually required to form a facet-centered (C54-Ti Siz) structure with a low resistivity. Furthermore, as the line width shrinks, such as below 0 · 2 5 // m, the thickness of titanium disilicide becomes thinner and agglomeration easily occurs, which increases the sheet resistance, so-called narrow

0503-9975TWF (Nl); TSMC2003-0015; Spin.ptd Page 6 200428533 V. Description of the invention (2) The narrow-line-width effect. Therefore, when the line width is as small as 0 · 25 a m or less, this material is no longer applicable. As far as cobalt silicide material is concerned, its thermal stability is similar to that of titanium silicide material ^, but its sheet resistance value is not as much related to line width as titanium silicide material, so it becomes 0.1 8 em or less. Commonly used materials. However, it cannot reduce the native oxide layer on the silicon surface like titanium, and it is necessary to pay attention to the cleaning of the silicon surface. In addition, its process also requires a two-stage tempering process to shape & low-resistivity cobalt disilicide, and when the line width is reduced below 65nm, high tempering temperature will cause the formation of agglomeration and increase Chip resistance value. As far as nickel silicide materials are concerned, only one stage of the tempering process is required in the process and the temperature does not need to be too high 'and too high, and it will form a nickel disilicon jNlSi2) phase with higher resistivity. Furthermore, the resistivity does not change much with the narrowing of the line width. In addition, it consumes more silicon than titanium silicide and Shi Xihua Ming, and can avoid the phenomenon of spiking on the superficial junction. Unfortunately, when manufacturing integrated circuits, it is often applied to the plasma process containing fluorine. The fluorine atoms in rhenium are liable to bond with the recording atoms of this material to generate an amorphous phase on the surface, causing the sheet resistance value to increase. . U.S. Patent No. 5, 047, 3 67 discloses a method for forming a self-aligned titanium nitride / cobalt silicide double-layer structure, which is firstly considered as a sintered sintered slab, and sequentially deposited on a Shixi substrate. The titanium metal layer and the cobalt metal I are heat-treated in a nitrogen-containing atmosphere to complete the fabrication of the self-aligned titanium / cobalt silicide double-layer structure. In addition, the manufacturing method of the barrier layer 6'5〇9'265 ___ ^, a titanium-niobium alloy layer is deposited on a silicon substrate, and then the titanium-nitride / titanium-silicide-niobium double-layer is seeded For the system, see Shen Guo &k; Shaped by the above method

200428533 V. Description of the invention (3) In the double-layer structure, the focus is on forming a barrier layer on the metal silicide layer to avoid the occurrence of spikes in the subsequent production of plugs and reduce the resistance. However, the metal petrochemical materials used are currently: Gold: Cobalt. These materials cannot be applied to very small scales or as described earlier. Summary of the invention: The objective of the present invention is to provide a double-layer structure and a method for forming the same, and a metal silicide device having a double-layer metal silicide layer and a method for forming the same. Recorded metal stone Xi Er = double-layer structure of silicidation layer to replace the traditional metal silicide single-layer surname = metal micro line width process. Furthermore, the phenomenon of rising sheet resistance caused by the narrow line width effect of the thick nickel metal in the lower layer, and meanwhile, by avoiding a thin cobalt metal silicide layer and protecting the lower nickel metal silicide layer in the process of ▲ 人 f ^ damage. π 3 I 1: According to the above-mentioned object, the present invention provides a metal silicic acid structure comprising a -Shixi substrate and a -Ni / Ni double-layer metal petrified :: a nickel double-layer metal petrified compound is provided on the Shixi substrate on. Langzhong, ^

It is located above the silicon substrate, and the cobalt metal silicide layer is located on the nickel metal silicide layer. Among them, the nickel metal layer has a thickness of 5% to 30%, and preferably 15%. In addition, the junction / nickel double-layer metal lithotripsy / nickel double-layer metal is subjected to a heat treatment plant.

200428533 V. Description of the invention (4) The thickness is in the range of 100 to 200 Angstroms, and the thickness of the cobalt metal layer is in the range of 50 to 200 Angstroms. In addition, the temperature of the heat treatment is in the range of 350,000 to 5500c, and the time of the heat treatment is in the range of 10 to 60 seconds. According to the above object, the present invention provides a method for forming a metal silicide double layer structure. First, a silicon substrate is provided, and a nickel metal layer and a cobalt metal layer are sequentially and compliantly deposited on the silicon substrate. Then, a heat treatment is performed on the silicon substrate to form a cobalt / nickel double metal silicide on the silicon substrate. Furthermore, the thickness of the nickel metal layer is in the range of 100 to 200 Angstroms, and the thickness of the metallic layer is in the range of 50 to 200 Angstroms. Furthermore, the above heat treatment is a rapid thermal tempering treatment. Among them, the temperature of rapid thermal tempering is in the range of 350 to 550 ° C, and the time of rapid thermal tempering is in the range of 10 to 60 seconds. Furthermore, the thickness of the cobalt metal silicide layer is 5% to 30%, and preferably 15%, of the thickness of the cobalt / nickel double metal silicide. In addition, according to the above object, the present invention provides a semiconductor device 'having a metal silicide double-layer structure, which includes a stone substrate and a diamond / recorded double-layer metal stone compound. The Shi Xi substrate has a gate and a source / dead region. The nickel / nickel double-layer metal silicide is disposed on the gate and source / drain regions. In the middle, the nickel metal silicide layer is located above the gate and source / drain regions, and the metal silicide layer is located above the nickel metal silicide layer. Furthermore, the spreading sound of the first metallization layer— ^ ^ 〇Λ The sum of the increase is 5% to 30% of the thickness of the cobalt / nickel double-layer metal silicide, and preferably 15%. Moreover, the double-layer metal fragment is formed by simultaneously

200428533 V. Introduction to the Invention (5) The double-layer metal is formed by performing a heat treatment. The thickness of the nickel metal layer is in a range of 100 to 200 angstroms, and the thickness of the cobalt metal layer is in a range of 50 to 200 angstroms. In addition, the temperature of the heat treatment is in the range of 35 to 55 t, and the time of the heat treatment is in the range of 10 to 60 seconds. Furthermore, according to the above-mentioned object, the present invention provides a method for forming a semiconductor device having a metallized double-layered structure. First, a silicon substrate is provided, which has a gate and a source / drain region, and a nickel metal layer and a cobalt metal layer are sequentially and compliantly deposited on the silicon substrate. Then, a heat treatment is performed on the silicon substrate to form a cobalt / nickel double metal silicide on the gate and source // drain regions. It further includes removing the non-silicided cobalt metal layer and nickel metal layer by a sulfuric acid and hydrogen peroxide mixed solution (SPM). Furthermore, the thickness of the nickel metal layer is in the range of 100 to 200 angstroms, and the thickness of the metal layer is in the range of 50 to 200 angstroms. In addition, the above heat treatment is a rapid thermal tempering treatment. In beans, the temperature of rapid thermal tempering is in the range of 350 to 55 0 t, and the time of rapid thermal tempering is in the range of 10 to 60 seconds. The thickness of the metallization layer is 5% to 30%, and preferably 15%, of the metallization layer. In order to make the above-mentioned objects, features, and advantages of the present invention specific preferred embodiments, and in accordance with all the following, easy to understand, the following: The drawings of children and corpses are described in detail as an embodiment: First Examples

200428533 V. Description of the invention (6) The method of forming a metal silicide double-layered structure on a silicon substrate according to the first embodiment of the present invention will be described below with reference to Figures 1a to 1b. First, referring to FIG. 1, a clear substrate 10 is provided, such as a broken crystal circle. Next, a nickel metal layer is sequentially and compliantly deposited on the silicon substrate 10 by conventional deposition techniques, such as physical vapor deposition (PVD) or chemical vapor deposition (CVD). 12 and a cobalt metal layer 14. In this embodiment, the nickel metal layer 12 is formed by chemical vapor deposition, and its thickness is in the range of 100 to 200 angstroms. Furthermore, the cobalt metal layer 14 is also formed by chemical vapor deposition, and its thickness is in the range of 50 to 200 angstroms. Next, referring to FIG. 1b, a heat treatment is performed on the silicon substrate 10, for example, using a conventional tempering furnace tube (a η nea 1 ingfurnace) method or rapid thermal annealing (RTA) to make the nickel metal The nickel and cobalt atoms in the layer 12 and the first metal layer 14 diffuse into the silicon substrate 10 to form a cobalt / nickel double-layer metal silicide 19 on the silicon substrate 10. Here, the initial / nickel double-layer metal silicide 9 includes a nickel metal silicide layer 16 located above the silicon substrate 10 and a cobalt metal silicide layer 8 located above the nickel metal silicide layer 16. Furthermore, a cobalt nickel silicide layer (not shown) is formed at the interface between the nickel metal silicide layer 16 and the cobalt metal silicide layer 18. In this embodiment, a rapid thermal tempering process is performed on the silicon substrate to form an initiation / nickel double-layer metal silicide. The temperature of the rapid thermal tempering process is in the range of 350 to 55 ° C. , And the time of rapid thermal tempering is in the range of 10 ~ 60 seconds. Under this tempering condition, the Co-Si silicide layer (CoSi) and dicobalt silicide (Co2Si) coexist in two phases. Therefore, its

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The higher the chip resistance, the phenomenon occurs. However, there will be no agglomeration. It is difficult for the starting atom to be bonded to the fluorine atom. Because _, ^ The first metallization layer 18 formed above the stonelization layer 16 can be used as a gift 1 ^ 1 to avoid the fluorine atoms directly interacting with the white and biochemical layer 1 in the subsequent plasma process containing fluorine. The nickel atoms in 6 are bonded and an amorphous mesh is formed on the surface of the silicon silicide layer. The resistance of the sheet increases and the contact resistance increases.

At the same time, in order to reduce the overall sheet resistance of the cobalt ^ / nickel double-layer metal silicide 丨 9, in this embodiment, the thickness of the cobalt metal silicide layer 18 is equal to the thickness of the cobalt / nickel double-layer metal silicide 19 5% ~ 30%. Preferably, the thickness of the cobalt metal silicide layer 18 is 5% of the thickness of the cobalt / nickel double-layer metal silicide 19.

Similarly, please refer to FIG. 1b, which illustrates a schematic cross-sectional view of a metal silicided double-layer structure according to the first embodiment of the present invention. It includes a silicon substrate i 0 and a cobalt / nickel double metal silicide 9. The cobalt / nickel double-layer metal silicide 19 is not placed on a silicon substrate 10. It includes a nickel metal silicide layer 16 above the silicon substrate 10 and a cobalt metal silicide layer 18 above the nickel metal silicide layer 16. In this embodiment, the thickness of the cobalt metal silicide layer 8 is 5% to 30% of the thickness of the cobalt / nickel double-layer metal silicide 19, and preferably 5%. Compared with the single-layer titanium, cobalt, and nickel metal silicides of the conventional technology, the starting / nickel double-layer metal petrochemicals of the present invention, due to the tempering temperature of less than 700 ° C, are located in the upper layer of cobalt metal. The silicified thin layer will not be agglomerated. At the same time, it can protect the nickel metal silicide layer from being damaged by the fluorine-containing plasma, and the overall sheet resistance value of the initial / nickel double-layer metal lithoxide will not increase too much. also

200428533 V. Description of the invention (8) That is, ‘keep a low contact resistance. In addition, the nickel-metal oxide matte layer in the lower layer, as described in the conventional technology, can avoid the phenomenon of the chip limit rising caused by the narrow line width effect. Second Embodiment A method for forming a semiconductor device having a self-aligned metal silicide double-layered structure according to a second embodiment of the present invention is described below with reference to FIGS. 2a to 2d.

First, please refer to FIG. 2a to provide a silicon substrate 20, such as a stone evening sphere. It has an active area and an isolation structure 28, such as a shallow trench isolation structure, surrounding the active area. The active region has a semiconductor element, such as a MOS transistor, which includes a source region 21, a drain region 23, and a gate structure. Here, the gate structure includes a gate dielectric layer 2 2, a gate 24, and a gate spacer 26. Among them, the line width of the gate electrode 24 may be less than 65 nm.

Next, please refer to Fig. 2b. Using conventional deposition techniques, such as physical vapor deposition, pD, or chemical vapor deposition (CVD), the isolation region 28 and the source region 2 of the active region 2 1. A nickel metal layer 30 and a cobalt metal layer 32 are sequentially and compliantly deposited on the drain region 23 and the gate structure. In this embodiment, the nickel metal layer 30 is formed by chemical vapor deposition, and its thickness is in the range of 100 to 200 angstroms. Furthermore, the cobalt metal layer 32 is also formed by chemical vapor deposition, and its thickness is in the range of 50 to 200 angstroms. 〃 Next, please refer to FIG. 2c, perform a heat treatment on the silicon substrate 20 in FIG. 2b, for example, using a conventional tempering furnace tube method or rapid thermal tempering (RTA), so that the nickel metal layer 30 and a cobalt Recording & sub 32 of metal layer

200428533

Cobalt atoms diffuse into the source region 21, the drain region 23 of the active region, and the gate 24 of the gate structure to form a cobalt / nickel double-layer metal silicide 33 in the source region 21 and the drain region 23 and a gate A cobalt / nickel double-layer metal silicide 35 is formed on 24. Here, the cobalt / nickel double metal silicide 33 includes a nickel metal silicide layer 30b, which is located above the source region 21 and the non-electrode region 23, and a cobalt metal petrochemical layer 32b, which is located at the nickel metal chip. Above the chemical layer 30b. Similarly, the cobalt / nickel layer metal petrified material 35 includes a nickel metal silicide layer 30a above the source gate 24, and a cobalt metal silicide layer 32a above the nickel metal silicide layer 30a. Furthermore, a cobalt nickel silicide layer (not shown) is formed at the interface between the nickel metal silicide layers 30a and 30b and the cobalt metal silicide layers 32a and 3 2 b. In this way, the semiconductor device with a self-aligned metal silicide double-layer structure of the present invention is completed. In this embodiment, a rapid thermal tempering process is performed on the silicon substrate 20 to form cobalt / nickel double-layer metal silicides 33 and 35. The temperature of the rapid thermal tempering process is in the range of 350 ~ 550 C, and The time for rapid thermal tempering is in the range of 10 to 60 seconds. As described in the first embodiment, under this tempering condition, the sheet resistance of the cobalt metal silicide layer 18 is high, but no lumping phenomenon will occur. Then, the isolation structure 28 and the gate barrier wall 26 are selectively removed by plasma etching or a suitable solution to remove the non-lithified starting metal layer 32 and the nickel metal layer 30. In this embodiment, the lead metal layer 32 and the nickel metal layer 30 are removed using a mixed solution (spM) of sulfuric acid and hydrogen peroxide. Finally, please refer to Fig. 2d. On the silicon substrate 20 in Fig. 2c, a dielectric layer 3 6 is formed in a square shape. The material can be: siliconized plasma, low dielectric constant spin.

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200428533 V. Description of invention (ίο) Coated glass (S0G), tetraethoxy stone eve glass (T EOS oxide), doped silicon oxide, fluorine silicon glass (FSG), phosphorous silicon glass (PSG), high-density electricity Undoped silica glass (HDP-USG) deposited by the slurry, silicon oxide (HDP-Si02) deposited by high-density plasma, silicon oxide deposited by sub-pressure chemical vapor deposition (SACVD), and ozone— Silica oxide deposited by tetraethoxysilane (〇3-TE0S). Next, by a conventional plasma etching process, a contact window 37 is formed in the dielectric layer 36 above the source region 21 and the drain region 23, and a contact window is formed in the dielectric layer 36 above the gate 24. 39 to expose cobalt / nickel double metal silicides 33 and 35.

If I is included in the plasma etching process, it is likely to be bonded to the nickel atoms in the nickel metal silicide layers 30a and 30b to increase the sheet resistance value and increase the contact resistance, as described earlier. Therefore, nickel metal petrochemical 30a and 30b drilled metal petrochemical layers 32 "32b can be used as a protective layer to avoid increasing the contact resistance. Similarly, the first implementation of your metal layer 33 and 35 The piece = drop: the overall inscription, nickel double and 32b; lower, the cobalt metal silicide layers 32a and 32b have a cobalt / nickel double metal silicide i9 5% ~ 30%, which is better 15%. Please refer to FIG. 2c, which shows a semiconductor device with a metal silicide double-layered structure. The device of the second embodiment includes a silicon substrate 20 and a cobalt / nickel double two: Intent. This semiconductor silicon substrate, such as a silicon wafer, has one of the following: silicides 3 3 and 35. Isolation structure 28, such as a shallow trench, a junction, a region, and a body element surrounding the active region, such as a MOS Transistor, half-conductance in the moving region of the human being ~~ 3 source area 21, a drain

200428533 V. Description of the Invention (π) Region 23 and a gate structure. Here, the gate structure includes a gate dielectric layer 22, a gate 24, and a gate spacer 26. Cobalt / nickel double-layer metal silicides 35 and 33 are disposed on the gate 24 and the source region 21 / drain region 23, respectively. Among them, nickel metal silicide layers 30b and 30a are located above gate 24 and source region 21 / drain region 23, respectively, and cobalt metal silicide layers 32b and 32a are located above nickel metal silicide layers 30b and 30a, respectively. Here, the thickness of the cobalt metal silicide layers 3_2b and 32a are 5 ° / 0 to 30%, and preferably 15%, of the thickness of the cobalt / nickel double metal silicides 33 and 35, respectively. As described in the first embodiment, in the cobalt / nickel double-layer metal silicide of the present invention, the thin layer of the cobalt metal silicide layer located on the upper layer will not be agglomerated. At the same time, it can protect the nickel metal silicide layer from being damaged by the fluorine-containing plasma and keep a low contact resistance. Furthermore, the thick layer of nickel metal silicide in the lower layer can avoid the rise of the sheet resistance caused by the narrow line width effect. Therefore, it can be applied to the process of very small line width. 'Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make changes and retouching without departing from the spirit and scope of the present invention. The scope of protection of the invention shall be determined by the scope of the attached patent application.

200428533

Figures 1a to 1b show the process for forming a metal silicided double-layered structure on the basis of the present invention ^ Examples are based on silicon. Figures 2a to 2d show the 'not = figure' according to the present invention. Semiconducting device with self-aligned metal fossilized double-layered structure: its intention is being formed. Symbol description of the flow cross section of the spear feeding device: 10, 20 to silicon substrate; 12, 30 to nickel metal layer; 14, 32 to initial metal layer; 16, 30a, 30b to nickel metal silicide layer; 18, 32a, 32b ~ cobalt metal silicide layer; 19, 33, 3 5 ~ cobalt / nickel double metal silicide; 21 ~ source region; 2 ~ gate dielectric layer; 2 ~ non-electrode region; 24 ~ gate; 2 6 to the gate gap; 2 8 to the isolation structure; 36 to the dielectric layer; 37 and 39 to the contact window.

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Claims (1)

200428533 VI. Scope of patent application 1 · A metal shredded double-layer structure, including a silicon substrate; and a start / nickel double metal silicide, which is disposed on the silicon substrate, wherein the start / nickel double metal The silicide comprises a nickel metal silicide layer, which is located above the Shixi substrate, and a cobalt metal silicide layer, which is located above the nickel metal silicide layer. The metal silicide double-layer structure according to item 1 of the patent application scope, wherein The thickness of the cobalt metal silicide layer is 5% to 30% of the thickness of the cobalt / nickel double metal silicide. 3. The metal silicide double-layer structure as described in item 1 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 15% of the thickness of the cobalt / nickel double metal silicide. 4. The metal silicided double-layered structure as described in item 丨 of the patent application scope, wherein the nickel / nickel double-layer metal lithoxide is subjected to a heat treatment at the same time as the nickel / cobalt double-layered metal on the stone-based substrate. form. 5. The metal petrified double layer structure as described in item 4 of the Shengu patent scope, wherein the thickness of the nickel metal layer is in the range of 100 to 200 Angstroms. The metallized double-layered structure described in item 4 of the I Λ Lee range, wherein the thickness of the Yuanshi metal layer is in the range of 50 to 200 Angstroms. 7. The metal silicided double-layer structure as described in item 4 of the scope of patent application, where the heat treatment temperature is in the range of 350 ~ 550 ° C. 8. The metal silicided double-layer structure as described in item 4 of the scope of the patent application, wherein the heat treatment time is in the range of 10 to 60 seconds. 9 · A method for forming a metal silicided double-layer structure, including the following steps 0503-9975TWF (Nl); TSMC2003-0015; Spin.ptd 200428533 6. Scope of patent application: Provide a silicon substrate; sequentially and compliantly deposit a nickel metal layer and a starting metal layer on the stone substrate; and A heat treatment is performed on the silicon substrate to form a cobalt / nickel double metal silicide on the silicon substrate. I 0 · The method for forming a metal silicided double-layer structure as described in item 9 of the scope of the patent application, wherein the thickness of the nickel metal layer is in the range of 100 to 200 angstroms. II. The method for forming a metal silicide double-layer structure as described in item 9 of the scope of the patent application, wherein the thickness of the cobalt metal layer is in a range of 50 to 200 angstroms. 1 2 The method for forming a metal silicided double-layer structure as described in item 9 of the scope of the patent application, wherein the heat treatment is a rapid thermal tempering treatment. 1 3 · The method for forming a metal silicided double-layered structure as described in item 12 of the scope of the patent application, wherein the temperature of the rapid thermal tempering process is in the range of 35 to 5500 c. 14. The method for forming a metal silicided double-layered structure as described in item 12 of the scope of the patent application, wherein the time of the rapid thermal tempering treatment is in the range of 10 to 60 seconds. 15 · The method for forming a metal silicide double-layer structure as described in item 9 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 5% to 30% of the thickness of the cobalt / nickel double metal silicide. 16. The method for forming a metal silicide double-layer structure as described in item 9 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 15 ° / 0 of the thickness of the cobalt / nickel double metal silicide. 0503-9975TWF (Nl); TSMC2003-0015; Spin.ptd Page 19 200428533 6. Scope of patent application i. A semiconductor device with a metal silicide double-layer structure, including a stone substrate with a gate and a source / drain region; and a start / nickel double-layer metal silicide, Disposed on the gate and the source / inverted region, wherein the cobalt / nickel double-layer metal silicide includes a nickel metal petrified layer 'located over the gate and the source / drain region, and- A metal silicide layer is located above the nickel metal silicide layer. 18 · The semiconductor device having a metal silicide double-layer structure as described in item 17 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is equal to the thickness of the cobalt / nickel double-layer metal fossil compound. 19 · The semiconductor device having a metal silicide double-layer structure as described in item 17 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 15% of the thickness of the cobalt / nickel double metal lithoxide. 2 〇 The semiconductor device having a metal silicide double-layer structure as described in item 1 γ of the scope of the patent application, wherein the cobalt / nickel double-layer metal silicide is obtained by simultaneously applying the nickel / cobalt double-layer metal on the silicon substrate. 0 21 formed by performing a heat treatment. The semiconductor device having a metal silicide double-layer structure as described in item 20 of the patent application scope, wherein the thickness of the nickel metal layer is in the range of 100 to 200 angstroms. 2 2 · The semiconductor device having a metal silicide double-layered structure as described in item 20 of the scope of patent application, wherein the thickness of the cobalt metal layer is in a range of 50 to 2000 angstroms. 2 3 · As described in item 20 of the scope of patent application, the company has a double layer of metallization. 0503-9975TW (Nl); TSMC2003.0015; Spin.ptd 200428533 Structured semiconductor device, in which the temperature of the plutonium treatment is in the range of 350 to 55 ° C. "2 4 · As described in item 20 of the patent application scope, a semiconductor device having a metallized double-layer structure, wherein The time for the treatment is in the range of 10 to 60 seconds. ",, .25 · A method for forming a semiconductor device having a metal silicide double-layer structure includes the following steps: A silicon substrate is provided, which has a Gate and a source / drain region; A nickel metal layer and a cobalt metal layer are sequentially and compliantly deposited on the silicon substrate; and a heat treatment is performed on the stone substrate to form a cobalt / nickel on the gate and the source / non-electrode regions. Double metal silicide. 26. The method for forming a semiconductor device having a metal silicided double-layer structure as described in item 25 of the scope of the patent application, further comprising removing the non-silicided starting metal layer and the nickel metal layer. 27. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 26 of the scope of the patent application, wherein the cobalt metal layer and the nickel metal layer are removed by a sulfuric acid and hydrogen peroxide mixed liquid (SPM). 28. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the far nickel metal layer is in the range of 100 to 200 angstroms. 29. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the starting metal layer is in a range of 50 to 200 angstroms. 200428533 VI. Scope of patent application 30. The method for forming a semiconductor device with a metal silicide double-layer structure as described in item 25 of the patent application scope, wherein the heat treatment is a rapid thermal tempering process. ′, ^ 3 1 · The method for forming a semiconductor device having a metal silicided double-layer structure as described in item 30 of the scope of the patent application, wherein the temperature of the rapid thermal tempering process is in the range of 350 to 550 ° C. 32. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 30 of the scope of the patent application, wherein the time of the rapid thermal tempering treatment is in the range of 10 to 60 seconds. ’ 33. The method for forming a semiconductor device having a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the starting metallization layer is 5 times the thickness of the cobalt / nickel double-layer metal silicide. % ~ 30%. 3 4 · The method for forming a semiconductor device with a metal silicide double-layer structure as described in item 25 of the scope of the patent application, wherein the thickness of the cobalt metal silicide layer is 1 5 of the thickness of the cobalt / nickel double metal silicide %. 〇503-9975TWF (Nl); TSMC2003-0015; Spin.ptd Page 22