200426910 玖、發明說明（1 ) 【發明所屬之技術領域】 本發明是有關於一種積體電路製程之曝光方法，特別 是指一種能精確定位光罩，以減少曝光後線路圖像誤差之 不同層次的曝光方法。 【先前技術】 微影製程（photolithography)是半導體製程中最 重要的步驟之一，凡是與M〇s結構相關的，例如各層薄膜 之圖像（pattern)、摻雜區域（d〇pants)等等，均是由 此製程決定。而，微影製程的技術層次，一般不但由所需 使用光罩（mask)數量所決定，且由於光罩使用數量愈多 ，即代表需定位光罩的次數愈多，而愈可能造成定位校正 誤差，進而影響元件的積集度（integration)，因此，如 何減 > 定位光罩之定位誤差，以提昇圖像的對準度，是業 界提升微影製程良率的努力方向之一。 15 x asml的微影曝光機為例，參閱第一圖，目前應 用於微影製程之光罩丨包含多數個相同之線路圖像… 及多數分設於四周角落的米字形粗定位記冑12，田字形 對準"己號14 (―般所使㈣光罩與®示相同，且有六個 :::隔之線路圖像，本例亦以六個圖像為例說明)，該 :广象11間一般鍍覆一層厚度約數百A的鉻膜形成 、光區13,避免曝光時線路圖像間的相互干擾。、 是先目前半導體業界所習用的微影製程2, i安置I 2!將上料❹數相騎路圖像η之光罩 、微影機台中，並配合機台與光罩i預設之定 20 玖、發明說明（2 ) 位方式，將光軍1之米字形定位記號12與機台之相對定 己5虎（圖未不出）彼此相配合，以相對定位該光罩1與 該微影機台。 、#、乂驟22將多數晶圓分別安置入該微影機台中 ’並分=依序相収位其中之—晶圓與該微影機台。 接著進仃步驟23 ’將光罩1上之線路圖像1卜曝光 至該晶圓上預覆的光阻層上，形成潛在圖像（iatent);再 以步驟24,將該些曝光後已具有潛在圖像的晶圓退出微 影機台；接著進行步驟25進行業界習知的顯影、清洗、 硬烤、去光阻、或摻雜（其他預定金屬）…等過程，形成 相對應於該線路，象11的-積體電路層；然後，視需要 依序重複進行步驟21 i 25 ’最後，即可以步驟％於該 些晶圓上分別形成複數積體電路層，完成具有複數積體電 路層之晶圓的製備。 熟悉微影製程人士皆知，由於每一晶圓傳送至微影 機台内’再相對微影機台定位時，其可能產生之定位誤差 係由機械移動以及相對於光罩定位所產生，因此，光罩丨 相對機台定位實為微影製程曝光時誤差來源最主要之一因 素。 由於量產成本所需，光罩1上之多數線路圖像11均 為形成同-積體電路層所設計，而可同時應用該些圖像 11於同-晶圓多處同時曝光形成潛在圖像，以大幅減少 Ί耗費時間’ 省生產成本；因此’曝光形成晶圓上一 預定積體電路層，即必需使用至少一光罩（若考量積體電 7 200426910 玖、發明說明（3 ) 路之複雜度，也有使用複數光罩多次曝光形成一層積體電 路），而使用一片光罩，則必須相對定位光罩與微影機台 一次；以目前元件的積集度而言，一般晶圓必須形成至少 六層以上之積體電路層，也就是說，必須相對定位光罩與 5 微影機台至少六次以上，而累計形成不可控之對準誤差， 直接影響晶圓積集度與良率。 再者，由於光罩的製造成本極為高昂，因此，目前 晶圓代工廠均僅進行大批量量產生產，藉由大量生產具有 相同元件之晶圓分攤光罩成本，以取得商業利潤。而對一 10 般資金並不雄厚的設計公司（design house )而言，由於 其製造元件之目的一般為實驗其設計之積體電路的優劣與 否，以及量產上市的可行性評估，所以其所需製造晶圓均 以小批量、多樣性為主，因此，現行必須使用多數光罩的 大批量生產方式並無法適用；同時，在微影製程中定位光 15 罩與微影機台的累計定位誤差，也會影響其實驗生產之精 確度，而更加難以評估其所實驗之積體電路的優劣。 因此，如何改進製程，使其適用於生產小批量多樣 性晶圓，而能符合更多業者的需求，是半導體製程研究改 進的另一方向。 20【發明内容】 因此，本發明之首要目的，即在提供一種多層次的曝 光方法，以減少微影製程中光罩與微影機台之定位誤差。 此外，本發明之另一目的，在提供一種可以減少使用 光罩數目、降低光罩成本，而適用於生產小批量多樣性晶 200426910 玖、發明說明（4 ) 圓的不同層次的曝光方法。 於是，本發明一種不同層次的曝光方法，以一微影機台 對一晶圓進行多層次曝光，使該晶圓具有複數積體電路層。 首先以步驟（A)將一具有複數相異線路圖像之光罩定位 5 於該微影機台上；接著以步驟（B)將該晶圓定位於該微影機 台上；再進行步驟（C)將該光罩其中之一線路圖像對應成形 出該晶圓其中之一積體電路層；最後以步驟（D)將該晶圓重 新定位於該微影機台上，及/或是定位另一晶圓，進而將該 光罩其中另一線路圖像對應成形出該晶圓其中之另一積體電 10 路層。 【實施方式】 本發明之前述以及其他技術内容、特點與功效，在以 下配合參考圖式之一較佳實施例的詳細說明中，將可清楚 的明白。 15 本發明不同層次的曝光方法3，適用製造小批量多數 晶圓，並以一微影機台對晶圓進行多層次曝光，該每一晶 圓分別具有複數積體電路層，本例將以形成六層積體電路 層為例說明。 參閱第三圖，本發明所使用之光罩4可為二元光罩， 20 或相轉移光罩，包含六不同之線路圖像41、42、43、44 、45、46，及多數分設於四周角落的十字形或是米字形定 位記號47 (圖示中以米字形為例說明），該每一線路圖像 41、42、43、44、45、46是針對每一層積體電路而設計 ，且該等線路圖像41、42、43、44、45、46間亦鍍覆一 200426910 玖、發明說明（5 ) 層厚度約數百A的鉻膜形成非透光區48，避免曝光時線 路圖像間的相互干擾。 參閱第四圖，本發明不同層次的曝光方法3，先以步 驟31將上述具有六不同線路圖像41、42、43、44、铛、 10 46之光罩4，安置於一微影機台中，例如現在業界習用的 ASML、Nikon等廠牌的步進/掃描式微影機台，並配合機 台與光罩4預設之定位方式，將光罩4之米字形（或十字 形）定位記號47與機台之相對定位記號（圖未示出）彼此 相配合，以相對定位該光罩4與該微影機台；接著以步驟 32將多數晶圓分別安置入該微影機台中，並分別依序相 對移動其中-預定曝光之晶圓與該微影機台相對定位。 15 20 接著進行步驟33，將光罩4上之線路圖像41，曝井 至該晶圓上預覆的一光阻層上，形成第一潛在圖像；再以 步驟34,將該些曝錢已具有第—潛在圖像的晶圓退出 微影機台；接著以步驟35’進行業界習知的顯影、清洗 、烘烤、參雜或是始刻（不同預定金屬），再進行去光阻 (通常是以㈣方式除去預定無用之光阻）·.等過程 成相對應於該線路圖像41之第—層積趙電路，由於步驟 35中顯影、清洗、供烤、去光阻、參雜...等過程，以為 業界所熟知，且非本發明重點所在，故在此不多加·、、、 然後，重複進行步驟32、步驟33、步驟Μ，及_ 5 ’將4些晶圓再:欠傳送人該微影機台巾’ 定位一晶圓與該微影機台後，再依序將已 位之光罩4上的其他多數線路圖像42、43、441 = 10 200426910 玖、發明說明（ά ) ，分別曝光形成第二、三…、六潛在圖像，再分別成形出 相對應之第二、三…、六層積體電路層，最後，則如步驟 36，完成該些具有六層積體電路層之晶圓的製備。 參閱下列第一表可知，本發明不同層次的曝光方法3 5 所製備完成之晶圓，其第二層積體電路（即表中的PL1) 之X方向最大重疊誤差（overlay error)為12nm，y方向 最大重疊誤差為3 lnm，第三層積體電路（即表中的PL4 )之X方向最大重疊誤差為25nm，y方向最大重疊誤差 則為10nm;而較習知需更換6光罩，定位六次光罩與微 10 影機台之製程，其第二層積體電路（即表中的PL1)之X 方向最大重疊誤差為53nm，y方向最大重疊誤差為42nm ，第三層積體電路（即表中的PL4)之X方向最大重疊誤 差為43nm，y方向最大重疊誤差為28nm，顯然，本發明 不同層次的曝光方法3,在微影製程中最重要的曝光圖像 15 準確度上，較習知之微影製程2具有大幅度改善。 第一表 \ 本發明製程 習知製程 X方向 最大重疊誤差 y方向 最大重疊誤差 X方向 最大重疊誤差 y方向 最大重疊誤差 第二層積體電路 (PL1) 12 nm 31 nm 53 nm 42 nm 第三層積體電路 (PL4) 25 nm 10 nm 43 nm 28 nm 200426910 玖、發明說明（7 ) 由於，本發明不同層次的曝光方法3，將多數層積體 電路之線路圖像41、42、43、44、45、46，形成於單一 光罩4中，因此，僅需以步驟3 i對應相同光罩4與微影 機口即可重複曝光完成六層線路圖像41、42、43、44 5 、45、46，因此可將人工定位光罩4與微影機台的誤差降 至最低；同時，由於線路圖像41、42、43、44、45、铛 均不相同，因此雖然曝光時間較使用具有多數相同線路圖 像11之光罩1增加，但是當生產小批量之多數晶圓時， 時間成本差異不大，因而對IC設計公司（design h〇use) 1〇 而言，由於其製造元件之目的僅為實驗其設計之積體電路 之優劣與否，以及量產上市的可行性評估，所需製造晶圓 之數量一般均極少量，故本發明不同層次的曝光方法3不 但可以最低的人工定位誤差，增進其實驗生產之精確度， 同時可以減少其所使用光罩的數目，減少投資金額，以生 15產六層積體電路之晶圓而言，應用本發明之製程的成本約 僅需400萬台幣，較習知必須使用六光罩之傳統製程的 9〇〇萬成本預算而吕，大幅節省5〇〇萬元以上的投資成本 〇 此外’熟悉半導體製程人士由上述說明可輕易得知， 20 凡應用 TTL Alignment (Through The Lens)定位光罩的 微影機台，均可簡單應用本發明不同層次的曝光方法3， 而可大幅降低使用光罩數目，減少定位誤差，而不限於步 進/掃描式微影機台，其他例如應用接觸式（contact)、近 接式（proximity)曝光的微影機台，同樣地也可以應用本 12 200426910 玖、發明說明（8 ) 發明。 5 10 層；也可以於光罩4定位後 圖案 41、42、43、44、45、 再者’要特別說明的是，由於本發明所使用之光罩4 上的線路圖像41、42、43、44、45、46均不相同，因此 ，可預先設計該些線路圖像41、42、43、44、45、46， 應用其中多數線路圖像41、42、43、44、45、46共同分 別曝光於晶圓之m阻層後，相對應地形成晶圓其中 -層的積體電路層，以更高的良率形成更複雜的積體電路 ，同時應用光罩上多數個顯像 46同時曝光於晶圓各預定區 域’而在晶圓上之各該區域，製成功能構造各異之多數晶 片，以於單-晶圓上合併製造出更多種設計之元件，以符 合生產效益。 綜上所述，由於半導體產業是一資金高度密集的產業 ，因此，其所有製程的研究改進，均依照量產化發展，期 15以大批量生產以降低生產成本，取得商業利潤，也因此， 對一般資金並不雄厚的設計公司而言，對現行動輒必須以 多數光罩進行之微影製程2,實在是一沉重的負擔，而本 發明不同層次的曝光方法3，將多數層積體電路層之線路 圖像，形成於單一光罩4中，而僅以一次相對定位光罩與 20 微影機台或是對應相同光罩對準記號，即可重複轉移多數 層線路圖像，而相對應成形出複數層積體電路層，不但可 將定位光罩與微影機台的誤差降至最低，同時也可縮減使 用光罩的數量’而可大幅降低生產成本，特別適用於小批 量晶圓的生產製程，而碟實達到本發明之目的。 13 200426910 玖、發明說明（9 ) 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 範圍及發明說明書内容所作之簡單的等效變化與修飾，皆 應仍屬本發明專利涵蓋之範圍内。 5【圖式簡單說明】 第一圖是一示意圖，說明一具有多數相同線路圖像之 光罩； 第二圖是一流程圖，說明習知之微影製程； 鲁 第三圖是-示意圖’說明應用於本發明不同層次的曝 10 光方法之具有多數不同線路圖像之光罩；及 第四圖是-流程圖，說明本發明不同層次的曝光方法 〇 第-表是-實驗結果’說明本發明不同層次的曝光方 法與習知之微影製程’在形成各層積體電路後，於x及y 15 方向所量測之最大重疊誤差。 14 200426910 玖、發明說明（10 ) 【圖式之主要元件代表符號簡單說明】 1 光罩 32 步驟 11 線路圖像 33 步驟 12 米字形定位記號 34 步驟 13 非透光區 35 步驟 14 田字形對準記號 4 光罩 2 微影製程 41 線路圖像 21 步驟 42 線路圖像 22 步驟 43 線路圖像 23 步驟 44 線路圖像 24 步驟 45 線路圖像 25 步驟 46 線路圖像 26 步驟 47 米字形定位記號 3 不同層次的曝光方法 48 非透光區 31 步驟200426910 发明. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to an exposure method for an integrated circuit manufacturing process, and particularly to a different level capable of accurately positioning a photomask to reduce the line image error after exposure. Exposure method. [Previous technology] Photolithography is one of the most important steps in the semiconductor process, and it is generally related to the MOS structure, such as the pattern of various layers of films, doped regions, etc. , Are determined by this process. However, the technical level of the lithography process is generally not only determined by the number of masks required, but because the more the number of masks used, the more times the mask needs to be positioned, the more likely it is to cause positioning correction. Error, which in turn affects the integration of the component. Therefore, how to reduce the positioning error of the positioning mask to improve the alignment of the image is one of the industry's efforts to improve the lithographic process yield. 15 x asml lithography exposure machine is taken as an example. Refer to the first picture, the reticle currently used in the lithography process 丨 contains most of the same line images ... and most of the m-shaped rough positioning notes set at the corners around the corner 胄 12 , Tian-shaped alignment " Self-number 14 (the general mask is the same as ®, and there are six ::: separated line images, this example also uses six images as an example), the : The 11 wide areas are usually plated with a chromium film with a thickness of several hundred A, and the light area 13 is used to avoid mutual interference between the line images during exposure. First, is the lithography process 2, which is currently used in the semiconductor industry, and I is set to I 2! The material and the lithography machine η, which are loaded with the digital phase riding road image η, are preset in cooperation with the machine and the photomask i. Positioning 20 玖, description of the invention (2) position method, matching the m-shaped positioning mark 12 of the light army 1 and the relative positioning 5 tiger (not shown in the figure) of the machine to match the positioning of the photomask 1 and the relative Lithography machine. , #, Step 22 will place most of the wafers into the lithography machine separately ′ and divide = one of the sequential order-wafer and the lithography machine. Then proceed to step 23 'to expose the line image 1 on the photomask 1 to the photoresist layer overlaid on the wafer to form a latent image. Then, in step 24, the exposed images have been exposed. The wafer with the potential image exits the lithography machine; then, step 25 is performed to perform development, cleaning, hard baking, photoresist removal, or doping (other predetermined metals), etc., which are well known in the industry, and form a corresponding process. Circuits, like the 11-integrated circuit layer; then, repeat steps 21 i 25 'in sequence as needed. Finally, you can form a complex integrated circuit layer on these wafers, and complete the circuit with a complex integrated circuit. Preparation of layered wafers. Those who are familiar with the lithography process know that since each wafer is transferred to the lithography machine and then positioned relative to the lithography machine, the positioning error that may occur is caused by mechanical movement and positioning relative to the photomask, so The relative positioning of the photomask and the machine is one of the most important sources of error in the exposure of the lithography process. Due to the cost of mass production, most of the circuit images 11 on the reticle 1 are designed to form homo-integrated circuit layers, and these images 11 can be applied at the same time to expose potential images on multiple wafers at the same time. Image, to greatly reduce the time consuming 'to save production costs; therefore,' exposed to form a predetermined integrated circuit layer on the wafer, it is necessary to use at least one photomask (if considering integrated circuit 7 200426910 玖, invention description (3)) The complexity is also the use of multiple photomasks to form a layer of integrated circuit for multiple exposures). When using a photomask, the photomask and the lithography machine must be positioned relative to each other; in terms of the current component accumulation, the general crystal The circle must form at least six integrated circuit layers, that is, the photomask and the 5 lithography machine must be positioned at least six times relative to each other, and an uncontrollable alignment error is accumulated, which directly affects the degree of wafer accumulation With yield. Furthermore, because the manufacturing cost of photomasks is extremely high, at present wafer foundries are only producing in large quantities, and the cost of photomasks is shared by mass production of wafers with the same components in order to obtain commercial profits. For a design house with a low general capital (design house), the purpose of manufacturing components is generally to test the advantages and disadvantages of the integrated circuit it designs and the feasibility evaluation of mass production and listing. The required manufacturing wafers are mainly small batches and diversity. Therefore, the current mass production method that must use most photomasks is not applicable; at the same time, the accumulation of positioning 15 masks and photolithography machines in the lithography process is not applicable. The positioning error will also affect the accuracy of its experimental production, and it will be more difficult to evaluate the advantages and disadvantages of the integrated circuit it is experimenting with. Therefore, how to improve the process so that it is suitable for the production of small batches of diverse wafers and can meet the needs of more manufacturers is another direction for the improvement of semiconductor process research. [Summary of the Invention] Therefore, the primary object of the present invention is to provide a multi-level exposure method to reduce the positioning error between the reticle and the lithography machine during the lithography process. In addition, another object of the present invention is to provide an exposure method that can reduce the number of photomasks and reduce the cost of the photomask, and is suitable for producing small batches of multi-layered crystals. Therefore, in the present invention, a different-level exposure method uses a lithography machine to perform multi-level exposure on a wafer, so that the wafer has a plurality of integrated circuit layers. First, step (A) is used to position a mask with a plurality of distinct line images on the lithography machine; then, step (B) is used to position the wafer on the lithography machine; (C) forming one of the integrated circuit layers of the wafer corresponding to one of the circuit images of the photomask; and finally repositioning the wafer on the lithography machine in step (D), and / or It is positioning another wafer, and then forming another integrated circuit layer of the wafer corresponding to the other circuit image in the photomask. [Embodiment] The foregoing and other technical contents, features, and effects of the present invention will be clearly understood in the following detailed description of a preferred embodiment with reference to the accompanying drawings. 15 The exposure method 3 at different levels of the present invention is suitable for manufacturing a large number of wafers in small batches, and the wafers are exposed at multiple levels using a lithography machine. Each wafer has a plurality of integrated circuit layers. This example will use The formation of a six-layer integrated circuit layer is taken as an example. Referring to the third figure, the photomask 4 used in the present invention may be a binary photomask, 20 or a phase transfer photomask, which includes six different line images 41, 42, 43, 44, 45, 46, and a plurality of sub-images. The cross-shaped or m-shaped positioning marks 47 at the corners of the four sides (the m-shaped is used as an example in the illustration), each line image 41, 42, 43, 44, 45, 46 is for each layer of the integrated circuit. Design, and these line images 41, 42, 43, 44, 45, 46 are also plated with a 200426910 玖, the description of the invention (5) a layer of chromium film with a thickness of about several hundred A to form a non-transmissive area 48 to avoid exposure The mutual interference between the line images. Referring to the fourth figure, the exposure method 3 of different levels of the present invention, firstly, in step 31, the photomask 4 having the six different line images 41, 42, 43, 44, clams, and 10 46 is placed in a lithography machine. For example, the stepping / scanning lithography machine of brands such as ASML and Nikon, which are customary in the industry, and the preset positioning method of the machine and the reticle 4, the m-shaped (or cross) positioning mark of the reticle 4 The relative positioning marks (not shown) of 47 and the machine are matched with each other to relatively position the photomask 4 and the lithography machine; then, in step 32, most wafers are respectively placed in the lithography machine, and The wafers in which the predetermined exposure is moved relative to each other are sequentially positioned relative to the lithography machine. 15 20 Then proceed to step 33, which exposes the line image 41 on the photomask 4 to a photoresist layer preliminarily formed on the wafer to form a first latent image; then, in step 34, the exposed images are exposed. The wafer that Qian has the first potential image exits the lithography machine; then, step 35 'is used for developing, cleaning, baking, blending or engraving (different predetermined metals) that are well known in the industry, and then debuffing. Resistance (usually removing the intended useless photoresist in a rubidium manner) ... etc. The process corresponds to the first-layered Zhao circuit corresponding to the line image 41. Because of the development, cleaning, baking, photoresist removal in step 35, Including processes such as ..., which are well known in the industry, and are not the focus of the present invention, so do not add more ... here, and then repeat step 32, step 33, step M, and _ 5 ' Yuan Zai: After owing to the lithography machine's towel, after positioning a wafer and the lithography machine, it will sequentially place most of the other line images on the mask 4 in place 42, 43, 441 = 10 200426910玖, invention description (ά), respectively exposed to form the second, third ..., six latent images, and then form the corresponding The second, third ..., six-layer integrated circuit layers, and finally, according to step 36, the wafers having the six-layer integrated circuit layers are completed. It can be known from the following first table that the maximum overlap error in the X direction of the second layer integrated circuit (ie, PL1 in the table) of the wafer prepared by the exposure method 3 5 of the present invention at different levels is 12 nm. The maximum overlap error in the y-direction is 3 lnm. The maximum overlap error in the X-direction of the third layered circuit (ie, PL4 in the table) is 25nm, and the maximum overlap error in the y-direction is 10nm. The process of positioning the photomask and the Micro 10 camera six times. The maximum overlap error in the X-direction of the second layered circuit (PL1 in the table) is 53nm, and the maximum overlap error in the y-direction is 42nm. The maximum overlap error in the X direction of the circuit (ie, PL4 in the table) is 43nm and the maximum overlap error in the y direction is 28nm. Obviously, the exposure method 3 of different levels of the present invention is the most important exposure image in the lithography process. 15 Accuracy In comparison with the conventional lithography process 2, it has greatly improved. The first table \ The process of the present invention is known in the process. The maximum overlap error in the X direction and the maximum overlap error in the X direction. The maximum overlap error in the X direction and the maximum overlap error in the y direction. Second layer integrated circuit (PL1) 12 nm 31 nm 53 nm 42 nm Third layer Integrated circuit (PL4) 25 nm 10 nm 43 nm 28 nm 200426910 玖, description of the invention (7) Because of the exposure method 3 of the present invention at different levels, most of the circuit images 41, 42, 43, 44 of the multilayer integrated circuit , 45, 46 are formed in a single photomask 4, so you only need to repeat the exposure in step 3 i corresponding to the same photomask 4 and lithography port to complete the six-layer line image 41, 42, 43, 44 5 45, 46, so the error between the manual positioning mask 4 and the lithography machine can be minimized. At the same time, because the line images 41, 42, 43, 44, 45, and clang are different, although the exposure time is longer than The mask 1 with most of the same line images 11 is increased, but when producing most wafers in small batches, the time cost difference is not large, so for IC design company 10, due to its manufacturing components The purpose is only to test the integrated circuit it designed Pros and cons, and the feasibility evaluation of mass production and listing, the number of wafers required for manufacturing is generally very small, so the exposure method 3 at different levels of the present invention not only can minimize the manual positioning error and improve the accuracy of its experimental production, At the same time, the number of photomasks used can be reduced, and the investment amount is reduced. For a wafer with 15 layers of six-layer integrated circuits, the cost of applying the process of the present invention is only about 4 million Taiwan dollars. The traditional process of the photomask has a budget of 90 million yuan, which greatly saves more than 5 million yuan in investment costs. In addition, those who are familiar with the semiconductor process can easily know from the above description. 20 Where TTL Alignment (Through The Lens) is used ) The lithography machine for positioning the photomask can simply apply the exposure method 3 at different levels of the present invention, which can greatly reduce the number of photomasks used and reduce positioning errors, and is not limited to the step / scanning lithography machine. The lithography machine using contact and proximity exposure can also apply this 12 200426910 玖, invention description (8) invention . 5 10 layers; the patterns 41, 42, 43, 44, 45 can also be positioned after the reticle 4, and further 'specially, because the line images 41, 42, on the reticle 4 used in the present invention, 43, 44, 45, 46 are all different, so these line images 41, 42, 43, 44, 45, 46 can be designed in advance, and most of them are applied to the line images 41, 42, 43, 44, 45, 46 After being collectively exposed to the m-resistance layer of the wafer, the integrated circuit layers of the wafer's middle-layer are formed correspondingly, and more complex integrated circuits are formed with a higher yield. At the same time, most imaging on the photomask is applied. 46 at the same time exposed to each predetermined area of the wafer ', and in each of the areas on the wafer, a plurality of wafers with different functional structures are made to combine and manufacture more designed components on a single wafer to meet production benefit. To sum up, because the semiconductor industry is a highly capital-intensive industry, the research and improvement of all its processes has been developed in accordance with mass production. The period 15 is to produce in large quantities to reduce production costs and obtain commercial profits. For design companies that are not generally well-funded, the lithography process 2 that must be performed with most photomasks for current actions is a heavy burden, and the exposure method 3 at different levels of the present invention will most of the multilayer circuit The layer line images are formed in a single photomask 4. Only one relative positioning of the photomask and the 20 lithography machine or corresponding alignment marks on the same photomask can be used to repeatedly transfer the line image of most layers. Corresponding to the formation of multiple laminated circuit layers, not only can minimize the error between the positioning mask and the lithography machine, but also reduce the number of masks used, which can greatly reduce production costs, and is especially suitable for small batch crystals. Round production process, and the dish actually achieves the purpose of the present invention. 13 200426910 发明. Description of the invention (9) However, the above are only the preferred embodiments of the present invention. When this cannot be used to limit the scope of the present invention, that is, what is generally made in accordance with the scope of the patent application and the description of the invention The simple equivalent changes and modifications should still fall within the scope of the invention patent. 5 [Schematic description] The first diagram is a schematic diagram illustrating a photomask with most of the same line images; the second diagram is a flowchart illustrating the conventional lithographic process; the third diagram is-a schematic diagram ' A mask having a plurality of different line images applied to the method of exposing 10 light at different levels of the present invention; and the fourth figure is a flowchart illustrating the exposure method of the different levels of the present invention. Invented different levels of exposure methods and the conventional lithography process' after forming each layered circuit, the maximum overlap error measured in the x and y 15 directions. 14 200426910 发明. Description of the invention (10) [Simplified description of the main symbols of the drawings] 1 Photomask 32 Step 11 Line image 33 Step 12 M-shaped positioning mark 34 Step 13 Non-transparent area 35 Step 14 Field shape alignment Mark 4 Photomask 2 Lithography process 41 Line image 21 Step 42 Line image 22 Step 43 Line image 23 Step 44 Line image 24 Step 45 Line image 25 Step 46 Line image 26 Step 47 M-shaped positioning mark 3 Different levels of exposure method 48 non-light-transmitting area 31 steps