200422237 玖、發明說明： 【發明所屬之技術領域】 本發明係關於安裝I C或LS I等的電子元件用的電子元 件安裝用薄膜輸送帶。 【先前技術】 伴隨著電子產業的發達，安裝1C(積體電路）、LSI(大型 積體電路）等的電子元件的印刷電路板的需要急遽增加，但 也要求電子機器的小型化、輕量化及高功能化，而作為此 等電子元件的安裝方法，最近採用使用TAB帶、T-BGA帶、 ASIC帶等的電子元件安裝用薄膜輸送帶的安裝方式。尤其 是在使用如個人電腦、行動電話等之要求高精細化、薄型 化、液晶晝面的框緣面積狹小化的液晶顯示元件（L C D )的電 子產業中，其重要性增高。 另外，伴隨著電子機器的小型化等，也要求電子元件安 裝用薄膜輸送帶的薄型化，近年來，提出有使用膜厚較薄 的絕緣層的C 0 F ( C h i ρ 0 n F i 1 m )帶等的方案。 如此之電子元件安裝用薄膜輸送帶，係經由例如下述的 步驟所製造，該等步驟包括：在聚醯亞胺組成的絕緣層的 寬度方向兩側形成搬運用的鏈孔等的步驟；使用鏈孔邊搬 運絕緣層邊於絕緣層一面所設的銅箔上形成光阻塗佈層的 步驟；對光阻塗佈層進行曝光·顯影的步驟；將光阻塗佈 層予以圖案加工以形成遮罩圖案的步驟；透過遮罩圖案蝕 刻銅箔以形成配線圖案的步驟；及於各配線圖案上形成焊 料抗姓劑層的步驟。 6 312/發明說明書(補件)/93-06/93106942 200422237 然而，在如上述之C0F帶等的絕緣層的厚度較薄的型式 中，無法充分確保鏈孔的剛性，而有搬運時鏈孔變形的問 題產生。 在此，為解決該問題，提出在各鏈孔（Sprocket hole) 的周圍沿著電性絕緣性可撓性帶（絕緣層）的長度方向連續 設置補強層（金屬層），以確保帶搬運強度的構造的方案（例 如，參照專利文獻1 )。 又，在上述之電子元件安裝用薄膜輸送帶之製造步驟 中，尤其是在形成抗#劑層或焊料抗#劑層的各步驟或艘 錫步驟中，導入在未形成有配線圖案的區域具有壓紋的隔 層元件（壓紋隔層薄膜）並將薄膜輸送帶捲取於捲軸上進行 加熱的所謂的硬化（c u r i n g )步驟、或防止鬚晶（w h i s k e r ) 產生用的加熱步驟（例如，參照專利文獻2 )。 (專利文獻1 ) 曰本專利實開平4 - 4 8 6 2 9號公報（圖1〜圖3，新型登錄 申請專利範圍） (專利文獻2 ) 日本專利特開2 0 0 1 - 7 7 1 5 7號公報（段落[0 0 0 6 ]) 【發明内容】 (發明所欲解決之問題） 然而，在上述之設有補強層之電子元件安裝用薄膜輸送 帶中，在最終製品之電子元件安裝用薄膜輸送帶的寬度方 向兩側、亦即在存在有鏈孔的區域，產生有沿其長度方向 的高度為1〜2 in m左右的波狀變形的問題。 7 312/發明說明書(補件)/93-06/93106942 200422237 如此顯眼之波狀變形，在未設置補強層於鏈孔周 般的製品中並未發現，在硬化步驟或防止鬚晶產生 步驟中，在供給壓力於薄膜輸送帶的狀態產生金屬 緣層之間的材料物性值的差異，例如，線膨脹係數 強度、或伸長率等的差異，可以認為是在製造步驟 熱·冷卻等的處理等複雜地相互影響所產生。 此外，如此般波狀變形的電子元件安裝用薄膜輸 於半導體組裝線上，無法由針輥等順利地定位搬運 無法追蹤設於搬運通路的導引等，招致電子元件的 良等，而有最終形成製品不良的問題。 本發明係鑑於上述情況，其目的在於提供一種可 半導體安裝線上的搬運或安裝時的可靠度之平坦的 件安裝用薄膜輸送帶。 (解決問題之手段） 解決上述課題之本發明之第1態樣為一種電子元 用薄膜輸送帶，係於具有由導電層組成於絕緣層的 配線圖案、及設於該配線圖案兩側的複數鏈孔，且 鏈孔周圍設有金屬層的電子元件安裝用薄膜輸送帶 特徵為：上述金屬層實質上係沿上述絕緣層的長度 續而設，且上述鏈孔間的區域的上述金屬層寬度w! 係在將該鏈孔寬度設為w 2 [ m m ]時，滿足0 · 3 $ w 1 $ (v\ 的條件。 在上述之第1態樣中，藉由將金屬層之寬度w!設 量，適度開放金屬層與絕緣層之間產生的應力，以 312/發明說明書(補件)/93-06/93106942 圍的一 的加熱 層與絕 或拉伸 中的加 送帶， ，另外， 安裝不 提向在 電子元 件安裝 表面的 在上述 中，其 方向連 [mm]， 2+1,1) 為指定 減低產 8 200422237 生於電子元件安裝用薄膜輸送帶的波狀變形。藉此，可實 現平坦的電子元件安裝用薄膜輸送帶，並提高在半導體安 裝線上的搬運或安裝時的可靠度。 本發明之第2態樣，係於第1態樣之電子元件安裝用薄 膜輸送帶中，其特徵為：上述鏈孔存在之區域内的上述金 屬層的寬度W3[mm]，係滿足（W2 + 0.2)Sw3$ (W2 + 1.6)的 條件。 在上述之第2態樣中，適度開放絕緣層與金屬層之間產 生的應力，可有效減低產生於電子元件安裝用薄膜輸送帶 的波狀變形。 本發明之第3態樣，係於第2態樣之電子元件安裝用薄 膜輸送帶中，其特徵為：上述鏈孔所存在之區域内的上述 金屬層的寬度W3[mm]，係滿足（W2 + 0.2)$W3$ (W2 + 1.1) 的條件。 在上述之第3態樣中，適度開放絕緣層與金屬層之間產 生的應力，可有效減低產生於電子元件安裝用薄膜輸送帶 的波狀變形。 本發明之第4態樣，係於第1〜3中任一態樣之電子元 件安裝用薄膜輸送帶中，其特徵為：上述金屬層的寬度 wjmm]與上述鏈孔所存在的區域内的上述金屬層的寬度 w 3 [ m m ]，係滿足w 1 < w 3的關係。 在上述之第4態樣中，適度開放絕緣層與金屬層之間產 生的應力，可有效減低產生於電子元件安裝用薄膜輸送帶 的波狀變形。 9 312/發明說明書(補件)/93-06/93106942 200422237 本發明之第5態樣，係於第1〜4中任一態樣之電子元 件安裝用薄膜輸送帶中，其特徵為：上述金屬層係藉由設 置指定個數的上述每一鏈孔的縫隙，而於上述絕緣層之長 度方向不連續。 在上述之第5態樣中，適度開放絕緣層與金屬層之間產 生的應力，可有效減低產生於電子元件安裝用薄膜輸送帶 的波狀變形。 本發明之第6態樣，係於第1〜5中任一態樣之電子元 件安裝用薄膜輸送帶中，其特徵為：在上述金屬層與上述 鏈孔的開口緣部之間，設置未存在有金屬層的區域。 在上述之第6態樣中，因為在各鏈孔的開口周緣未設置 金屬層，因此，在製造或安裝時，不會產生插入各鏈孔的 針輥或定位銷等與金屬層接觸而形成短路的原因的金屬片 或金屬粉等。 【實施方式】 以下，參照實施形態詳細說明本發明。 (實施形態1 ) 圖1為顯示本發明之實施形態1的電子元件安裝用薄膜 輸送帶的概要圖，圖1 ( a )為俯視圖，圖1 ( b )為剖視圖，圖 1 ( c )為要部放大俯視圖。 如圖所示，本實施形態之電子元件安裝用薄膜輸送帶1 〇 係為C 0 F薄膜輸送帶，具有設於帶狀絕緣層1 1 一面側的由 導電層1 2組成的配線圖案1 3、及設於該配線圖案1 3的寬 度方向兩側的複數鏈孔1 4。 10 312/發明說明書(補件)/93-06/93106942 200422237 配線圖案1 3係連續設於絕緣層1 1的表面。又，如此之 配線圖案1 3之詳細說明容待後述，但其係在絕緣層1 1的 表面所設的導電層1 2上塗佈光阻後，經由曝光·顯影及蝕 刻而將導電層1 2予以圖案加工所形成。 另外，在配線圖案1 3上設有利用網版印刷塗佈焊料抗 姓劑材料塗佈溶液而形成的焊料抗姓劑層1 5。也就是說’ 在配線圖案1 3的中央部，係如圖1 ( a)所示，在安裝半導 體晶片的部分分別延設屬配線圖案1 3的一部分的内部導 線1 3 a。另一方面，在該内部導線1 3 a相反側的焊料抗蝕 劑層1 5之外側，延設屬配線圖案1 3的一部分的成為外部 連接用端子部的外部導線1 3 b。 在此，作為絕緣層的材料1 1，除了聚醯亞胺以外，可使 用例如聚酯、聚醯胺、聚醚硬、液晶聚合物等，而尤以可 使用由均苯四曱酸2酐與芳香族二胺合成的全芳香族聚醯 亞胺（例如，商品名：K a p t ο η ;東麗·杜邦（股）製）、具有 聯苯骨骼的全芳香族聚醯亞胺（例如，商品名：U Ρ I L Ε X ;宇 部興產（股）製）。如此之絕緣層1 1的厚度一般為1 2 . 5〜1 2 5 //m，較佳為12.5〜75#111，更佳為12.5〜50#m。 另一方面，作為導電層1 2的材料，除了銅之外，可使 用I呂、金、銀等，但一般為銅層。另外、，銅層可使用蒸鍵 或電鍍所形成的銅層、電解銅箔、軋製銅箔等之任一者。 導電層12的厚度一般為1〜70/im，較佳為5〜35//m。 另外，在鏈孔1 4的周圍設有在半導體安裝線上的定位 搬運中用以補強各鏈孔1 4的金屬層1 6。也就是說，金屬 11 312/發明說明書(補件)/93-06/93106942 200422237 層1 6係於絕緣層1 1的寬度方向兩側所設的複數鏈孔1 4 的周圍，與配線圖案1 3不連續且沿絕緣層1 1的長度方向 連續而設。於是，例如在本實施形態中，該金屬層1 6利用 將各導電層1 2予以圖案加工而與配線圖案1 3同時形成， 並作為確保各鏈孔1 4之強度用的虛設配線等使用。 在此，本發明中，處於各鏈孔1 4間的區域的金屬層1 6 的寬度w! [ m m ]，係在將該鏈孔1 4的寬度設為w 2時，滿足 0 · 3 S w 1 S ( w 2 + 1 · 1 )的條件，最好是滿足 0 · 5 S w 1 S ( w 2 + 1 · 0 )的條件（參照圖1 ( c))。例如，本實施形態中將金屬層 1 6的寬度w!設為2. 4 m m。在此，將金屬層的寬度最小值設 為0 . 3 m m，是為了確保各鏈孔1 4間的剛性，並獲得所需的 帶搬運強度。 另外，在本發明中，鏈孔14所存在之區域内的金屬層 1 6的寬度w 3 [ m m ]，係在將該鏈孔1 4的寬度設為w 2時，較 佳情況是滿足（w 2 + 0 . 2 ) S w 3 S ( w 2 + 1 · 6 )的條件，而尤佳 條件是滿足（w 2 + 0 · 2 ) S w 3 S ( w 2 + 1 · 1 )。例如，本實施形 態中，將處於各鏈孔14間的區域的金屬層16的寬度w!、 與處於存在有鏈孔14之區域内的金屬層16的寬度w3設為 相同寬度，亦即W 1 = W 3。在此，將金屬層1 6的寬度W 3的最 小值設為w 2 + 0 . 2 m m，是為了確保各鏈孔1 4的剛性，並 獲得所需的帶搬運強度。 又，關於各鏈孔14的寬度方向一側的金屬層16的寬度 與另一側的金屬層1 6的寬度的關係，最好為相同的寬度， 但當然也可為不相同的寬度。另外，金屬層1 6最好設於較 12 312/發明說明書(補件)/93-06/93106942 200422237 絕緣層1 1的寬度方向兩側端部的内側。這是為了防止在製 造或安裝時金屬層16接觸於搬運通路上所設的導引等而 產生金屬片或金屬粉等。 在此，關於鏈孔1 4的寬度w 2，係根據E I A J (日本電子機 械工業會）規格，分別規定其標準值為在帶（絕緣層11 )寬 為35111111、48111111為1.42±0.03111111，在帶寬為7〇111111為1.98± 0.03mm。關於該鏈孔1 4的間距則規定標準值為4. 7 5 土 0 . 0 5mm ° 如上述說明，本實施形態中，利用至少將處於各鏈孔1 4 間之區域内的金屬層1 6之寬度w!限定為指定量，在後述 之硬化步驟中，適度開放金屬層1 6與絕緣層1 1之間所產 生的應力，可減低產生於屬最終製品的電子元件安裝用薄 膜輸送帶1 0的寬度方向兩側的沿長度方向上所發生的波 狀變形。亦即，可實現平坦的電子元件安裝用薄膜輸送帶 10，提高在半導體安裝線上的可靠度。 另外，因為帶全體的剛性不會變得太大，因此即使在搬 運通路彎曲的情況，帶本身仍可自由追蹤搬運通路，可較 好地搬運。 又，如此般構成之電子元件安裝用薄膜輸送帶1 0，例 如，將相當於5〜1 0個量的半導體的大小且切割為條狀者 供給安裝裝置，而安裝半導體等的電子元件。此時，因為 在鏈孔1 4的周圍設有金屬層1 6，因此可確保鏈孔1 4的剛 性，可高精度安裝電子元件。 在此，參照圖2，說明上述之電子元件安裝用薄膜輸送 13 312/發明說明書(補件)/93-06/93106942 200422237 帶1 0的製造方法的一例。又，圖2為說明電子元件安裝用 薄膜輸送帶的製造方法的剖面圖。 本實施形態之製造方法中，在後述之各製造步驟後，雖 未圖示，將在未形成有配線圖案的區域具有凹凸部的壓紋 隔層薄膜與薄膜輸送帶（C0F積層薄膜）一起捲取於捲軸 上，並視需要導入加熱的硬化步驟。 首先，如圖2 ( a)所示，準備於絕緣層1 1上形成導電層 12的C0F用積層薄膜20。 其次，如圖2 ( b )所示，藉由沖壓（p u n c h i n g )等使絕緣層 1 1與導電層1 2貫穿而形成鏈孔1 4。該鏈孔1 4可形成於絕 緣層1 1的表面上，也可形成於絕緣層1 1的背面。 再者，如圖2 (c)所示，使用一般的光微影蝕刻法，沿導 電層1 2上形成有配線圖1 3的區域塗佈光阻材料塗佈溶 液，其後，以約6 0〜1 0 0 °C加熱硬化而形成光阻材料塗佈 層2 1。又，在鏈孔1 4内插入定位銷進行絕緣層1 1的位置 定位後，透過光罩2 2進行曝光·顯影，將光阻材料塗佈層 2 1予以圖案加工，形成如圖2 ( d )所示的配線圖案用抗蝕劑 圖案23。 接著，如圖2 ( d )所示，例如在本實施形態中使用轉印 法，將抗蝕劑材料塗佈溶液局部塗佈於對應鏈孔1 4的區 域，形成用以形成金屬層1 6的金屬層用抗蝕劑圖案2 4。 例如，在本實施形態中，將處於各鏈孔1 4間之區域内的金 屬層16的寬度Wi、與處於存在有鏈孔14之區域内的金屬 層1 6的寬度W 3設為相同寬度，亦即以W I = W 3的方式形成金 14 312/發明說明書(補件)/93-06/93106942 200422237 屬層用抗蝕劑圖案2 4。又，金屬層用抗蝕劑圖案2 4可於 形成配線圖案用抗蝕劑圖案2 3前形成，也可於形成鏈孔 1 4前利用轉印法另外形成。當然，也可同時形成配線圖案 用抗蝕劑圖案2 3及金屬層用抗蝕劑圖案2 4。 接著，將配線圖案用抗蝕劑圖案2 3及金屬層用抗蝕劑 圖案24作為遮罩圖案，由蝕刻液溶解除去導電層12，再 由鹼溶液等溶解除去配線圖案用抗蝕劑圖案2 3及金屬層 用抗蝕劑圖案2 4，形成如圖2 ( e )所示的配線圖案1 3與金 屬層1 6。 接著，如圖2 ( f )所示，在配線圖案1 3與金屬層1 6的表 面上形成鍍錫層（未圖示）後，中間夾入壓紋隔層而捲取於 捲軸上，進行約8 0〜2 0 0 °C的加熱處理。藉此，可防止鬍 晶的產生。接著，例如使用網版印刷法，形成焊料抗蝕劑 層1 5。例如，在本實施形態中，以包圍配線圖案1 3之中 央部的方式形成焊料抗蝕劑層1 5，於配線圖案1 3之中央 部形成内部導線1 3 a，於焊料抗蝕劑層1 5的外側形成外部 導線1 3 b。將此在中間夾入壓紋隔層而捲取於捲軸上，進 行約1 0 0〜2 0 0 °C的加熱硬化處理。藉此，完成圖1所示之 電子元件安裝用薄膜輸送帶10。 在如此之電子元件安裝用薄膜輸送帶1 0的各製程，尤 其是在形成各抗蝕劑圖案2 3、2 4的步驟、在形成焊料抗蝕 劑層1 5的步驟所導入的硬化步驟中，本實施形態中，利用 至少將處於各鏈孔1 4間之區域内的金屬層1 6之寬度w, 限制於指定量，便可適度開放絕緣層1 1與金屬層1 6之間 15 312/發明說明書(補件)/93-06/93106942 200422237 產生的内部應力。因此，藉由如此之應力，可減低於電子 元件安裝用薄膜輸送帶1 〇的寬度方向兩側的沿長度方向 上產生的波狀變形。亦即，可實現平坦的電子元件安裝用 薄膜輸送帶1 0。另外，藉由金屬層1 6可提高鏈孔1 4的剛 性，並可確保充分的帶搬運強度。因此，在安裝電子元件 等時，可於鏈孔1 4插入針輥等而輕鬆定位搬運，同時，可 追蹤設於搬運通路上的導引等，而可提高在半導體安裝線 上的搬運或安裝時的可靠度。 又，本實施形態中係如上述，沿絕緣層1 1的長度方向 以相同寬度連續設置金屬層1 6，但金屬層的形狀並不侷限 於此。以下，根據實施形態來例示金屬層的形狀。 (實施形態2 ) 圖3為本發明之實施形態2的電子元件安裝用薄膜輸送 帶的要部放大俯視圖。 如圖3 ( a )所示，金屬層1 6 A係以處於各鏈孔1 4間之金 屬層16A的寬度Wi[mm]較處於存在有鏈孔14的區域的金 屬層1 6 A的寬度w 3小，亦即，以w !< w 3的條件而設。 另外，如圖3 ( b)所示，金屬層1 6 B係於絕緣層1 1的長 度方向對應指定個數、例如3〜8個的鏈孔1 4群連續而設， 且此等鏈孔1 4群係透過縫隙1 7而不連續。 如此之金屬層1 6 B的長度方向的長度L [ m m ]，係相當於 鏈孑L 1 4的3〜8個量的約1 0〜4 0 m in，最好為相當於3〜6 個量的1 0〜3 0 m m。例如，本實施形態中，為相當於4個鏈 孔1 4的1 7〜1 9 m m。又，縫隙1 7的寬度並無特別的限定， 16 312/發明說明書(補件)/93-06/93106942 200422237 但最好為例如0 . 1〜2 . 0 m m左右。 又，如圖3 ( c )所示，金屬層1 6 C係於上述金屬 設有縫隙1 7。 如以上之說明，在本實施形態之電子元件安裝 送帶中，係欲將各金屬層16A、16B、16C的寬度 限制為指定量，因此充分開放絕緣層1 1與金屬J 產生的應力，可更為有效地減低電子元件安裝用 帶的波狀變形。 尤其是本實施形態中，盡可能小地限制處於鏈 之區域的金屬層1 6 A的寬度w!，亦即，盡可能小 各鏈孔1 4之補強無直接關連，但與薄膜輸送帶之 的金屬層16A的寬度w!，以確保各鏈孔14之補i 同時，可沿帶的長度方向調整各鏈孔1 4之周圍部 孔1 4之間的部分的金屬層1 6 A與絕緣層1 1間產 平衡（參照圖3 ( a))。另外，藉由在各鏈孔1 4之 層1 6 B以指定間隔設置縫隙1 7，可獲得與限制上 1 6 A的寬度w!的寬度相同的效果（參照圖3 ( b ))。 限制處於鏈孔1 4間之區域的金屬層1 6 C的寬度同 間隔設置縫隙1 7，則更為有效（參照圖3 ( c ))。 根據上述情況，若採用本實施形態之各金屬層 1 6 B、1 6 C的形狀等，可有效減低產生於屬最終產 元件安裝用薄膜輸送帶的寬度方向兩側的沿長度 波狀變形，而可獲得提高在半導體安裝線上的搬 時的可靠度的效果。 312/發明說明書(補件V93-06/93106942 層1 6 A上 用薄膜輸 或形狀等 I 1 6之間 薄膜輸送 孔14間 地限制與 補強相關 I效果， 分與各鏈 生的應力 切的金屬 述金屬層 又，若與 時以指定 1 6A、 品之電子 方向上的 運或安裝 17 200422237 \)/ 3 態 形 施 實 膜 薄 用 裝 安 件 元 子 電 的 3 態 形 施 實 之 明 發 本 示 顯 為 4 圖 圖 視 俯 大 放 部 要 的 帶 送 輸 域 區 層 的 6 金 1 在 層 ， 屬 示 金 所在 4 存 tlil未 如有 設200422237 发明 Description of the invention: [Technical field to which the invention belongs] The present invention relates to a film conveyor belt for mounting electronic components for mounting electronic components such as IC or LS I. [Previous technology] With the development of the electronics industry, the demand for printed circuit boards on which electronic components such as 1C (Integrated Circuit) and LSI (Large Integrated Circuit) are mounted has increased sharply. However, miniaturization and weight reduction of electronic devices have also been required. As a method of mounting such electronic components, a mounting method of a film conveyor belt for mounting electronic components using a TAB tape, a T-BGA tape, or an ASIC tape has recently been adopted. Especially in the electronics industry, which uses liquid crystal display elements (LCD) that require high definition, thinness, and narrow frame area of the liquid crystal surface, such as personal computers and mobile phones, its importance is increasing. In addition, along with the miniaturization of electronic devices and the like, a reduction in the thickness of a thin film conveyor belt for mounting electronic components is also required. In recent years, C 0 F (C hi ρ 0 n F i 1 using a thin film insulation layer has been proposed. m) band and so on. Such a film conveyor belt for mounting electronic components is manufactured by, for example, the following steps, which include the steps of forming chain holes for transportation on both sides in the width direction of an insulating layer composed of polyimide; use A step of forming a photoresist coating layer on a copper foil provided on one side of the insulation layer while carrying an insulating layer with a chain hole; a step of exposing and developing the photoresist coating layer; patterning the photoresist coating layer to form A step of masking a pattern; a step of etching a copper foil through the mask pattern to form a wiring pattern; and a step of forming a solder resist layer on each wiring pattern. 6 312 / Invention Manual (Supplement) / 93-06 / 93106942 200422237 However, in the type with a thin insulation layer such as the above-mentioned C0F tape, the rigidity of the chain hole cannot be sufficiently ensured, and there are chain holes during transportation. Deformation problems occur. Here, in order to solve this problem, it is proposed to continuously provide a reinforcing layer (metal layer) along the length direction of the electrically insulating flexible tape (insulating layer) around each chain hole (Sprocket hole) to ensure the belt carrying strength. (See, for example, Patent Document 1). In addition, in the manufacturing steps of the above-mentioned film conveyor belt for electronic component mounting, in particular in the steps of forming the anti-agent layer or the solder anti-agent layer or the tin step, it is introduced to have an area where the wiring pattern is not formed. An embossed barrier element (embossed barrier film), a so-called curing step in which a film conveyor is wound on a reel and heated, or a heating step to prevent the generation of whiskers (for example, see Patent Document 2). (Patent Document 1) Japanese Patent Shikaihei 4-4 8 6 2 9 (Figures 1 to 3, scope of patent application for new registration) (Patent Document 2) Japanese Patent Laid-Open No. 2 0 0 1-7 7 1 5 Publication No. 7 (paragraph [0 0 0 6]) [Summary] (Problems to be Solved by the Invention) However, in the above-mentioned film conveyor belt for mounting electronic components provided with a reinforcing layer, electronic components are mounted on the final product. On the two sides in the width direction of the film conveyor belt, that is, in a region where a chain hole exists, there is a problem of wave-like deformation in which the height along the length direction is about 1 to 2 in m. 7 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 Such noticeable wavy deformation is not found in products without a reinforcing layer on the periphery of the chain hole, in the hardening step or the step of preventing whisker generation In the state where the supply pressure is on the film conveyor belt, the difference in the physical properties of the material between the metal edge layers, such as the difference in linear expansion coefficient strength or elongation, can be considered as processing such as heat and cooling in the manufacturing steps, etc. Complex interactions arise. In addition, such a wavy deformed electronic component mounting film is transported on a semiconductor assembly line, and cannot be smoothly positioned and conveyed by a pin roller or the like, and cannot be tracked and guided in a conveying path, resulting in good quality of the electronic components, and finally formed Defective product. The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a flat film mounting belt for component mounting that can be transported or mounted on a semiconductor mounting line with a high reliability. (Means for Solving the Problem) A first aspect of the present invention that solves the above-mentioned problems is a film conveyor belt for an electronic element, which is provided with a wiring pattern composed of a conductive layer and an insulating layer, and a plurality of numbers provided on both sides of the wiring pattern. The chain hole, and the electronic component mounting film conveyor belt with a metal layer around the chain hole is characterized in that the metal layer is substantially continuous along the length of the insulation layer, and the width of the metal layer in the area between the chain holes w! When the width of the chain hole is set to w 2 [mm], the condition of 0 · 3 $ w 1 $ (v \ is satisfied. In the first aspect described above, the width of the metal layer w! Setting, moderately open the stress generated between the metal layer and the insulating layer, using a heating layer surrounded by 312 / Invention Specification (Supplement) / 93-06 / 93106942 and a feeding belt during insulation or stretching, and In the above, the installation is not raised to the mounting surface of the electronic component. In the above, its direction is connected to [mm], 2 + 1,1) to specify to reduce the yield. 8 200422237 Wavy deformation caused by the film conveyor belt for electronic component mounting. This makes it possible to realize a flat film conveyor belt for electronic component mounting, and to improve reliability during transportation or mounting on a semiconductor mounting line. The second aspect of the present invention is the film conveyor belt for mounting electronic components in the first aspect, characterized in that the width W3 [mm] of the metal layer in the area where the chain hole exists is satisfied (W2 + 0.2) Sw3 $ (W2 + 1.6). In the second aspect described above, moderately opening the stress generated between the insulating layer and the metal layer can effectively reduce the wave-like deformation occurring in the film conveyor belt for electronic component mounting. A third aspect of the present invention is the film conveyor belt for mounting electronic components in the second aspect, characterized in that the width W3 [mm] of the metal layer in the area where the chain hole exists is satisfied ( W2 + 0.2) $ W3 $ (W2 + 1.1). In the third aspect described above, moderately opening the stress generated between the insulating layer and the metal layer can effectively reduce the wave-like deformation occurring in the film conveyor belt for electronic component mounting. The fourth aspect of the present invention is the film conveyor belt for mounting electronic components in any one of the first to third aspects, characterized in that the width of the metal layer wjmm] and the area in which the chain hole exists The width w 3 [mm] of the metal layer satisfies the relationship w 1 < w 3. In the fourth aspect described above, the stress generated between the insulating layer and the metal layer is appropriately opened, which can effectively reduce the wave-like deformation occurring in the film conveyor belt for electronic component mounting. 9 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 The fifth aspect of the present invention is a film conveyor belt for mounting electronic components in any of the first to fourth aspects, characterized in that: The metal layer is discontinuous in the length direction of the insulating layer by setting a specified number of the gaps of each of the chain holes. In the fifth aspect described above, moderately opening the stress generated between the insulating layer and the metal layer can effectively reduce the wave-like deformation occurring in the film conveyor belt for electronic component mounting. A sixth aspect of the present invention is the film conveyor belt for electronic component mounting according to any one of the first to fifth aspects, characterized in that a non- There is a region with a metal layer. In the sixth aspect described above, since no metal layer is provided on the opening periphery of each chain hole, no pin roller or positioning pin or the like inserted into each chain hole is formed in contact with the metal layer during manufacturing or installation. The cause of the short circuit is metal pieces or metal powder. [Embodiment] Hereinafter, the present invention will be described in detail with reference to embodiments. (Embodiment 1) FIG. 1 is a schematic view showing a film conveyor belt for mounting electronic components according to Embodiment 1 of the present invention. FIG. 1 (a) is a plan view, FIG. 1 (b) is a cross-sectional view, and FIG. 1 (c) is a schematic view. Part enlarged top view. As shown in the figure, the film conveyor belt 10 for electronic component mounting of this embodiment is a C 0 F film conveyor belt, and has a wiring pattern 1 3 made of a conductive layer 12 provided on one side of the belt-shaped insulating layer 1 1. And a plurality of chain holes 14 provided on both sides in the width direction of the wiring pattern 13. 10 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 The wiring pattern 1 3 is continuously provided on the surface of the insulating layer 1 1. In addition, the detailed description of such a wiring pattern 13 will be described later, but it is a method in which the conductive layer 1 is coated with a photoresist on the conductive layer 12 provided on the surface of the insulating layer 11 and then exposed, developed, and etched. 2 Formed by patterning. In addition, a solder resist layer 15 formed by applying a solder resist coating material solution by screen printing is provided on the wiring pattern 13. That is, as shown in FIG. 1 (a), the inner portion of the wiring pattern 13 is extended with the internal wiring 13a which is a part of the wiring pattern 13 in the portion where the semiconductor wafer is mounted. On the other hand, outside the solder resist layer 15 on the opposite side of the internal lead 13a, an external lead 13b serving as a terminal portion for external connection, which is a part of the wiring pattern 13, is extended. Here, as the material 11 of the insulating layer, in addition to polyimide, for example, polyester, polyimide, polyether rigid, liquid crystal polymer, etc. can be used, and especially pyromellitic acid 2 anhydride can be used. Fully aromatic polyfluorene imine synthesized with an aromatic diamine (for example, trade name: K apt ο η; manufactured by Toray DuPont), fully aromatic polyfluorene imide with biphenyl skeleton (for example, Commodity name: U Ρ IL Ε X; Ube Industrial (share) system). Thus, the thickness of the insulating layer 11 is generally 1 2. 5 to 1 2 5 // m, preferably 12.5 to 75 # 111, and more preferably 12.5 to 50 # m. On the other hand, as the material of the conductive layer 12, in addition to copper, Ie, gold, silver, etc. can be used, but generally a copper layer. As the copper layer, any of a copper layer formed by vapor bonding or electroplating, an electrolytic copper foil, a rolled copper foil, or the like can be used. The thickness of the conductive layer 12 is generally 1 to 70 / im, and preferably 5 to 35 // m. In addition, metal layers 16 for reinforcing the respective chain holes 14 are provided around the chain holes 14 during positioning and transportation on the semiconductor mounting line. That is, the metal 11 312 / invention specification (supplement) / 93-06 / 93106942 200422237 layer 16 is connected to the plurality of chain holes 1 4 provided on both sides in the width direction of the insulating layer 1 1 and the wiring pattern 1 3 is discontinuous and is provided continuously along the longitudinal direction of the insulating layer 1 1. Therefore, in this embodiment, for example, the metal layer 16 is formed by patterning the conductive layers 12 simultaneously with the wiring pattern 13 and is used as a dummy wiring for ensuring the strength of each chain hole 14. Here, in the present invention, the width w! [Mm] of the metal layer 16 in the region between the chain holes 14 satisfies 0 · 3 S when the width of the chain hole 14 is set to w 2. The condition of w 1 S (w 2 + 1 · 1) is preferably a condition of 0 · 5 S w 1 S (w 2 + 1 · 0) (see FIG. 1 (c)). For example, in the present embodiment, the width w! Of the metal layer 16 is set to 2.4 m. Here, the minimum value of the width of the metal layer is set to 0.3 mm in order to ensure the rigidity between the chain holes 14 and obtain the required belt handling strength. In addition, in the present invention, the width w 3 [mm] of the metal layer 16 in the region where the chain hole 14 exists is when the width of the chain hole 14 is set to w 2, preferably ( w 2 + 0. 2) S w 3 S (w 2 + 1 · 6), and a particularly preferred condition is to satisfy (w 2 + 0 · 2) S w 3 S (w 2 + 1 · 1). For example, in this embodiment, the width w! Of the metal layer 16 in the region between the chain holes 14 and the width w3 of the metal layer 16 in the region where the chain holes 14 exist are set to be the same width, that is, W 1 = W 3. Here, the minimum value of the width W 3 of the metal layer 16 is set to w 2 + 0.2 mm, in order to ensure the rigidity of each chain hole 14 and obtain the required belt handling strength. The relationship between the width of the metal layer 16 on one side and the width of the metal layer 16 on the other side of each chain hole 14 is preferably the same width, but it may be different. In addition, the metal layer 16 is preferably provided on the inner side of both end portions in the width direction of the insulating layer 11 more than 12 312 / Invention (Supplement) / 93-06 / 93106942 200422237. This is to prevent the metal layer 16 from coming into contact with the guide or the like provided on the conveyance path during the manufacturing or installation process, thereby generating a metal sheet or metal powder. Here, the width w 2 of the chain hole 14 is specified in accordance with the EIAJ (Electrical Machinery Industry Association of Japan) specifications, and its standard values are 3511111 in width (insulation layer 11) and 1.42 ± 0.03111111 in 4811111, respectively. It is 7011111 and 1.98 ± 0.03mm. Regarding the pitch of the chain holes 14, the standard value is set to 4. 7 5 soil 0.05 mm. As described above, in this embodiment, a metal layer 16 that is at least in a region between the chain holes 14 is used. The width w! Is limited to a specified amount. In the later-mentioned hardening step, the stress generated between the metal layer 16 and the insulating layer 11 is appropriately opened, and the film conveyor belt 1 for mounting electronic components, which is a final product, can be reduced. The wavy deformation that occurs in the length direction on both sides in the width direction of 0. That is, it is possible to realize a flat film conveyor belt 10 for mounting electronic components, and improve reliability on a semiconductor mounting line. In addition, since the rigidity of the entire belt does not become too large, the belt itself can follow the conveying path freely even when the conveying path is bent, and can be conveyed better. In addition, the film conveyor belt 10 for mounting electronic components configured as described above is, for example, a semiconductor device having a size corresponding to 5 to 10 pieces of semiconductors and cut into strips to be supplied to a mounting device to mount electronic components such as semiconductors. At this time, since the metal layer 16 is provided around the chain hole 14, the rigidity of the chain hole 14 can be ensured, and electronic components can be mounted with high accuracy. Here, an example of a manufacturing method of the above-mentioned film conveyance for electronic component mounting 13 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 10 will be described with reference to FIG. 2. Fig. 2 is a cross-sectional view illustrating a method for manufacturing a film conveyor belt for mounting electronic components. In the manufacturing method of this embodiment, after each manufacturing step described later, although not shown, the embossed interlayer film having uneven portions in a region where a wiring pattern is not formed is rolled together with a film conveyor belt (C0F laminated film) Take it on a reel and introduce a heated hardening step if necessary. First, as shown in FIG. 2 (a), a laminated film 20 for COF in which a conductive layer 12 is formed on an insulating layer 11 is prepared. Next, as shown in FIG. 2 (b), the insulating layer 11 and the conductive layer 12 are penetrated by punching (pu n c h i n g) or the like to form a chain hole 14. This chain hole 14 may be formed on the surface of the insulating layer 11 or on the back surface of the insulating layer 11. Furthermore, as shown in FIG. 2 (c), a photoresist coating solution is applied along the area where the wiring pattern 13 is formed on the conductive layer 12 using a general photolithography etching method. 0 ~ 1 0 0 ° C heat-hardened to form a photoresist coating layer 21. In addition, after inserting positioning pins in the chain holes 14 to locate the position of the insulating layer 11, exposure and development are performed through the photomask 22, and the photoresist material coating layer 21 is patterned to form a pattern as shown in FIG. 2 (d The resist pattern 23 for a wiring pattern shown in FIG. Next, as shown in FIG. 2 (d), for example, a transfer method is used in this embodiment to partially apply a resist material coating solution to a region corresponding to the chain hole 14 to form a metal layer 16. The metal layer with a resist pattern 2 4. For example, in this embodiment, the width Wi of the metal layer 16 in the region between the chain holes 14 and the width W 3 of the metal layer 16 in the region where the chain holes 14 exist are set to be the same width. That is, gold 14 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 resist pattern 24 for a metal layer is formed in a manner of WI = W3. The resist pattern 24 for the metal layer may be formed before the resist pattern 23 for the wiring pattern is formed, or may be separately formed by the transfer method before the chain hole 14 is formed. Of course, the resist pattern 23 for wiring patterns and the resist pattern 24 for metal layers may be formed simultaneously. Next, using the resist pattern 23 for the wiring pattern and the resist pattern 24 for the metal layer as a mask pattern, the conductive layer 12 is dissolved and removed by an etching solution, and the resist pattern 2 for the wiring pattern is removed by dissolving the alkali solution or the like. 3 and the metal layer resist pattern 2 4 to form a wiring pattern 13 and a metal layer 16 as shown in FIG. 2 (e). Next, as shown in FIG. 2 (f), a tin plating layer (not shown) is formed on the surface of the wiring pattern 13 and the metal layer 16, and an embossed spacer is sandwiched therebetween and wound on a reel. Heat treatment at about 80 ° ~ 200 ° C. This can prevent the occurrence of Hu Jing. Next, for example, a screen printing method is used to form a solder resist layer 15. For example, in this embodiment, a solder resist layer 15 is formed so as to surround the central portion of the wiring pattern 13, an internal lead 1 3 a is formed at the central portion of the wiring pattern 13, and a solder resist layer 1 is formed. The outer wires 5 form the outer wires 1 3 b. This is sandwiched between the embossed partition and wound up on a reel, and heat-cured at about 100 to 200 ° C. Thereby, the film conveyor belt 10 for electronic component mounting shown in FIG. 1 is completed. In each process of such a thin film conveyor belt 10 for electronic component mounting, in particular, the hardening step introduced in the step of forming each resist pattern 2 3, 2 4 and the step of forming the solder resist layer 15 In this embodiment, by using at least the width w of the metal layer 16 in the area between the chain holes 14 to a specified amount, the gap between the insulating layer 11 and the metal layer 16 can be appropriately opened 15 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 Internal stress generated. Therefore, with such stress, it is possible to reduce the wavy deformation in the longitudinal direction which is lower than the widthwise sides of the film conveyor belt 10 for electronic component mounting. In other words, a flat film conveyor belt 10 for mounting electronic components can be realized. In addition, the rigidity of the chain holes 14 can be improved by the metal layer 16 and sufficient belt handling strength can be ensured. Therefore, when mounting electronic components, it is easy to position and transport by inserting needle rollers into the chain holes 14 and tracking the guides provided on the transport path. This improves the handling or mounting on the semiconductor mounting line. Reliability. In this embodiment, as described above, the metal layer 16 is continuously provided with the same width along the longitudinal direction of the insulating layer 11, but the shape of the metal layer is not limited to this. Hereinafter, the shape of the metal layer will be exemplified based on the embodiment. (Embodiment 2) FIG. 3 is an enlarged plan view of a main part of a film conveyor belt for mounting electronic components according to Embodiment 2 of the present invention. As shown in FIG. 3 (a), the metal layer 16 A has a width Wi [mm] of the metal layer 16A between the chain holes 14, which is larger than the width of the metal layer 16 A in the area where the chain holes 14 exist. w 3 is small, that is, it is set on the condition that w! < w 3. In addition, as shown in FIG. 3 (b), the metal layer 16B is provided in the length direction of the insulating layer 11 corresponding to a specified number, for example, 3 to 8 chain holes 1 to 4 are continuously arranged, and these chain holes The 1 4 lineage is discontinuous through the gap 1 7. The length L [mm] of the metal layer 1 6 B in the longitudinal direction is about 10 to 4 0 in, which is equivalent to 3 to 8 pieces of chain ridge L 1 4, and preferably 3 to 6 pieces. The amount is 10 to 30 mm. For example, in the present embodiment, it is 17 to 19 mm corresponding to four chain holes 14. The width of the slit 17 is not particularly limited. It is preferably 16 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237, but is preferably about 0.1 to 2.0 mm, for example. As shown in FIG. 3 (c), the metal layer 16C is provided with a slit 17 in the metal. As described above, in the electronic component mounting tape of this embodiment, the width of each metal layer 16A, 16B, and 16C is limited to a specified amount. Therefore, the stress generated by the insulating layer 11 and the metal J can be fully opened, and The wave-like deformation of the electronic component mounting tape is more effectively reduced. In particular, in this embodiment, the width w! Of the metal layer 16 A in the region of the chain is restricted as small as possible, that is, as small as possible, the reinforcement of each chain hole 14 is not directly related, but it is related to the film conveyor belt. The width w! Of the metal layer 16A is to ensure the complement of each chain hole 14. At the same time, the metal layer 16 A of the portion between the hole 14 and the surrounding portion 14 of each chain hole 14 can be adjusted along the length of the belt and insulated. The balance of production between layers 1 and 1 (see Figure 3 (a)). In addition, by providing the slits 17 at the specified intervals in the layers 16B of each of the chain holes 14, the same effect as that of limiting the width w! Of 16A can be obtained (see FIG. 3 (b)). It is more effective to limit the width of the metal layer 16 C in the region between the chain holes 14 to the gap 17 at the same interval (refer to FIG. 3 (c)). According to the above, if the shape of each of the metal layers 1 6 B and 16 C of this embodiment is adopted, it is possible to effectively reduce the length-wave-like deformation that occurs on both sides in the width direction of the film conveyor belt for the final component installation. It is possible to obtain the effect of improving the reliability during transportation on the semiconductor mounting line. 312 / Explanation of the invention (Supplement V93-06 / 93106942 The film conveyance or shape on the layer 1 6 A is between I 1 6 and the film transport hole 14 limits the effect related to the reinforcement, and it is divided into the stress generated by each chain. The metal layer and the metal layer, if the time is specified with the 16A, the direction of the electronic product or installation 17 200422237 \) / 3-state implementation film thin film installation equipment Yuanzidian three-state implementation of the This display is shown in Figure 4 as shown in the figure below. It is required to bring the 6 gold 1 layer on the layer of the transport area. It belongs to the 4 where the gold is located.
間 之 nr 立口 緣 口 開 之 4 11 孔 「蒙} 鏈 與 D 6 IX 層 金 在 存 未 之 此 如 又 ~ A ο ηϋ 11 右 左層 屬 ο各 ~ 之 1 2 ο 態 為 形 好施 最 實 如 述 上 在 可 也 但 示 圖 未 度 寬 的 域 區 的 例 域 區 的 層 屬 金 在 存 未 有 設 間 之 緣 周 口 開 之 4 11 孔 鏈 各 與 金 屬 在金 由在 藉存 ， 未 般 置 此 設 如 間 之 外 1 另 孔 !·** ο 鏈 果入 效插 的 生 同 產 相 會 態 不 孔 鏈，中 各域態 與 區形 6D的施 1 D 實 層 1 本 屬層， 可 銷 位 定 或 1¾ 針 的 4 β— 咅 緣 周 D 開 之 4 11 形 ， 施時 實 裝 述安 上或 與 造 示 得 製 圖 獲在未 金 與 等 層1 6 D接觸而形成金屬層1 6 D缺陷之情況，亦即不會產生 金屬片或金屬粉等。因此，可確實防止因如此之金屬片或 金屬粉等而產生的例如配線圖案的短路等的不良狀況。 在此，準備金屬層的形狀或寬度尺寸各異的實施例1〜8 與比較例1及2，考慮絕緣層與金屬層的材料物性質的平 衡，檢討適度開放產生於絕緣層與金屬層間的應力，以實 現平坦的電子元件安裝用薄膜輸送帶的較佳條件。 (實施例1 ) 於帶寬3 5 m m的絕緣層的寬度方向兩側形成複數鏈孔 (w 2 = 1 . 4 2 m m )後，將設於絕緣層上的導電層予以圖案加工， 以形成配線圖案，並於形成有鏈孔的絕緣層的寬度方向兩 側的區域沿其長度方向連續形成寬度w ! = 2 . 4、w 3 = 2 . 4 [ m m ] 18 3】2/發明說明書(補件)/93-06/93106942 200422237 的金屬層，在各配線圖案上形成鍍錫層後，再形成焊料抗 蝕層，將此作為實施例1之電子元件安裝用薄膜輸送帶（參 照圖1 ( c ))。 (實施例2 ) 除了於4個鏈孔的各個設置縫隙外，其他與實施例1相 同，將此作為實施例2之電子元件安裝用薄膜輸送帶（參照 圖3(b))。又，各金屬層之長度方向的長度設為L=18.0mm。 (實施例3 ) 除了形成寬度wi = 2.2、W3 = 2.2[mm]的金屬層以外，其他 與實施例1相同，將此作為實施例3之電子元件安裝用薄 膜輸送帶（參照圖1 ( c ))。 (實施例4 ) 除了於4個鏈孔的各個設置縫隙外，其他與實施例3相 同，將此作為實施例4之電子元件安裝用薄膜輸送帶（參照 圖3(b))。又，各金屬層之長度方向的長度設為L=18.4丨nm。 (實施例5 ) 除了形成寬度wi = 1.5、W3 = 2.9[mm]的金屬層以外，其他 與實施例1相同，將此作為實施例5之電子元件安裝用薄 膜輸送帶（參照圖3 ( a ))。 (實施例6 ) 除了於4個鏈孔的各個設置縫隙外，其他與實施例5相 同，將此作為實施例6之電子元件安裝用薄膜輸送帶（參照 圖3(c))。又，各金屬層之長度方向的長度設為L=18. Omm。 (實施例7 ) 19 312/發明說明書(補件)/93-06/93106942 200422237 除了形成寬度wi = 1.0、W3 = 2.2[mm]的金屬層以外，其他 與實施例1相同，將此作為實施例7之電子元件安裝用薄 膜輸送帶（參照圖3 ( a ))。 (實施例8 ) 除了於4個鏈孔的各個設置縫隙外，其他與實施例7相 同，將此作為實施例8之電子元件安裝用薄膜輸送帶（參照 圖3(c))。又，各金屬層之長度方向的長度設為L=18.4mm。 (比較例1 ) 將沿絕緣層的長度方向連續形成寬度w 1 = 2 · 7、w 3 = 2 . 7 [ m m ] 的金屬層者，作為比較例1之電子元件安裝用薄膜輸送帶。 (比較例2 ) 除了形成寬度wi = 3.0、W3 = 3.0[mm]的金屬層以外，其他 與比較例1相同，將此作為比較例2之電子元件安裝用薄 膜輸送帶。 (試驗例1 ) 針對上述各實施例1〜8與比較例1及2，分別準備8個 試樣，針對各試樣形成配線圖案，在該配線圖案上施以鍍 錫後，以中間夾入壓紋隔層而捲取於捲軸上的狀態進行於 約1 2 0 °C的溫度條件下6 0分鐘的加熱處理。然後，在形成 焊料抗蝕劑層後，以中間夾入壓紋隔層而捲取於捲軸上的 狀態進行於約1 4 0 °C的溫度條件下1 2 0分鐘的加熱處理。 針對如此之各試樣，分為配線圖案形成後、鍍錫後、焊料 抗蝕劑層形成後的3次，來測定電子元件安裝用薄膜輸送 帶的波狀變形量[mm]。具體而言，將各實施例及比較例之 20 312/發明說明書(補件)/93-06/93106942 200422237 電子元件安裝用薄膜輸送帶載置於基台上，從該基台的上 面來測定電子元件安裝用薄膜輸送帶的寬度方向兩端部向 上浮起部分的最大高度。然後，將各試樣的最大高度的平 均值作為電子元件安裝用薄膜輸送帶的波狀變形量 [m m ]。下表1顯示其結果。 又，波狀之離基台的最大高度[m m ]的測定，係例如使用 可從載置於基台上的電子元件安裝用薄膜輸送帶的垂直方 向上側照射雷射光，並藉由雷射光的反射測定距離的雷射 反射測定器來進行。 (試驗例2 ) 設為與上述實施例1及3的金屬層相同形狀（參照圖 1(c))，使該金屬層的寬度wi、W3[mm]變化至1.8〜3.0mm， 調查此時之焊料抗蝕劑層形成後的波狀變形量[m m ]的變 化。圖5顯示其結果。又，圖5為顯示金屬層的寬度wi、 W3與焊料抗蝕劑層形成後的波狀變形量的關係的曲線圖。 (表1) 金Μ i層 :m m ] 波狀變形量[m m ] W 1 W 3 L 配線圖案 形成後 鍍錫後 焊料抗蝕劑 層形成後 實施例1 2. 4 2.4 一 0. 8 0. 9 1 . 0 實施例2 2. 4 2. 4 18.0 0. 8 0. 8 0.9 實施例3 2. 2 2.2 — 0. 6 0. 7 0. 8 實施例4 2. 2 2. 2 18.4 0.55 0. 6 0.7 實施例5 1 . 5 2. 9 一 0. 5 0. 6 0.65 實施例6 1 . 5 2. 9 18.0 0. 5 0.55 0.6 實施例7 1 . 0 2. 2 — 0. 5 0.55 0. 6 實施例8 1 · 0 2. 2 18.4 0.45 0.45 0.55 比較例1 2. 7 2.7 — 1 . 0 1 . 2 1.35 比較例2 3. 0 3. 0 — 1 . 1 1 . 2 1 . 4 從表1的結果可知，在實施例1及3中，與比較例1及 21 200422237 2相比，藉由較小地限制金屬層的寬度w I、w 3，可將焊料 抗蝕劑層形成後的波狀變形量減低為約接近6 0〜7 0 %。另 外，在實施例2及4中，除上述實施例1及3之各條件外， 藉由以指定間隔於金屬層上設置縫隙，可知與比較例1及 2相比，可將焊料抗蝕劑層形成後的波狀變形量減低為約 接近5 0〜6 5 %。又，該情況係如圖5所示，從在金屬層的 寬度w 1約小於2 . 5 m m的情況，波狀變形量[m m ]急遽降低的 情況可得到保證。 在實施例5中，可知與比較例1及2相比，只要將處於 各鏈孔之間的金屬層的寬度w3設為更小，便可將焊料抗蝕 劑層形成後的波狀變形量減低為約接近5 0 %。又，關於金 屬層的寬度w3與波狀變形量的關係，可考慮顯示與圖5所 示曲線相同的推移，因此若較小地限制金屬層的寬度W3 的話，便可進一步減低焊料抗蝕劑層形成後的波狀變形 量。又，在實施例6中，除上述實施例5之條件外，藉由 以1 8. 0 m m的間隔設置縫隙，可知與上述各比較例1及2 相比，可將焊料抗蝕劑塗佈加熱後的波狀變形量減低為約 接近4 5 %。 此外，在實施例7中，可知與上述各比較例1及2相比， 利用進一步較小限制金屬層的寬度W I、W 3，便可將焊料抗 蝕劑塗佈加熱後的波狀變形量減低為約接近4 5 %。另外， 在實施例8中，除上述實施例7之條件外，藉由以1 8 . 4 m m 的間隔設置縫隙，可知與上述各比較例1及2相比，可將 焊料抗蝕劑塗佈加熱後的波狀變形量減低為約接近4 0 %。 22 312/發明說明書(補件)/93-06/93106942 200422237 因此，藉由將金屬層的寬度W 1、W 3限制在指定量，或設 置縫隙，可實現平坦的電子元件安裝用薄膜輸送帶，因而 可提高在半導體安裝線上的搬運或安裝時的可靠度。 另外，如上述表1所示，可知可減低產生於配線圖案形 成後或鍍錫後之薄膜輸送帶的波狀變形量。因此，可獲得 防止在電子元件安裝用薄膜輸送帶之製造時的搬送不良的 產生的效果。 又，在上述各實施例1〜8中係使用帶寬3 5 m m的絕緣 層，但使用帶寬70mm(69.950±0.2mm)的絕緣層，也可獲 得與上述類似的結果及效果。 (其他之實施形態） 以上說明了本發明之各實施形態，當然，電子元件安裝 用薄膜輸送帶並不侷限於上述者。 例如，在上述實施形態中，雖例示並說明了 1列設置配 線圖案1 3及鏈孔1 4等組成的輸送圖案的電子元件安裝用 薄膜輸送帶1 0，但不侷限於此，例如，也可為複數並列設 置輸送圖案的多條電子元件安裝用薄膜輸送帶。 另外，在上述實施形態中，雖例示了屬C0F薄膜輸送帶 之電子元件安裝用薄膜輸送帶10,但也可為其他的電子元 件安裝用薄膜輸送帶，如TAB、CSP、BGA、μ-BGA、FC、 QFP型式等，其構成等亦不受限制。 (發明效果） 如上述所說明，根據本發明，藉由實質上至少沿絕緣層 的長度方向連續設置金屬層，且將鏈孔之間區域的金屬層 23 312/發明說明書(補件V93-06/93106942 200422237 寬度w i [ m m ]，在將該鏈孔寬度設為w 2 [ m m ]時，滿足0 · 3 $ w 1 $ ( w 2 + 1 · 1 )的條件，可適度開放金屬層與絕緣層之間產 生的應力，以減低產生於電子元件安裝用薄膜輸送帶的波 狀變形。藉此，可實現平坦的電子元件安裝用薄膜輸送帶， 提高在半導體安裝線上的搬運或安裝時的可靠度。 【圖式簡單說明】 圖1為顯示本發明之實施形態1的電子元件安裝用薄膜 輸送帶的概要圖，圖1 ( a )為俯視圖，圖1 ( b )為剖視圖，圖 I ( c )為要部放大俯視圖。 圖2 ( a )〜（f )為說明本發明之實施形態1的電子元件安 裝用薄膜輸送帶的製造方法的一例的剖面圖。 圖3 ( a )〜（c )為本發明之實施形態2的電子元件安裝用 薄膜輸送帶的要部放大俯視圖。 圖4為顯示本發明之實施形態3的電子元件安裝用薄膜 輸送帶的要部放大俯視圖。 圖5為顯示金屬層的寬度w!、w3與焊料抗蝕劑層形成後 的波狀變形量的關係的曲線圖。 (.元件符號說明） 10 電子元件安裝用薄膜輸送帶 II 絕緣層 12 導電層 13 配線圖案 13a 内部導線 13b 外部導線 24 3】2/發明說明書(補件)/93-06/93】06942 200422237 14 鏈孔 15 焊料抗#劑層 16 金屬層 1 6 A 金屬層 1 6B 金屬層 1 6C 金屬層 1 6D 金屬層The gap between the nr opening and the opening of the 4 11 hole "Mongol" chain and the D 6 IX layer of gold are still there ~ A ο ηϋ 11 The right and left layers belong to each of the ~ 1 2 ο The state is the best shape In fact, the layered gold in the domain area that is not too wide is not shown in the illustration. The layer of gold in the existence of the existence of the gap between the opening and closing of the 4 11 hole chain and the metal in the gold are borrowing, not Place this setting as if it is outside the room 1 another hole! · ** ο The phytosynthetic phase of the fruit fruit is not a non-porous chain, and the domain states and shapes of the 6D are applied 1 D. The solid layer 1 is the native layer , Can be pinned or 1 ¾ pin 4 β— 咅 edge circumference D open 4 11 shape, when the installation description is placed on it or in contact with the same layer 16 D to form a metal layer In the case of a 16 D defect, that is, a metal sheet or metal powder is not generated. Therefore, it is possible to surely prevent a defective condition such as a short circuit of a wiring pattern caused by such a metal sheet or metal powder, etc. Here, prepare Examples 1 to 8 having different shapes or width dimensions of the metal layer Compared with Examples 1 and 2, considering the balance of the material properties of the insulating layer and the metal layer, review the appropriate conditions for moderately opening the stress generated between the insulating layer and the metal layer to achieve a flat film conveyor belt for electronic component mounting. Example 1) After forming a plurality of chain holes (w 2 = 1.4 2 mm) on both sides in the width direction of the insulating layer with a bandwidth of 35 mm, pattern the conductive layer provided on the insulating layer to form a wiring pattern. The widths on both sides in the width direction of the insulating layer where the chain hole is formed are continuously formed along the length direction w! = 2.4, w 3 = 2.4 [mm] 18 3] 2 / Specification of the Invention (Supplement) / 93-06 / 93106942 200422237, after forming a tin plating layer on each wiring pattern, and then forming a solder resist layer, this was used as a film conveyor belt for mounting electronic components in Example 1 (see FIG. 1 (c) (Example 2) Except that the slits are provided in each of the four chain holes, it is the same as Example 1, and this is used as the film conveyor belt for electronic component mounting of Example 2 (see FIG. 3 (b)). The length of each metal layer in the length direction is set to L = 18.0 mm. 3) Except for forming a metal layer having a width of wi = 2.2 and W3 = 2.2 [mm], the other parts are the same as in Example 1, and this is used as a film conveyor belt for mounting electronic components in Example 3 (see FIG. 1 (c)). (Example 4) Except that a slit is provided in each of the four chain holes, it is the same as Example 3, and this is used as a film conveyor for electronic component mounting of Example 4 (see FIG. 3 (b)). The length in the longitudinal direction of each metal layer is set to L = 18.4 nm. (Example 5) Except that a metal layer having a width of wi = 1.5 and W3 = 2.9 [mm] was formed, it was the same as Example 1, and this was used as a film conveyor belt for mounting electronic components in Example 5 (see FIG. 3 (a )). (Embodiment 6) The same procedure as in Embodiment 5 was performed except that slits were provided in each of the four chain holes, and this was used as a film conveyor belt for mounting electronic components in Embodiment 6 (see Fig. 3 (c)). Omm。 The length in the longitudinal direction of each metal layer is set to L = 18. Omm. (Example 7) 19 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 Except that a metal layer having a width of wi = 1.0 and W3 = 2.2 [mm] was formed, the other parts were the same as those in Example 1, and this was implemented as The film conveyor belt for electronic component mounting of Example 7 (refer to FIG. 3 (a)). (Embodiment 8) The same procedure as in Embodiment 7 was carried out except that slits were provided in each of the four chain holes, and this was used as a film conveyor belt for mounting electronic components in Embodiment 8 (see Fig. 3 (c)). The length in the longitudinal direction of each metal layer was set to L = 18.4 mm. (Comparative Example 1) A metal layer having a width w 1 = 2 · 7, and w 3 = 2.7 [m m] continuously formed along the length of the insulating layer was used as a film conveyor belt for mounting electronic components in Comparative Example 1. (Comparative Example 2) Except that a metal layer having a width of wi = 3.0 and W3 = 3.0 [mm] was formed, it was the same as Comparative Example 1, and this was used as a thin film conveyor belt for mounting electronic components in Comparative Example 2. (Experimental example 1) For each of the above-mentioned Examples 1 to 8 and Comparative Examples 1 and 2, eight samples were prepared, a wiring pattern was formed for each sample, tin plating was applied to the wiring pattern, and then sandwiched therebetween. The interlayer was embossed and wound on a reel, and the heat treatment was performed at a temperature of about 120 ° C for 60 minutes. Then, after the solder resist layer is formed, the embossed barrier layer is sandwiched between the solder resist layer and wound on the reel, and the heat treatment is performed at a temperature of about 140 ° C for 120 minutes. With respect to each of these samples, the wave shape deformation [mm] of the film conveyor belt for electronic component mounting was measured three times after the wiring pattern was formed, after tin plating, and after the solder resist layer was formed. Specifically, 20 312 / Invention Specification (Supplement) / 93-06 / 93106942 200422237 of each Example and Comparative Example was placed on a base plate and measured from the top of the base plate. Maximum height of the floating portion at both ends in the width direction of the film conveyor belt for electronic component mounting. Then, the average value of the maximum height of each sample was taken as the wave-shaped deformation amount [m m] of the film conveyor belt for electronic component mounting. Table 1 below shows the results. In addition, the measurement of the maximum height [mm] of the wavy shape from the abutment is performed by, for example, irradiating laser light from a vertical upper side of a film conveyor belt for mounting electronic components mounted on the abutment, A laser reflection measuring device for reflection measurement distance is performed. (Experimental example 2) The same shape as that of the metal layers of Examples 1 and 3 described above (see FIG. 1 (c)), and the widths wi and W3 [mm] of the metal layers were changed to 1.8 to 3.0 mm. Changes in the amount of corrugated deformation [mm] after the formation of the solder resist layer. Figure 5 shows the results. FIG. 5 is a graph showing the relationship between the widths wi and W3 of the metal layer and the amount of wave-like deformation after the solder resist layer is formed. (Table 1) Gold M i layer: mm] Wavy deformation [mm] W 1 W 3 L Wiring pattern is formed After tin plating After solder resist layer is formed Example 1 2. 4 2.4-0.8 0. 9 1 .0 Example 2 2. 4 2. 4 18.0 0. 8 0. 8 0.9 Example 3 2. 2 2.2 — 0. 6 0. 7 0. 8 Example 4 2. 2 2. 2 18.4 0.55 0 6 0.7 Example 5 1. 5 2. 9-0. 5 0. 6 0.65 Example 6 1. 5 2. 9 18.0 0. 5 0.55 0.6 Example 7 1. 0 2. 2 — 0. 5 0.55 0 6 Example 8 1 · 0 2. 2 18.4 0.45 0.45 0.55 Comparative Example 1 2. 7 2.7 — 1. 1.0 1. 2 1.35 Comparative Example 2 3. 0 3. 0 — 1.. 1 1. 2 1. 4 As can be seen from the results in Table 1, in Examples 1 and 3, compared with Comparative Examples 1 and 21 200422237 2, the widths of the metal layers w i and w 3 were set to be smaller, and after the solder resist layer was formed, The amount of wavy deformation is reduced to approximately 60 to 70%. In addition, in Examples 2 and 4, in addition to the conditions of Examples 1 and 3 described above, by providing a gap in the metal layer at a predetermined interval, it can be seen that the solder resist can be compared with Comparative Examples 1 and 2. After the layer is formed, the amount of wave-like deformation is reduced to approximately 50 to 65%. In addition, as shown in FIG. 5, from the case where the width w 1 of the metal layer is less than about 2.5 mm, the case where the amount of wave-shaped deformation [m m] decreases sharply can be guaranteed. In Example 5, it was found that, compared with Comparative Examples 1 and 2, as long as the width w3 of the metal layer between each chain hole is made smaller, the amount of wave-like deformation after the solder resist layer is formed The reduction is approximately 50%. In addition, regarding the relationship between the width w3 of the metal layer and the amount of undulation, it is considered to show the same transition as the curve shown in FIG. 5. Therefore, if the width W3 of the metal layer is restricted to a small extent, the solder resist can be further reduced. The amount of wave-like deformation after layer formation. In addition, in Example 6, in addition to the conditions of the above-mentioned Example 5, by providing gaps at intervals of 18.0 mm, it can be seen that the solder resist can be applied in comparison with each of the above Comparative Examples 1 and 2. After heating, the amount of wavy deformation was reduced to approximately 45%. In addition, in Example 7, it can be seen that, compared with the respective Comparative Examples 1 and 2 described above, by further narrowing the widths of the metal layers WI and W 3, the amount of wave-like deformation after heating and soldering the solder resist can be applied. The reduction is approximately 45%. In addition, in Example 8, in addition to the conditions of the above-mentioned Example 7, by providing a gap at an interval of 18.4 mm, it can be seen that the solder resist can be applied in comparison with the respective Comparative Examples 1 and 2 described above. After heating, the amount of wavy deformation was reduced to approximately 40%. 22 312 / Invention Manual (Supplement) / 93-06 / 93106942 200422237 Therefore, by limiting the width W1, W3 of the metal layer to a specified amount, or setting a gap, a flat film conveyor belt for electronic component mounting can be realized Therefore, the reliability during transportation or mounting on a semiconductor mounting line can be improved. In addition, as shown in Table 1 above, it was found that the amount of wave-like deformation of the film conveyor belt which is generated after the wiring pattern is formed or after the tin plating is reduced. Therefore, it is possible to obtain the effect of preventing the occurrence of transport defects during the manufacture of the film conveyor belt for electronic component mounting. In each of the above-mentioned Examples 1 to 8, an insulating layer having a bandwidth of 35 mm was used. However, similar results and effects can be obtained by using an insulating layer having a bandwidth of 70 mm (69.950 ± 0.2 mm). (Other Embodiments) Although the embodiments of the present invention have been described above, it goes without saying that the film conveyor belt for mounting electronic components is not limited to the above. For example, in the above-mentioned embodiment, the film conveying belt 10 for electronic component mounting in which the conveying pattern consisting of the wiring pattern 13 and the chain hole 14 are provided in one row has been illustrated and described. However, the present invention is not limited to this. A plurality of film conveyor belts for electronic component mounting, in which a plurality of transfer patterns can be arranged in parallel. In addition, in the above-mentioned embodiment, although the film conveyor belt 10 for electronic component mounting which is a COF film conveyor belt is exemplified, other film conveyor belts for electronic component mounting, such as TAB, CSP, BGA, μ-BGA , FC, QFP types, etc., and their composition is not limited. (Effects of the Invention) As described above, according to the present invention, the metal layer is continuously provided substantially at least along the length of the insulating layer, and the metal layer in the region between the chain holes is 23 312 / Invention Specification (Supplement V93-06) / 93106942 200422237 The width wi [mm], when the width of the chain hole is set to w 2 [mm], the condition of 0 · 3 $ w 1 $ (w 2 + 1 · 1) can be met, and the metal layer and insulation can be opened appropriately. The stress generated between the layers reduces the wave-like deformation of the film conveyor belt for electronic component mounting. Thereby, a flat film conveyor belt for electronic component mounting can be realized, and the reliability during transportation or mounting on a semiconductor mounting line can be improved. [Brief description of the drawings] FIG. 1 is a schematic view showing a film conveyor belt for mounting electronic components according to Embodiment 1 of the present invention, FIG. 1 (a) is a plan view, FIG. 1 (b) is a cross-sectional view, and FIG. I (c ) Is an enlarged plan view of main parts. Figs. 2 (a) to (f) are cross-sectional views illustrating an example of a method for manufacturing a film conveyor belt for mounting electronic components according to Embodiment 1 of the present invention. Figs. 3 (a) to (c) Electron according to Embodiment 2 of the present invention An enlarged plan view of the main parts of the film conveyor belt for component mounting. Fig. 4 is an enlarged plan view of the main parts of the film conveyor belt for electronic component mounting according to Embodiment 3 of the present invention. Fig. 5 shows the widths w !, w3 and solder of the metal layer. A graph showing the relationship between the amount of undulated deformation after the formation of the resist layer. (Description of element symbols) 10 Film conveyor belt for electronic component mounting II Insulating layer 12 Conductive layer 13 Wiring pattern 13a Internal conductor 13b External conductor 24 3] 2 / Invention Manual (Supplements) / 93-06 / 93] 06942 200422237 14 Chain holes 15 Solder resistance #agent layer 16 Metal layer 1 6 A Metal layer 1 6B Metal layer 1 6C Metal layer 1 6D Metal layer
17 縫隙 20 C0F用積層薄膜 2 1 光阻材料塗佈層 22 光罩 23 配線圖案用抗蝕劑圖案 24 金屬層用抗蝕劑圖案 W 1 寬度 W2 寬度17 Gap 20 Laminated film for C0F 2 1 Photoresist coating layer 22 Photomask 23 Resist pattern for wiring pattern 24 Resist pattern for metal layer W 1 Width W 2 Width
312/發明說明書(補件)/93-06/93106942 25312 / Invention Specification (Supplement) / 93-06 / 93106942 25