TW200421601A - A novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout - Google Patents

Abstract

A nonvolatile memory array has a single transistor flash memory cell and a two transistor EEPROM memory cell which maybe integrated on the same substrate. The nonvolatile memory cell has a floating gate with a low coupling coefficient to permit a smaller memory cell. The floating gate placed over a tunneling insulation layer, the floating gate is aligned with edges of the source region and the drain region and having a width defined by a width of the edges of the source the drain. The floating gate and control gate have a relatively small coupling ratio of less than 50% to allow scaling of the nonvolatile memory cells. The nonvolatile memory cells are programmed with channel hot electron programming and erased with Fowler Nordheim Tunneling at relatively high voltages.

Description

200421601 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates generally to a nonvolatile integrated circuit memory (nonvolatile integrated circuit memory), and particularly to a non-volatile and programmable read-only memory ( EEPR0M) and flash can be removed and programmable read-only memory (Flash Memory). [Previous Technology] The structure and application of the floating gate non-volatile memory (floating gate non-volatile memory) are well known, and there are three types of floating gate non-volatile memory: electrically programmable Read-Only Memory (EPROM), Erasable and Programmable Read-Only Memory (EEPROM) and Flash-Erasable and Programmable Read-Only Memory (Flash Memory), EPROM programming is electrically injected The charge from the floating gate to the floating gate of the EPROM is erased by ultraviolet light. The individual cells of the EEP ROM and flash memory (j? 1 ash memory) are similar in structure, but they are different. Organizations, EEPROM and flash memory can transfer the charge to the floating gate through a channel oxide layer through Channel Hot Injection or Fowler-Nordheim Tunneling. Programmatically, erasure of EEPROM and flash memory is usually achieved by a Furnohan tunneling effect through a channel oxide layer. The main application of non-volatile memory is permanent memory used in microprocessors or microcontroller systems. According to its evolution, the permanent program memory system of microprocessors is programmed by typical photomasks. MASK rom), and later by EPR 0 Μ, program memory modification needs to be implemented

Page 8 200421601 V. Description of the invention (2) The memory is changed by the body. Because the need to update the microprocessor program is more and more important, the byte-alterable EEPR0M (byte-alterable EEPR0M) with bit changes can be developed to provide system reproducibility. Written memory, in addition, because microprocessors and microcontrollers are becoming more and more common, when the power is turned off, 'requires permanent storage and will not fail or disappear. In most applications, the program will not It is often modified. However, relative data is often changed. The program memory (pr 〇grammem 〇ry) can be divided into: configuration, traceablity, startup program, or main program. program), data includes any information externally input to the system, such as ... applications, instruments, recorders, or sensor data needed for historical use or to maintain continuity of operation when power is turned off or power is lost Data memory (data 11 ^ 111〇1 ^) is often changed throughout the entire application life cycle. Program memory is usually built in flash memory. The memory size of flash memory is usually large, with 8KB (64K_bi (512K-bit) sectors as the unit. 七 工 一 " Stop / b On the other hand, the lean memory is usually built in EEPR0M, the necessary segment of EEPROM which is used for data memory, i * * r ·,, 'J is erased gj,, The erasing size (S1Ze) can be as small as a unit tuple (8bits), an early page (128-byte), or even the entire chip. The reprogrammability of Xiyuan Memory requires that the system = Permanent demand The non-volatile is determined by the energy period of the element during the life cycle of the application without the application of power, and the data of the component is accompanied by the application of the life cycle t. And data 200421601 V. Description of the invention (3) --- Sexual demand will be related to the failure rate, and the failure rate needs to be reduced, because the flash memory situation is applied to the program memory, which has the least number of reprogramming and the longest data retention And minimum durability (approximately 100,000) program / erase cycles ), On the contrary, EEPR0M applied to data memory must be capable of repeated modification and high durability (more than one million times programmed / erased). To achieve one million times programmed / erased and have unit tuples Single-byte erase segment. The traditional EEPR0M uses a very large cen size (approximately 100 times the smallest feature size of the technology). On the other hand, the flash memory has a long distance. Smaller unit size (approximately 丨 0 times the smallest feature size of the technology). In applications where data rate change is required, such as data memory, non-volatile memory requires faster Data change (program / erase) cycle. Therefore, EEPROM requires a write or program rate of 1 millisecond (ms). On the other hand, flash memory can tolerate a write rate in the order of 1000 milliseconds. 1 a to 1 d illustrate a conventional floating gate memory cell. A flash memory cell 10 is formed in a P-type substrate 2, a region 6 and an n + source region. 4) On this p-type substrate 2 A relatively thin gate dielectric or tunneling oxide 8 is deposited on the surface of the p-type substrate 2 and a poly-crystalline silicon floating gate 12 Channel oxygen formed above channel region 5 between drain region 6 and source region 4

Page 10 200421601

On the surface and surface of the shield 8, 'a polycrystalline silicon interlayer dielectric layer 4 is arranged on the floating gate 1 2' to separate the floating gate 12 from the second polycrystalline silicon layer forming a control gate 6 In most EEPR0M and flash memory applications, the p-type substrate 2 is connected to a substrate bias, most of which is the ground reference voltage (0v), and the source area 4 passes through the β through the source line & η ne terminal) 22 is connected to a source voltage generator 'control gate 16 through a word line terminal (word H ne terminal) 20 is connected to the control gate voltage generator, and the drain region 6 is connected through interlayer contact (ContaCt ) 24 is connected to the bit line, and then to a bit line voltage generator. The memory cell 10 is isolated from adjacent memory cells or IC circuits on the substrate by a shallow low trench isolation 26. The shallow trench isolation 26 provides a layer of isolation from any adjacent memory cells. As an interference signal. As is well known, the coupling coefficient between the control gate 16 and the floating gate 12 is the key to determine the flow of electricity to or from the floating gate. 2 The voltage applied to the two ends of the channel oxide layer 8 is the key, so it is hoped to maintain a relatively large floating Coupling coefficient of the gate 12, for this purpose, the floating gate 12 extends beyond the shallow trench isolation 26 to form what is commonly called wings 28, which makes the voltage applied to the control gate 16 relatively low, and The charge still flows to or leaves the floating gate 2; however, the wing limits the design of the memory cell 10 to a minimum size. According to the 4 矣 operation, the stylization of the 3 self-memory unit 1 Q applies a relatively high voltage (on the order of 10V) to the control gate "through the word line 20, and the drain voltage generator VD is set to a moderately high voltage. (On the order of 5 ¥), and the source voltage

200421601 V. Description of the invention (5) The generator VS is set to the ground reference voltage (0V). Due to these voltages, the channel 5 near the zone 6 will generate hot electrons. These hot electrons have enough energy to accelerate the passage through the oxide layer 8 of the channel. And trapped on the floating gate 12, trapped hot electrons will cause the threshold voltage of the field effect transistor formed by the memory cell 10 to increase by 3 to 5 volts. A change in the threshold voltage will cause the memory cell to be programmed to a logical zero (logic 0) from an unprogrammed state. Traditionally, the erasing of the memory cell is to set the word line 20 to a relatively large negative voltage (on the order of −18V), and the bit line 18 and the source line 22 are separated, so that the area 6 and the source area 4 float. On the other hand, the bit line 18 and the source line 22 are connected together, so that the drain region 6 and the source region 4 are connected to the ground reference voltage. In this case, there is a large electric field development across the channel region 5 On the channel oxide layer 8, the electric field causes the electrons trapped on the floating gate 12 to flow to the channel region 5, the drain region 6 and the source region 4, and then the electrons are removed from the floating gate by the Furnohan tunnel. 1 2 'Removed' The memory cell becomes erased (unprogrammed) due to the removal of trapped electrons, which causes the threshold voltage to change. If the memory unit is to be written into logic one, the memory unit is not programmed 'and no or very little negative charge is placed on the floating gate 12. Therefore, if the a memory unit is to be erased, a relatively large negative voltage is transmitted through The word line 20 is applied to the control gate 16 to make the memory cell 10 be over-erased. In fact, the positive charge is stored on the floating gate 12. This phenomenon causes the field effect transistor of the memory cell 10 to become Depletion-mode. In fact, drain region 6 and source region 4 will become short-circuited. When this happens, the selected memory cell will have over erased memory cell 1 on the same bit line on the array. 〇And misread the information, in order to overcome

Page 12 200421601 V. Description of the invention (6) dm as shown in Figures / 2a to 2c. 'A selective closed-circuit crystal (STx) 30 is arranged in the memory unit 10 and the source line body (STx) 30 is maintained at In the 0ff state, Tian ^ selects the gate day-day unit 10. jPrevent any overcurrent from flowing through the memory. Please refer to Figure 2a to Figure 20. Now, learn a memory unit. The memory unit 10 is formed in the _ " well 36, two = said that 1 is formed at -positioned at -p. Inside the n-type well 34 on the type substrate 2— & not zone (dra.nr eg, 〇n) 6 ^ _ n + (sour ur regl〇n) 4 ^^^ A layer 8 is deposited on the surface of the 15-type substrate 2. The upper gate f and the second gate 12 are formed on the surface of the layer 5 in the channel region 5 between the drain region 6 and the source region 4. A polycrystalline silicon interlayer dielectric layer " Arrange the spar layer to separate. The second sub-gate 12 and the formation-control room 16 are basically the second most. The source area 4 is the source area of the gate transistor 30, and the source area 38 of the gate :: body 30 is selected. The memory area 10 and the source area 6 and the source area * are simultaneously i I ^ ΓΛΐνΒ / 30 ^ ffi " i40 £ ^ ^ ^ ^ ^ ^ -ίο Top: Ά Select the source area 38 of the power source 30 The gate oxide layer 39 is formed between the gate oxide layer 39 when the passivation oxide layer 8 is formed; the source region 4 of the element 10 and the idler transistor 3 are selected. In the source area, select the gate electric body 30 to control the impact of the memory unit over-erasing. In most EEPROM or flash memories with a double transistor structure, page 13 200421601

V. Description of the Invention (7) :: Electricity 3 2; 6 even! It is biased at a substrate, and most of the cases are grounded. ^ Selecting the source region 38 of the gate transistor 30 through ί =: The voltage generator controls the gate 16 to cry through the word line terminal 20. Second: the device, The selection line 32 is connected to the selection signal production area (TfEM number to the gate 40 of the selection gate transistor 30), and the contact 24 between the drain port and the layer 24 is connected to the bit line 18, and a bit line voltage is generated The reverse connection of the main herJh has been recalled ^ 10 and the selection gate transistor 30 is isolated by a shallow trench (shal 1⑽: Γ:: -i〇n) 26 and adjacent memory cells located on the substrate or 1. = 二 _ The shallow shallow trench isolation 26 provides a layer of isolation to isolate any operational interference signals from the adjacent Z fe early element. As everyone knows and as mentioned above, the floating gate extends beyond the shallow trench isolation 26 to form a wing 28 The wing 28 makes the voltage applied to the control gate 16 relatively relatively, and makes the charge flow to and from the floating gate 12, however, the wing limits the design of the early element 10 to reach the minimum size. The program of the hidden unit 1 Q In the chemical system, the area 6 of the memory unit 10 is set, the voltage is + 15 · 0V or more, and the control gate 16 is set to the ground reference voltage. Voltage, the source area 4 is not connected to the source line, and is made floating to avoid leakage current. The voltage applied to the drain area 6 and the channel area 5 is connected to the bit line. Select the gate line 3 2 as the ground reference voltage, which will cause the high-voltage drain region 6 and channel region 5 to cause the charge to tunnel from the floating gate 2 to the Furnohan tunnel of the drain region 6. Traditionally, memory The erasure of the unit is to set the word line and the control gate to a bias voltage of about + 15 · 〇v ~ + 17 · 0V. The drain area 6 passes through the bit line is and the source area 4

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And the source line 22 is connected to the ground reference voltage, and a voltage of + 3 · 〇ν ~ + 5 · 〇ν is selected to be assigned. The bit line "Assures that the drain region 6 is set to the ground reference voltage. The memory unit of the structure is controlled by adding a control gate. Area to increase the coupling coefficient, other structures are effective and the memory unit, to help improve the memory unit to provide more gate transistors, to avoid the memory unit and bits from the bit line and source line. These and other structure examples As follows: The voltage of the gate 40 of the transistor 30 is isolated from other structures of the closely-coupled gate transistor, and is interfered with. By selecting the gate transistor 30 to ground, the known habits are tightly combined with the floating gate. Selecting the size, and the operation of the element line and source line memory unit Wu Guo Patent No. 6,3 70,08 No. 1 (Sakui, et al) discloses a selection circuit having a memory unit and two memory units sandwiching the memory unit Crystal non-volatile memory cell, a non-volatile memory cell with a $ control gate line, a non-volatile memory cell connected to a control gate line is formed: page (P age), one The sense amplifier with a latch function is connected to a bit line. In the data changing operation, the data of a page of memory cells is read to the sense amplifier and the data is sensed and stored in the sense amplifier. For page erasing, the programming of the data in the sense amplifier is in page 7C. Before repeating the programming, the data in the sense amplifier is allowed to be programmed as bytes or page data. Changes. 'Khan US Patent No. 6,400, 604 (Noda) teaches a non-volatile semiconductor memory element with a data reprogramming pattern. The memory has an array of memory cells and a selection based on page address signals. A page buffer for storing data to be paged into one page of the memory unit, the memory is more ^ = an internal row address generating circuit for generating a page address signal input page ^ 200421601 V. Description of the invention (9) The address is to pass the round material at f — Receive: Internal? The second solution generated by the address generation circuit: it is used to control the circuit with lean material repeating program mode, will; page Address signal; hard-range memory unit. Negative buffering "pages to the selected one-Wu Guo Patent No. 6,307, 78 No. 1 (Shum) provides a hybrid electric a turn. . Flash memory with tlNOR structure, floating gate transistor arrangement = election = electricity: between the body and an associated bit line, the flash memory is deposited on a triple well (^ rjple wei 1), And according to the Furnohan tunneling mechanism operation, the stylization of the memory unit involves the carrier tunneling from a channel region to the gate oxide layer to a floating gate, rather than tunneling from a drain or source region to Floating gate. U.S. Patent No. 6,212,102 (66 ° Factory No. 3, 055, 6131.) describes an EEPROM with a source-side selection of a double transistor memory unit (tw〇-transistc r memory ceiis), a programmed memory The voltage required by the unit is transmitted via a source line. U.S. Patent No. 6,266,274 (? 00! ^ 311 (11 :, 6:81.)) Relates to a non-volatile dual transistor memory cell having an N-type channel selection transistor and an N-type channel transistor The driving circuit of the memory unit includes a P-channel transmission transistor, and a transmission channel is connected to the front line of the memory unit. US Patent No. 6,174,759 (Verhaar, et al.) Teaches an EEPROM unit, which is provided with There is a high-voltage transistor similar to the selection transistor described in Figures 2a to 2c. The value of the p-type channel is different from that of the η-type well.

Page 16 200421601 V. Description of invention (ίο) Piezoelectric crystals are mostly made. Therefore, the floating gate memory unit in the US patent is closed to control the gate capacitance to the source region and the planar portion of the region and the gate. Coefficient with the memory unit. The US patent is the same as the invention. The OR memory planes are arranged in rows and columns. The memory blocks are connected to the non-regions and areas of a main source memory unit. It is because of the procedural memory unit. [Summary of the Invention] The purpose of the present invention is to limit the number of process steps to be combined into a flash by the same process steps as a P-channel logic transistor. 6,32 6,66 No. 1 (Dormans, et al ·) describes a type of 'which has a large capacitance surface between the control gate and the floating gate. Fortunately, the horse is roughly flat on the floating gate and at least the side wall portion of the floating gate, and ends on the selection gate. Fang, this patent provides a semiconductor element, which has a large capacitance dissipation between # system floating gates to increase: light 5,748,538 (Lee, describes a kind of bit array, a EEPR0M non-volatile The non-volatile memory line in the memory cell is similarly connected to a main bit line with the same bit writing ability (f, or & type) is a rich type or erasing the ability to forbid the electric writing Quickly this memory unit, in the same memory The source area of the unit is transparent in the memory block. A non-volatile material is selected in the row direction. Youhan tunneling pressure is applied to the non-exposed person and the flash memory array includes a block to control the non-volatile separation. Single method of source memory to achieve 1-way north broadcast

Single transistor of the memory = 200421601 V. Description of the invention (11) EEPR0M double transistor memory unit. Another object of the present invention is to provide a flash memory non-volatile memory cell with a single transistor, which has a floating gate with a low coupling coefficient, so that the memory cell can be downsized. Another object of the present invention is to provide a double-transistor EEPROM non-volatile memory unit, which has a floating gate with a low coupling coefficient connected in series with a small selection transistor, so that the memory unit can be reduced in size. Another object of the present invention is to provide a memory array in which a flash memory unit and an EEPROM memory unit can be integrated on the same substrate using the same process technology. In order to achieve at least one of these and other purposes, a non-volatile memory array is formed on a substrate. The non-volatile memory array has non-volatile memory cells arranged in rows and rows. Each non-volatile memory cell There is a source region and a drain region arranged on the surface of the substrate, the drain region is separated from the source region layout to form a channel region in the substrate, and a channel insulation layer is arranged between the source region and the drain region. On the surface of the channel region, a floating gate is arranged above the channel insulation layer, the floating gate is aligned with the edge of the source region and the edge of the drain region, and has a width defined by the width of the edge of the source region and the edge of the drain region A control gate is arranged above the floating gate, and is separated from the floating gate by a layer of interlaminar rims. The floating gate and the control gate have a relatively small coupling coefficient of less than 50%, without wings.玎 Reduce the size of non-volatile memory cells. The non-volatile memory in the parent row has a bit line connected to the drain regions of all non-volatile memory cells in the row of non-volatile memory cells. Similarly, every

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V. Description of the invention (12) A non-volatile memory sheet 70 has a source line connected to the source area of all non-volatile memory cells on the non-volatile memory cell, and the non-volatile memory array has one character. Line connects the gates of all non-volatile memory cells on each row of non-volatile memory cells °

In the case of non-volatile memory cells with single-crystal non-volatile memory cells, a non-volatile memory cell is programmed by first applying a moderately high positive voltage of about + 10V ~ + 12V to the connection On the sub-wire of the control gate of the selected non-volatile memory cell to place a charge on the control gate of the selected non-volatile memory cell, a medium positive voltage of about 5 V is applied to the selected non-volatile memory cell. The bit line of the drain region of the memory cell allows a medium-positive voltage to be transmitted to the source line connected to the source region of the selected non-volatile memory cell. The programming time of a single transistor flash memory cell with a moderately high jade gate voltage, a medium positive drain voltage, and a ground-referenced source voltage is between about 1 to 100 microseconds (// s). The erasing of a selected memory cell with a single transistor is to apply a very south negative voltage of approximately-1 5 V to-2 2 V to remove the negative charge from the floating gate to the control gate connected to the selected memory cell. Character lines.

Separate the source line connected to the source area of the selected memory unit and the character line connected to the drain area of the selected non-volatile memory unit, so that the source area and the drain area float, on the other hand, erase the When a non-volatile memory cell is selected, a ground reference voltage is applied to a source line connected to a source region of the selected memory cell and a character line connected to a drain region of the selected non-volatile memory cell. The erasing time of the memory unit is about 1 millisecond (mS) to 1 second.

% 19 I 200421601 V. Description of the invention (13) Non-volatile single-crystal flash memory array has non-volatile memory, and it has a gate transistor for dividing a bit line array structure, and the gate transistor A source region having a first metal line connected to a region of a transistor having a floating gate, the gate transistor also having a drain region connected to a main bit line by a second metal line, and a connection The gate of the _selection line receives the selection gate signal for selectively applying a one-bit line voltage signal to the non-volatile memory array. There is also a gate selection line. The gate of the gate transistor of each non-volatile memory cell connected to a row of non-volatile memory cells.

The programming of placing the charge on the control gate of the non-volatile memory cell is to first apply a moderately high positive voltage of about + 10V ~ + 12V to the word connected to the control gate of the selected non-volatile memory cell. Element line, a medium positive voltage of about 6 V is applied to the main bit line connected to the gate region of the selected non-volatile memory cell, so that the medium positive voltage 5 y is transmitted to the transistor with a floating gate In the drain region, a ground reference voltage is applied to the source line connected to the source region of the transistor with a floating gate of the selected non-volatile memory cell, and a very high positive voltage is applied to the selected non-volatile memory cell. The selection line of the gate of the transistor of the memory cell.

The time for programming the selected non-volatile memory cell after applying a very high positive selection gate voltage, a moderately high positive control gate voltage, a medium positive bit line voltage, and a ground reference voltage is approximately 1 to 100 microseconds ( V s). The erasure of the charge on the floating gate of the selected non-volatile memory cell is firstly applied a very high negative voltage of about -15V ~ -22V to the gate transistor connected to the selected non-volatile memory cell. Character line of control gate, select

200421601 Fifth invention description (14) The selection signal is set to ground reference voltage, and the gate transistor of the memory cell = σ is connected to the selected non-volatile, 丄 M <pole; the non-volatile memory is selected. The source line and the source line of the unit are connected to the bit line and the source area of the selected non-secondary transistor. x fe Early Yuan's Gate Transistor On the other hand, a ground-referenced lightning memory ... has a floating source of electricity, and the source of the gate connected to the selected non-volatile memory cell. Lines, and lines, non-volatile memory cells are erased and between the bits. ] Person, force 1 second (1 ^) to 1 second

[Embodiment] Sexual memory or the entire crystal memory often has more tuples that must have higher reprogrammed lines (erase). The body EEPR0M has bit line lines that traditionally remove interference and store data codes. (No piece) Changeable information used for storage and modification, such as the programming of data bits and the durability of erasure. In order to achieve the problem of programmatic interference with non-volatile memory cells that have not been selected during the erasing operation, It has been separated to avoid the other side. As mentioned above, the flash is non-volatile, because the bit of EEPR0M is changed to the block of flash memory (page code. Because EEPR0M is used to protect (data), so EEPR0M is used for many bit times. Therefore, EEPR0M must have a high durability of one million times. In high-voltage bit lines (stylized) and character interference must be eliminated, which leads to double The size of the transistor is very large and cannot be reduced, but it will not, in addition, the characters of the EEPR0M cell array are exempt from erasing the character lines of the unselected byte.

200421601 V. Description of the invention (15)-Memory is a single transistor non-volatile memory unit. Although it has a small memory unit, the programming and erasing time in units of blocks (b 1 ock) is relatively long. long. In order to reduce the size of the memory unit and provide an integrated flash memory and EEPROM design, the present invention provides a transistor in a non-volatile memory unit, which has a bit between the source region and the drain region, and the source region. The floating gates that are aligned with the edges of the pumping area are not heavy. In addition, the wings shown in Figures 1a to 1d and 2a to 2c have been deleted to lower the control gate and floating gate. The coupling coefficient and the reduced coupling coefficient require a higher control voltage to maintain the same efficiency of programming and erasing operations. Figures 3a to 3d illustrate a single transistor floating gate flash memory unit of the present invention. A non-volatile memory unit 100 is formed in a p-type substrate 102 and an n + drain region (drain region). ) 104 and a Π + source region 106 are formed in the p-type substrate 102. A relatively thin gate dielectric or tunneling oxide 108 is deposited on the surface of the p-type substrate 102, and a poly-crystalline silicon floating gate 112 is formed on A polycrystalline silicon interlayer dielectric layer 14 is arranged on the floating gate 1 12 on the surface of the channel oxide layer 108 on the channel area 105 between the drain region 104 and the source region 106. The gate 1 12 is separated from the first polycrystalline stone layer forming a control gate 1 16. The floating gate 112 is located above the channel area 105, and is restricted to align with the edge 110 of the drain area 104 and the source area 106. In addition, it does not have the wings 28, which are floating as shown in the id figure. The gate is limited by the width of the edge 1 2 8 of the drain region 104 and the source region 106, so its coupling coefficient (< 50%) is lower than that shown in graphs ia to id.

Page 22 200421601 V. Description of the invention (16) "-Non-volatile memory unit. In the application of the single transistor non-volatile memory single 7L of the present invention in a flash memory, the p-type substrate is connected to a substrate bias voltage, and most of the cases are ground reference voltage (0V), The source area 106 is connected to a source voltage generator through a source line terminal 讥 122, and the control gate i6 is connected to a control gate voltage generator through a word line terminal WL 120. The drain area 104 is connected through a layer The contact (c ο ntact) 1 2 4 is connected to the bit line 1 1 8 and then connected to a bit line voltage generator. f. The memory unit 100 is isolated from adjacent memory units or IC circuits on the substrate by a shallow trench isolation 126, which provides a layer of isolation to isolate interference signals from any operation of adjacent memory cells. In order to compensate for the lower coupling coefficient between the control gate 116 and the floating gate 丨 丨 2, the magnitude of the voltage applied to the control gate must be increased to maintain the same tunneling electric field when passing through the oxide layer 108 of the same thickness. And cause the charge to flow to or leave the floating gate 1 1 2 'in the single transistor flash non-volatile memory cell of the present invention' the programming and erasing voltage only needs a few volts, which is more than the conventional use of channel oxide layer (ETOX) The flash ROM technology EPROM is large, ETOX is a registered trademark of Indale Corporation. '' According to the operation of the non-volatile memory unit according to the present invention, as shown in FIG. 8 a 'The stylization of the memory unit 100 is to apply a relatively high voltage (on the order of + 10V to + 12V) through the word line 叽 120. ) On the control gate 116, the drain voltage generator is set to a moderately high voltage (on the order of 5V), so that the bit line Γ18 and the area 104 are set to a moderately high voltage, and the source voltage is generated as the ground reference. Voltage (0V) 'set the source line SL 112 and source area 106 to%

200421601 V. Description of the invention (17) Due to these voltages, hot electrons will be generated in the channel region 105 near the drain region 104 due to these voltages. These hot electrons have sufficient energy to accelerate the passage through the channel oxide layer 108 and trap. On the floating gate, the trapped hot electron will cause the critical voltage of the field effect transistor formed by the memory cell 100 to increase by 3 to 5 volts. The change in the threshold voltage caused by the trapped hot electron will cause The memory unit is never programmed to logical zero. The erasure of the single-crystal flash memory unit of the present invention is through the word line w: 1 20 Set the word line generator and control gate 6 to a relatively high negative voltage-

\ 5.〇V ~~ 22 · 〇V, preferably -18 · 〇V, the bit line voltage generator and bit line BL 118 can be separated from the source line generator and source line SL 122, so that the sink 104 And source region 106 'On the other hand, the bit line voltage generator and bit line BL 118 can be connected to the source line generator and source line SL i 22, so that 104 and source region 106 are connected to the ground reference voltage. Under the circumstances, a large electric field develops across the channel oxide layer ι0 of the channel area 105 so that the electron burial on the floating gate 112 is & Huadian 1 channel area 105. The electronic hunting from Ernuhan through the tunnel to pass Figure 4 illustrates from Figure 3a to Figure 3 (1 Figure ^ ^ ^ w ^ ^ ^ ^ ^ The application of a group of flash memory non-volatile memory cells i OO]. In the early crystal memory, the memory cell can be a P-type substrate for flash memory. A single group, however, its structure to the total triple well structure (trip 1 e we 1 1) shown in Figure W. One of them is a so-called plate, and smaller p-type wells are arranged in the Type 11 wells are formed in p-type base t wells.

200421601 V. Description of the invention (18) fe, early Yuan 1 Q 〇 In a relatively large P-shaft well, each of the array _ j μ under the array 20, 20 5 is formed in a separate p control gate connected to each character Each of the 14 lines 25a, ..., 225k on each column of a non-volatile memory cell 100, likewise, the array, view, ..., 23k: :: memory cell 10 °, the poles are connected to the -source The drain of the unit 100 is connected to the mother-nonvolatile memory 9r, 0βπ on the first mother row and the acceptor-metal bit line 255a ..... Z55m, 260a, ..., 26m. One bull and two 5 i Don't: The array can have vertical sub-arrays (not shown in the figure). In order to enter the two-step car train and control the array, individual bit lines 255a, ...,

Jbbin, 260a, ... n? Rrim 'ja 01 r ^ 1] 111 is connected to the main bit line 245a, ..., 245m, 250a,, 25 through the gate transistor 21〇 ... 210m, a 215m 〇m, the gate transistor 2 on each row of the array 10a ..... 210m, 215 & 215m are connected to the second metal main bit line 245a, ..., 245m, 25〇a, ... 25. m, each gate transistor 210a, ..., 21m, 215a, ..., 2 15m source is connected to the drain of each non-volatile memory cell 1000 on each row of the array, a The gate transistors 2 of block 200 or one block of two or more blocks of 200, 205 are connected to the selected gate line. The gates of 10a, ..., 210m, 215a, ..., 215m are connected to the selected gate line. The source lines 230a,…, and 230k of each block are connected to the main source lines 240a and 240 m respectively. Please refer to Figure 8a. The programming of the selected memory unit is like a single memory. According to the unit, a voltage is applied to a relatively high voltage (+1 〇) to a character line 225a ..... 225k containing a memory cell to be programmed (a plurality of memory cells on each character line can be programmed). · 〇V ~ + 1 2 · 0 V order of magnitude), brake

Page 25 200421601 V. Description of the invention (19) SG 220 and gate transistor 2 10a ..... 210m .............. The pole of the invention is set to a very high voltage (+ 1 5 · 〇V ~ + 2 2 · 0 V) to activate the gate transistor 2 1 Oa, ..., 2 1 Om, 2 1 5a, ..., 2 1 5m, which differs from the conventional technology by only about 10V Due to the very high voltage of the gate line SG 220, the idler transistors 210a ..... 210m, 215a ..... 215m can be made into similar components with a volume much smaller than the conventional one to save silicon area, including The second metal main bit line 245a on the line of the memory unit 丨 00, not, = 51; 25 / a / 25 0m is set to a moderate high voltage (on the order of 5V), the main source line 240a. .... 24〇m is set to ground reference voltage (0V), as mentioned earlier, this

Channel hot electron (CHE) charging of the floating gate of the selected non-volatile memory cell 1000 will be charged. _ Excluding selected non-volatile memory cells 1 00 (these cells are not programmed and set to erase state logic one) the main bit lines 245a, ..., 245m, 25 0a, ..., 250m are set to Ground reference voltage (OV), the gate line% 2 2 0 is set to a very high voltage to activate the bit line 255a ..... 25 5m ^ 260a… which does not include the selected non-volatile memory cell during the stylized operation , 2 0m on the gate transistor 2 l0a ..... 21m, 215a ..... Bits containing the selected non-volatile memory cell ... 26 unselected memory on 26 Unit 215m, therefore, is not located on the non-enclosed lines 255a, ..., 255m, 260a

The drain is set to ground reference voltage (0 V). The non-selected non-volatile memory cell on the word line 225a ..... 22 5k containing the selected non-volatile memory cell has its control gate set to a very high voltage (+1 0) during the stylized operation. · 0ν ~ + 12 · 〇v), the source of each non-volatile memory cell of the selected ^ unselected block is set as the ground reference

Page 26 200421601 V. Description of the invention (20) Voltage (0V). The bit line of the unselected non-volatile memory bit on the bit line 2 55a ..... 255m J 26〇a ..... 26 0m containing the selected non-volatile memory cell is not determined as Relatively high voltage is about + 5 · 0V. Because the gate and source of the transistor with floating gate are set to ground reference voltage (ov), it can avoid the occurrence of hot-electron phenomenon and interference. Non-volatile Memory unit. For these non-volatile memory cells that are not in the same block or sub-array of the selected non-volatile memory cells, their gate lines 2 2 0, word lines 22 5a ..... 22 5k, bit lines 255a ... ..255m, 26 0a ..... 2 6 0m, and source lines 230a, ..., 230k are set as ground reference voltages to avoid any interference signals in the secondary array. Erasing occurs in entire blocks or sub-arrays, basically as described in a single memory cell, for all word lines 225a ..... 225k in a sub-array set to a very high negative voltage (-15 · 0V ~ -22 · 0V), gate line SG 220 and gate transistor 210a ..... 210m, 215a ..... 2 1 5m gates are set to ground reference voltage (0V) to stop gate transistor 21 〇 a ..... 210m, 215a,…, 21 5m 'main bit line 245a,…, 245m, 2 50a,…, 2 50 ro are set to ground reference voltage (0v), sub array The main source lines 240a, ..., 240m and source lines 230a, ..., 230k are set to ground reference voltage (0V). As mentioned earlier, this will cause the Furnohan charge to tunnel, and the non-volatile from blocks 200, 205. The floating gate of the sexual memory unit 00 removes all electricity because all the non-volatile memory units of blocks 2 0, 2 and 5 are erased, so in blocks 2 0, 2 5 Non-selected non-volatile memory list

200421601 V. Description of the invention (21) yuan, not 4 These non-volatile memory cells in the same area, block or sub-array of the selected non-volatile memory cell, the gate line SG 22〇, the character line 2 2 5a .. ... 225k, bit line 2 55a, ..., 255m, 2 6 0a, ..., 2 60m, and source line 2 3〇a ..... 2 3 0 k is set as the ground reference voltage (〇v ) To avoid any interfering signals in the secondary array.

In the erasing with short time interval and the application that needs more durability (resistance to high number of programming and erasing), such as the most commonly used EEPROM, the dual transistor memory cell is the most suitable to avoid non-volatile The memory sheet το has been erased. Figures 5a to 5c illustrate the dual transistor memory unit of the present invention. The memory unit 100 is formed on a p-type substrate 102, an n + drain region 104 and an n + source. A region (source regen) 10 is formed in the p-type substrate 102. A relatively thin transport oxide layer (tunnel ng × xide) is deposited on the surface of the P-type substrate 102, and a polycrystalline silicon floating gate (p0ly- · crystalline siliC0n fl〇ating gate) n2 is formed at The channel oxide layer 108 above the channel region 105 between the region 104 and the source region 106 is closed. A polycrystalline silicon interlayer dielectric layer 丨 4 is arranged on the floating gate 丨 2 to place the # 2 is separated from the second polycrystalline silicon layer forming a control gate 丨 丨 6.

Basically, the drain region 104 is the source region of the gate transistor 丨 30. The drain region 138 of the gate transistor 130 is selected through a layer of contact (conntact) i24 connected to the line 118, and the gate transistor 13 is selected. The gate electrode 14 is arranged on the gate oxide layer 139 located in the drain region 104 of the memory cell 100 and the drain region 13 of the gate transistor 130, and the thickness of the oxide layer 139 of the idler element is greater than that of the floating $ π pieces. 100-channel oxide layer 108 is thick to resist deep during stylized operation

Page 28 200421601

Voltage across the components + 1 8. 0 V. When the oxide layer 108 is formed, a thicker gate oxide layer 319 is formed in the channel region between the source region 104 of the memory cell 100 and the drain region 138 of the gate transistor 130. The gate electrode 14 is connected to the selection control line 32, and transmits a selection signal to the selection gate transistor 30 to control the impact of over-erasing of the memory unit.

In most applications of EEPROM or flash memory with a dual transistor structure, the p-type substrate 102 is connected to a substrate bias. Most of the cases are ground-referenced voltage (0V). The drain region 138 is connected to the bit line voltage generator 6 V through the inter-layer contact (con tact) 124 and the bit line terminal 1 18, and the control gate 1 1 6 is connected to the control gate voltage via the word line terminal 1 2 0 as 'The selection gate line 1 3 2 is connected to a selection signal generator to provide a selection signal to the gate electrode 1 4 〇 of the selection gate transistor 130, the source area 106 is connected to the source line 122, and then to a source Line voltage generator.

Similar to Figures 3a to 3d, the single-crystal non-volatile memory cell 'floating gate 1 1 2 is located above the channel area 105, and is limited to the drain area 丨 〇4 and the source area 1 0 6 edge 1 1 0 alignment, in addition, it does not have wings 2 8 ′ as shown in Figure 丨 d, so that the floating gate is limited to the width of the edge 1 2 8 of the no area 1 0 4 and the source area 1 0 6 Therefore, its coupling coefficient (< 50%) is smaller than the non-volatile memory cells in Figs. 2a to 2C. As shown in Figure 8b, the programming of the memory unit 100 is based on the memory unit 100 and the pole 104. The set voltage is approximately + 5 · 0 V, and the control gate 116 is set to a relatively high positive voltage. (Approximately +10. 0V ~ + 12 · 0V), the source region 106 is set to ground and appears on the drain 1 0 4 and channel 1 0 5 + 5 · 0 V

Page 29 200421601 V. Description of the invention (23) Line Η 8 Ya · After selection gate transistor 丨 3 〇, gate 丨 4 〇 Through selection gate% 1 ^ 322 疋 voltage is about + 17〇v ~ + 22〇v This will generate the drain region ι04 to ask for electricity [, and the through-force region 105 will generate a channel hot electron programming, injecting electrons from the drain region 104 to the floating gate 丨 2. — The double-transistor EEPROM memory cell structure of the present invention is a proportional structure, because during the channel thermoelectronic programming, the selection of the gate transistor 30 requires the bit line 118 to be approximately +60 volts. Drain 104] You, 4 /, + 5 V / Therefore, the voltage difference (Vds) across the gate element 130 is only about-the low voltage (Vds) from the drain to the source of the gate element 130 Demand and bit 2 and the low voltage of 6V on the mountain and the main will not force the selection of the gate transistor 13 (3 has a higher red plate and the channel length, so a small gate element 130 can make n people 1 memory unit 100 With the same pitch width, it is now applicable to process technologies less than 0 · 1 3 / zm. The erasing of A -1 ^ ^ t is to set the word line and the control gate 1 1 6 to a bias voltage of 2.0V. The region 104 is maintained at the ground reference voltage level by selecting the gate transistor 13 and the source region 130, and the gate transistor is selected (the gate 140 is given a +-one voltage to ensure that the drain region 104 is set to be connected to the ground reference / 118). Electricity-A 1 彳. U4 ° is the ground test voltage. On the other hand, the bit line 118 and source line 122 can be forced to float. Ten-tone single Γ The figure says that Λ is from the non-volatile bitransistor of Figure 5c to Figure 5c: Early = A group of Γ ^ 100 ° formed by an EEPR0M array is arranged into a memory cell group: two: two, difficult, These unit groups are usually-bytes, /, 仃, in flash memory, the memory unit can be a

200421601 V. Description of the invention (24) As shown in Figures 3a to 3d, a single group of common p-type substrates is used. In the preferred embodiment, the memory unit groups 300a, ..., 300k, 305a, ..., 3 0 5k is formed on a p-type substrate without any triple wells, and the control gate of each non-volatile memory cell on each column of the array is connected to a word line 32 5a .. ... 3 2 5k, 32 7a ..... 3 2 7k. Similarly, the source of each non-volatile memory cell on each column of the array is connected to a source line 3 3 0a .. ... 3 30k, 332a, ..., 33 2k, the female non-volatile 5 hexadecimal unit 1 on each row of the array is connected to a bit line 3 4 5 a, ..., 345m , 350a, ..., 350m. Each memory cell group 3 0 0a ..... 3 0 0k, 30 5a ..... 30 5k each non-volatile memory cell 1 00 through the gate electrode of the memory cell i 0 〇 Connected to the main bit line 345a ..... 34 5m, 35 0a ..... 350m, the memory cell group on each column is 300a ..... 3 0k, 3 0 5a, ... In each of the memory cells of 305k, the gate of the gate transistor is connected to the selection gate line 320a ..... 32 0k, and each memory cell group is 300a ..... 30 0k, 305a, 305k source lines 330a, ..., 330k, 332a, ..., 332k are main source lines 340a and 340m, respectively. Please refer to Figure 8b. The programming of the selected memory unit is as described in the single memory unit. For the memory unit containing the memory unit to be programmed (in each selected memory unit group, multiple memories on each character line). Cells can be stylized). Character lines 325a,…, 325k, 327a, ..., 327k apply a voltage to a relatively high voltage (on the order of + 10.0V to + 12.0V). & Ji Yi Zaofan Group 300a, ^ ", 300k, 305a, ..., 305k gate transistor memory cell 1 00 gate set to very high voltage (+

Page 31 200421601

V. Description of the invention (25) Order of magnitude of 15 · 0V ~ + 22 · 0V) to activate the memory cell group 300a, ..., 30k, 30 5a ... 305k gate transistor The idle transistor of the memory cell 丨 〇〇, including the bit lines 345a, ..., 345m, 350a, ..., 350m of the selected non-volatile memory cell 100 is set to a moderately high voltage (on the order of 6.0V ), The main source lines 340a, ..., 340m are set to ground test voltage (0 V). As mentioned earlier, this will cause the hot electron charging of the channel of the floating gate of the selected non-volatile memory cell 100. Does not include the selected non-volatile memory cells 00 (these cells are not programmed, set to erase state logic one) bit line 345a, ..., 345m

3 5 0 a,…, 3 5 0 m are set to ground reference voltage, select the gate line 3 2 〇a,…, 320k to set to very high voltage (+ i50v ~ + 22〇v) to include the selected non-volatile Bit line 345a of the memory cell 100, ..., not 345m x 350a ..... The selection gate of the memory cell 100 on 3 50m, therefore, it does not include the selected non-volatile The position of the sexual memory unit-said unselected at 345a, ..., 345m, 35 0a ... 350m. The 7 ° line drain is set to ground reference voltage (0V). "Where the unselected non-volatile memory single control gate on the character line 3 25 &, ... containing 3, 2 5k, 3 2 7a, ... Set to a relatively high voltage (+ 10 · 〇V ~ + 12 · 〇v) and be selected $ ':

The source of each non-volatile memory cell in the selected block is set to = ^] voltage (0V). ★ Also refer to the unselected non-volatile memory bits on the bit lines 345a, ... 345m, 350a ..... 350m that contain the selected non-volatile memory cells: The drain is set to a relatively high voltage (+ 6 · 〇v), because it has a floating structure, its < Electric crystal 200421601 V. Description of the invention (26) The gate and source of the body are set to ground reference voltage (〇v), so channel heat can be avoided. The electronic phenomenon and interference are not selected non-volatile memory cells. 〇〇 /. For those non-volatile memory cells not in the selected memory cell group 300a, ..., 300k, 305a, ..., 30k, the selection gate Lines 32〇a, ..., 320k, character lines 325a, ..., 325k, 32 7a, ..., 32 7k, source lines 330a ..... 3 3 0 k, 33 2a ... 332k, and bits The element lines 345a ..... 345m, 350a, ..., 350m are set to ground reference voltage (0v) to avoid any interference in unselected memory cell groups 300a, ..., 300k, 305a, ..., 305k. signal. Erasing is to memorize the entire memory cell group 3 00a of the early element 100, ..., 300 k, 3 05 a, ..., 3 0 5 k or the memory cell group of the memory cell 3 0 0a. ..., 3 0 0k, 30 5a, ..., 3 0 5k groups occur basically as described in a single memory unit, in a selected memory unit 1 00 memory unit group 3 0 0a ..... 3 0 0k, 3 0 5a, ..., 30 5k character lines 325a, ..., 32 5k, 32 7a, ..., 327k are set to a very high negative voltage (-10.5V ~ -22 · 0V), which should be selected Memory cell group 3 0 0a ..... 3 0 0k, 3 0 5a ..... 3 0 5k selection gate line 320a ..... 320k and the gate of the memory cell 1 0 0 gate transistor The pole is set to ground reference voltage (0 V) to stop the switching transistor of the memory cell 100, the selected memory cell group 3 0 0 a,…, 30 0k, 30 5a, ..., 30 5k bits The lines 345a, ..., 345m, 350a, ..., 350m are set to ground reference voltage (0V), the main source lines 340a, ..., 34 0m and the selected memory cell group 30 0a, ..., 30 0k, 30 5a ... . 3 0 5k source line 33 0a ..... 330k, 332a ..... 332k is set as ground reference (0V), as described above, which may cause charge tunneling rich Ernuo Han,

Page 33 200421601 V. Description of the invention (27) From the selected memory unit group 3 00a ..... 3 0k, 3 0 5a ..... 3 0 5k non-transitory memory unit 1 0 0 The floating gate removes all charges. Since all non-volatile memory cells 1 0 0 of the selected memory cell group 30 0a ..... 3 0 0k, 3 0 5a ..... 3 0 5 k are erased, they are not selected as non-volatile. The same memory cell group 3 of the memory cell 1 00a. 3a 0k ..... 3 0 0k, 3 0 5 a ..... 3 0 5 k of these non-volatile memory cells, the selection gate 32 0a , ..., 320k, word lines 32 5a, ..., 32 5k, 327a, ..., 327k, and bit lines 345a, ..., 34 5m, 3 50a ... 350m are set to ground reference voltage (0 V) To avoid any interfering signals in the secondary array. Fig. 7 is a diagram illustrating the selection of a gate transistor 21〇a ..... 210m, 215a, ..., 215m of Fig. 4 or each of the non-volatile memory cells of Fig. 5a to Fig. 5c. The relationship between the channel width of the crystal 1 30 and the gate voltage of the selected gate transistor. The bit line voltage generator of the charge pumping circuit of a memory array sets the bit line to approximately 6 · 5 V. Voltage, which is based on the assumption that the memory cell requires an electrode voltage & v and an electrode current of 5 0 0 // A to perform the channel thermal electron programming under the assumption that the 'selected gate transistor is designed to have a channel length fixed as 〇.4 // m, This figure illustrates the minimum channel width required to provide the required conditions under different gate voltages. The figure shows that the control gate of a conventional non-volatile memory unit is set to 10V voltage, and its channel width must be 1 · 7 // m, however, the voltage applied to the control gate of the non-volatile memory cell of the present invention is increased to 20V, which enables the channel width of the gate transistor to be greatly reduced to only 0.45, making the selection Idle crystals are small enough to fit in memory cells Within pitch width

Page 34 200421601

(The width of a row of memory cells in an array or a column), a non-transistor non-volatile memory cell constructed in an EEPROM array includes a non-transistor single-crystal memory cell constructed in the flash memory array of the present invention The same memory cell structure, the two array structures use the same Furnohan tunneling erasure and channel hot electron programming method, 4 enables the proposed array structure and flash memory array structure to be integrated on the same product on the substrate Body circuit. Figures 9a and 9b illustrate the criticality of the non-volatile memory list of the present invention.

The voltage distribution is used as the reference threshold voltage during the read operation (VreM voltage is defined as the technical Rose of non-volatile memory cells) ~ the flat line between the logical division (Logic One) and the programmed (Logical Zero), because The amount of charge placed on the floating gate will be changed when the technical gate is reduced, and the sloping gate is removed or formalized. Therefore, ^% formalization ☆ 臾 中 碎 > \ — Here, the distribution of the boundary voltage of the non-volatile memory cell is as shown in the figure. ^ Y, the mouth does not contain an array of the selected non-volatile memory.掐 、 日 丨 丨 丨 丈 # Enough to detect whether the selected non-volatile memory cell should be selected. N: Contains non-volatile memory of the selected non-volatile memory μ knee ^ / boundary voltage (Vread), if the non-selected , S 涊 龉 a Nibe, ⑴4 breaks the non-volatile memory cell, which is turned on, the logic is detected, and the other too M τ σ-4, 1 For stylization, the selected non-volatile σ series zero is detected. I have recalled that the early is not connected, the logic

As stated in 耵, it has not been programmed (that is, the volatile memory unit may be changed to the contrary)-the non-volatile memory unit of the block non-volatile memory sheet may be over-erased and may also be over-erased. Remove the floating brake power of the speed memory unit n & & soil, non-solar body in enhancement mode (enhancement

200421601 V. Description of the invention (29) mode), and it is on at any time. This situation is not allowed in the single-crystal flash non-volatile memory cells in the first to the second figures. However, the 5a The non-volatile memory cell EEPR0M of the bi-transistor shown in Fig. 5c allows erasing the memory cell, and prevents the bit line current from flowing through the enhanced floating gate transistor to avoid data destruction of other memory cells. Special operations that are "correct ion", "repair", "recover", "converge" or "soft programming" (s〇ft — programming) are used in the memory unit The threshold voltage is adjusted back with reference to the threshold voltage (Vread). Because the single-transistor fast-crystal EEPR0M non-volatile memory cell of the present invention has the same application structure, the erasing time of the stylized flash memory is about several hundred. The specification is several milliseconds (mS). Two types of memory thermionic methods, therefore, The stylized time grid is in the range of 1 to 10 microseconds (#S). The non-volatile memory cell of the present invention is programmed to change the critical electrical time when Fernohan tunnels and removes the element from the floating gate. As shown by curve 95, the erasing time of the large-scale memory unit is approximately the time when the voltage is applied as described above. Please refer to Figures 11a to 11m. Set these over erase unless the volatile is set in the flash memory unit. The desired flash non-volatile memory unit and dual power use are the same as EEPR0M and flash memory and erasing time. In fact, milliseconds (mS), and the programming of EEPR0M product body is the same between channels. For current product specifications, please refer to Figure 10, which discusses the formulating and erasing time. The time for channel hot pressing is shown in curve 90. The charge is used to erase the nonvolatile memory unless stated in the volatile memory list. The duration of the recall unit is from about 1 to 10 microseconds (" S), and the non-volatile range is from 1 millisecond to 1 second. ’It ’s a discussion of non-volatile memory sheets

Page 36 200421601

The switching transistor 2 i 〇a ..... 210 ', 215 :: ..., 215m of Figure 1 and Figure 4 are non-volatile. Method for manufacturing gate transistor 1 30 of memory list 70. In this description, floating gate transistor 100 and selective gate transistor 130 have two polycrystalline silicon layers (a first polycrystalline silicon layer and a second polycrystalline silicon layer). ), But the control gate 116 and floating gate 112 of the non-volatile memory cell 100 are separated by the polycrystalline silicon interlayer dielectric layer 114, and the second polycrystalline silicon layer control gate and the first gate element 30 are selected. The polycrystalline silicon layer is short-circuited and there is no separation. For the floating gate transistor 100, the first polycrystalline silicon layer serves as a floating gate, and the second polycrystalline silicon layer serves as a floating gate.

To control the gate, the gate transistor 130 has a stacked gate structure, but the gate voltage is directly applied to the first polycrystalline stone layer.

Please refer to Fig. 11a, and prepare a P-type stone with a crystal structure orientation of < 100 >. The substrate 400 ′ is then formed on a silicon substrate 400 by thermally oxidizing or depositing an implanted oxide layer 40 2 having a thickness between about 100˜30 (ΰ), and then depositing a layer of photoresist 404 And by patterning the photomask in the 13th region of the gate transistor, the threshold voltage adjustment (Vt) and field distribution of 406 are performed in the 30th region of the selected gate transistor. P-type impurities ( p — type impurity) Adjust the threshold voltage of the gate transistor 1 3 0 and the on-state voltage of the field transistor, such as the side or I2 (BF2). The threshold voltage of the gate transistor 丨 3 〇 is approximately 0.6 ~ 1.5V. The threshold voltage of the field transistor is usually greater than 18V. The 130 Vt distribution energy of the gate transistor is selected between 5 and 50 KeV, and the boron ion dose is approximately 3x1 〇 " ~ 5χΐ 〇i2 i〇ns '/ cm2' selects the field distribution value of the gate transistor 130. The energy is about 30 ~ 1 80KeV, and the butterfly ion dose is about 1 χΐ 〇i2 ~ 1 χΐ 〇i4 丨 〇ns / cm2

Page 37 200421601 V. Description of the invention (31) The field distribution energy is greater than the selection gate transistor 丨 3 0Vt distribution energy, because the implanted ions must penetrate the field oxide layer. During programming, the selection The gate voltage is between 5 and 22V, which is higher than the word line voltage. Therefore, the field voltage needs to increase the threshold voltage of the field transistor to ensure that the field transistor does not conduct when the gate high voltage is selected.

After the photoresist 404 and the implanted oxide layer 402 are stripped off, as shown in FIG. 1 lb, a layer having a thickness of about [] ~ [00 ～ 30] is grown at a high voltage (HV) gate oxide f 408 thermally. On the silicon substrate 400, the silicon substrate 400 is patterned by the optical cell photolithography of the memory cell to form a photoresist 4 10, and the non-volatile memory cell transistor 100 is formed by a floating gate transistor 100 area. Threshold voltage adjustment (Vt) distribution value and field distribution value 4 1 2; the memory cell vt is implanted to adjust the threshold voltage of the non-volatile memory cell transistor 100, which is between 丨 · 〇 ~ 3 · 〇v The field distribution value is to increase the critical voltage of N-type field transistor (not shown) to more than 20 · 0V, and the non-volatile memory cell transistor 丨 〇〇Vt distribution energy is about 5 ~ 5 0 K e Between V, the dose of boron ions is approximately between χ 1 〇12 ~ lxl013ions / cm2, the field distribution energy is between approximately 30 ~ 18 KeV2, and the dose of nano ions is approximately between Klx101 ~ lx1041i. ns / cm2.

The high-voltage (HV) gate oxide layer 408 of the nonvolatile memory cell transistor shown in FIG. 11 d is removed, and then the photoresist 414 is removed. As shown in FIG. Between 90 0 to 1 100 t, the traditional dry oxidation method is used to thermally grow a channel oxide layer 416 with a thickness of about 70 to 120 μm on the silicon aa circle and grow in the selective gate transistor. The channel oxide layer 4 1 6 is thinner than the oxide layer grown in the non-volatile memory cell transistor region. This is because the high-voltage (HV) gate oxide layer 408 already exists in this region, and the channel oxides

Page 38 200421601 V. Description of the invention (32) The layer 4 16 and the high-voltage (ΗV) gate oxide layer 4 0 8 are combined to form a gate oxide layer of a selective gate transistor 1 30, whose thickness is about 15%. ~ 35 〇 again. Figure 11f of McCaw, followed by deposition of a first polycrystalline silicon layer 41 8 using a low-pressure chemical vapor deposition (LPCvd) method, with a thickness of approximately 1000-2000 A, and then a polycrystalline silicon layer 4 18 The first polycrystalline silicon layer is optically lithographically patterned, and the polycrystalline silicon layer 4 1 8 in the window region of the first polycrystalline silicon layer is removed. Then 'deposit a polycrystalline silicon interlayer dielectric layer 420 such as silicon dioxide using low pressure chemical vapor deposition (LPCVD), plasma assisted chemical vapor deposition (PECVD), or high density plasma chemical vapor deposition (HDPCVD). , Nitride stone, or oxide / nitride / oxide composite layer, or the use of thermal oxidation procedure (thermal oxidation procedure) can also be used to produce a silicon oxide layer. All methods produce a thickness of about 100 ~ 300. Then, as shown in FIG. 11g, a low-pressure chemical vapor deposition (lpcvd) method is used to deposit a second polycrystalline silicon layer 422 with a thickness of about 1500 to 3000 A. From the in-situ doping, add Shishen and scales to Shixiyan environment, or add a layer of Shixi tungsten layer (WSi) for the control gate of subsequent non-volatile memory cells, as shown in Figure 11h As shown. Next, the 'optical M shadow and reactive ion etching (reac ^ ive 丨 0 η etching, RIE) process is used to generate a stacked gate structure in the first polycrystalline layer dig and the second polycrystalline layer 422, and its cross section The schematic structure is shown in FIG. 111. The anisotropic reactive ion money engraving (RIE) process of the second polycrystalline silicon layer 4 2 2 and the first polycrystalline silicon layer 4 1 8 is performed by gas (Cl2). However, the polycrystalline silicon interlayer dielectric layer 420 is patterned with fluorine contained in CHF3. The stacked gate structure of the non-volatile memory cell 100 has a control structure formed by a second polycrystalline silicon layer 4 2 2

Page 39 200421601 V. Description of the invention (33) The interlayer dielectric layer 42 and the first polycrystalline layer 418 of the interlayer dielectric layer 418 and the first polycrystalline layer 418 are contaminated by the gate. 〖6 on. In Figure 11j of Cangkao, a layer of photoresistor 424 is deposited, and the memory cell photo is non-volatile. The photoresistor region το 100 is removed. Then, the photoresist is implanted into a non-volatile region to form a non-volatile process. The interface between the source area 428 and 3 430 of the memory unit, its energy is approximately between 30 ～ 60 KeV, arsenic ion ^: approximately between ιχ1 (Ρ ～ 7xl0 丨 51〇ns / cm2, non-volatile The large memory area 430 interface is a steep interface to improve the channel's collision of hot electrons. The ion implantation of the memory unit 426 is to be in the memory unit area = = doped area _ interface. In addition, non-volatile The source area of the memory unit 428 gate i4 田 3 = floating medium and / or volatile memory unit 1⑽ floating control and control, the edges of the stack vertical gate structure are aligned, as shown in Figure 3d, the stack j fork is limited to Shallow trench isolation that defines the boundary of the non-volatile memory cell ('. No). As shown in Figure 1 lk, select the drain region 436 of the gate transistor 丨 3 = two non-volatile memory cell region The 430 interface maintains a high interface collapse ^ Φ = pressure, on the other hand, it is not desirable to approach the drain region of the selection gate transistor 丨 30 In the case of impact ionization, the junction between the drain region 436 of the gate transistor 13 and the junction 43 () of the non-volatile memory cell has different doping concentration points. The gate transistor drain region 36 is selected, and 434 is implanted with phosphorus ions, the energy of which is about μ ~ 15〇 [", the ion dose is about 1 × 1014 ~ 2x1015inns / cm2, The planting 434 produces a double-diffused drain region in the gate region of the selective gate transistor 130. The “π junction” is the double-diffused drain region. 00) The 436 junction is higher than that of the non-volatile memory cell. Page 40 200421601 V. Invention Note (34) that the region 430 is connected, and the mask has a slower doping concentration distribution. As shown in the figure 1 1 1 'by low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition The method (pecvD) is used to deposit an insulating layer with a thickness between about 100 and 2000 to form an insulating spacer 4 3 8 '. Then, a fluorine-based compound (cf4) is used as an etching solution to perform reactive ions. # 刻 （RIE） process, and then the source / drain N + implantation 440 is performed by the ion implantation process, and its energy Approximately between 30 ～ 60 KeV, and arsenic or phosphorus ion agent i is between approximately 5 × 1014 and 1 × 10 μ6 ions / cm2, so as to reduce the series resistance of the source / subzone 442, 444, and 446. Next , By means of low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition (PECVD) deposition of an interlayer dielectric layer (ILD) with a thickness of about 800 ~ 150 0 0A 'It is composed of silicon dioxide, and the interlayer dielectric layer (I LD) completely fills the space between the stacked gate structures 2. The planarization of the interlayer dielectric layer is completed by a chemical mechanical planarization (CMP) process, so that the interlayer dielectric layer has a smooth upper surface shape: 'reducing the subsequent openings for the source / drain regions. Difficulties in the optical lithography process 2 The surname Λ solution, such as CHF4, reacts to the layered dielectric layer (ILD). The contact openings are generated by using tungsten gaseous tungsten gas under low pressure: == LPCVD) or RF sputtering. Shoot mine _. Metal layers (such as towns) between ~ 4_A, complete gas 2 are removed by chemical mechanical planarization (CMP) process or by chlorine interlayer & power bank (1LD ^ reactive reactive ion etching (rie) process) Source &; P \ / Yan layer, the crane plug (Tungsten plug) to raise the Q,> and the electric contact of the multi-gate gate, shoot the mine by Shecheng

Page 41 200421601 V. Description of the invention (35) &quot; -------- (RF sput ter i ng) Shen Yan & ^ 0 m eight s ® λ slave layer with a thickness of about 3 0 0 0 ~ 80 0 The metal layer between OA, such as aluminum, is used as a flame &amp; .. ', Ma-metal interconnects (metal interconnects) 〇 Select the mask crystal of the gate transistor <隹 $ gate structure (418, 420, 422) There is a gate connected to 4ZZh, as shown in Fig. 6, which is called M and ΛΛ "320 a ..... 320k first multi-day Shixi layer gate External connection green, .. ^ L,. ^ 〇a ^ ,,, Uexternal connection), the non-volatile nature shown in Figure 5 has been thinking about the early element and selection &quot; The process steps of the crystal can be performed by any current semiconductor process corresponding to π and King of t, and it is applicable to future steps. The reliability issues related to high voltage can be selected by the field. The cell structure parameters such as channel length, gate oxide thickness, and shallow trench isolation depth are optimized and controlled. A current semiconductor device of a nand type array flash non-volatile memory cell is optimized. It has been proved to be very guilty, the process can be maintained above 20v, and has a durability of more than one million times, which is sufficient to manufacture the non-volatile memory unit of the present invention. The change of the process is as follows As shown in Figure 12a to Figure 12C, this change is a self-aligned process, in which the first polycrystalline silicon layer automatically contacts the field oxide layer and the source area of the non-volatile memory cell 100. Align the width of the drain region (as shown in Figure 3d) to reduce the width of the non-volatile memory cell. After the first polycrystalline silicon layer 4 1 8 is deposited, the shallow trench shown in Figure 3d is isolated 1 2 6 The first polycrystalline silicon layer 4 1 8 is automatically aligned with the active edge of the non-volatile memory cell in Figure 12a. The first polycrystalline silicon layer 418 can be deposited and formed by a well-known process. Such as low pressure chemical vapor deposition (LPCVD) or plasma-assisted chemical vapor deposition

Page 42 200421601 V. Description of the invention (36) method (PECVD), so that a polycrystalline silicon layer with a thickness of about 500-650 A is formed on the channel oxide layer, so as to reduce the thickness of the layer. CVD method deposits a layer of silicon nitride (Si ^ phase sinking) with a thickness of preferably about 1 500i. When isolation is formed, an active area mask is used for the boundary ^ / con area. A layer of photoresist is applied on top of the selected region to perform the chemical process, etching the silicon nitride, the first polycrystalline silicon layer and the underlying insulating layer. It is insulated below and not above, where the photoresist is stripped, silicon nitride, first polycrystalline silicon ^ remains in the insulating layer and is etched away. There are two methods for forming the isolation area: silicon ^ = 了 面 ( L0C0S) method and shallow trench isolation (STI) method, in shallow trench isolation (ST ^: oxidation etching extends into the substrate to a depth of about 2800 ~ 3200i, silicon trench = medium, silicon dioxide insulation material, In this area, a well-known silicon region g, a full field (L0C0S) method can be used to form a local field oxide layer or a shallow trench isolation method (STi), and a stone oxide layer is preferred. The shallow trench is formed, so it is desirable to use the shallow '^ — method, because it can form a flat layer with respect to the first polycrystalline stone layer 418, which is absolutely volatile, and the unit of the floating gate 418 of the 00! Align the source area and the non-recoverable area of the memory cell 1000. After the formation of the isolation region, use the low pressure chemical vapor deposition (LPCVD), plasma-assisted chemical vapor deposition (pEcvD), Or high-density electrical = chemical vapor deposition (HDPCVD) deposition-a layer of polycrystalline silicon interlayer dielectric layer 420 such as silicon oxide, silicon nitride, or an oxide / nitride / oxide composite layer, or it can be used Thermal oxidation 〇xidati⑽

PrOCedUrf) produces oxidized debris, and the thickness produced by all methods is about 100 ~ 300A, as shown in Figure 12a. Then, the inter-crystalline silicon interlayer dielectric

Page 43 200421601 V. Description of the invention (37) The layer 420 is patterned with an oxide / nitride / oxide (ON) mask, as shown in Figure 12b, using a fluorine compound (CHFx) anisotropy Reactive ion etching (RIE) process to remove the selected gate transistor. The polycrystalline silicon interlayer dielectric layer 4 20 in the region 30 is then deposited using a low pressure chemical vapor deposition method (LpcvD) as shown in FIG. A second polycrystalline silicon layer 4 2 2 between 1 500 and 3 00 ×. In addition, arsenic and phosphorus are added to the silane environment by in-situ doping during the deposition process, or a tungsten silicide layer is added. (WSi), for the control room of the subsequent non-volatile memory unit 100. Next, the 'optical lithography and reactive ion etching (R 丨 E) process is used to generate a stacked gate structure (418, 42.0, 4 2 2) with a cross-sectional view as shown in FIG. 12c, and a second polycrystalline silicon layer is deposited. 4 2 2 so that it is directly in electrical contact with the first polycrystalline silicon layer 4 1 8 to form a gate electrode of the selective gate transistor 3 30. The two single and dual crystal non-volatile memory cells provide a scalable memory array that can be used for flash memory or EEPROM using the same non-volatile memory cell structure, which makes flash memory and EEPR. M can be combined into discrete memory or implanted memory in a integrated circuit for flash memory and EEPR0M single and double crystal non-volatile memory cells, using the same non-volatile memory The manufacturing technology and the erasing method have equivalent performance. The non-volatile memory unit of the present invention has the advantages of small chip size, high durability, and high elasticity. ^ The present invention has been particularly shown and described, and those skilled in the art should understand that any form and detail of the invention can be changed without departing from the spirit of the invention and the scope of patents.

Page 44 200421601 Brief description of the diagram: Yuan: i: 2 Figure 种-A kind of non-volatile floating gate memory unit of a single-transistor: Ι 疋 Figure of a conventional non-volatile floating gate memory unit of a double-transistor Schematic diagram of the array;: Single: ΐ :: plane τ-a non-volatile floating gate of the single-transistor of the present invention, Figure 4 / non-volatile memory of the single-transistor of the present invention: 5: Figure I *:] 5 : Ξ is a non-volatile floating gate of a bi-electric transistor according to the present invention, "a diagram of Si Zao Yuan; Fig. 6 is a schematic diagram of an array of non-volatile memory cells of a bi-electric crystal according to the present invention; Fig. 7 It is the relationship diagram between the channel visibility of the selective gate transistor and the voltage of the selected gate signal of the non-volatile memory cell of the double-transistor of the present invention; FIG. 8a is a diagram describing the formatting and erasing of the non-volatile of the flash memory of the present invention Voltage level table of the memory unit; ° Figure 8b is a table describing and erasing the electric dust level table of the EEPR0M non-volatile memory unit of the present invention; Figures 9a and 9b are the non-volatile memory of the present invention Figure of critical voltage division of unit programming and erasing; Figure 10 is the critical voltage of the non-volatile memory cell of the present invention. The relationship between pressure and time ’is used to determine the programming and erasing operation time of the non-volatile memory unit of the present invention; FIG. Ua to FIG. 11m are cross-sectional views of a substrate for explaining the present invention.

Page 45 200421601 The diagram briefly explains the formation steps of the transistor non-volatile memory unit. Figures 12a to 12c are cross-sectional views of a substrate for explaining the additional steps of forming the non-volatile memory unit of the electric double crystal of the present invention. . [Simple description of element symbols] P-type substrate 2 n + source region 4 channel region 5 ΙΊ +; and region 6 gate dielectric layer, channel oxide layer 8 m flash memory cell 1 0 floating gate 1 2 polycrystalline silicon interlayer dielectric layer 1 4 Control gate 1 6 Word line terminal, word line 20 Source line terminal, source line 2 2 Interlayer contact 24 Shallow trench isolation 26 Wing 28 Select gate transistor (STx) 30 _ Select gate line 3 2 η well 34 ρ-type well 36 source area 3 8

Page 46 200421601 The diagram simply illustrates the gate oxide layer 3 9 gate 4 0 curve 9 0 curve 9 5 non-volatile memory cell, floating gate element, floating gate transistor, memory cell transistor 1 0 0 p-type Substrate 102 n + and region 1 0 4 channel region 105 n + source region 1 0 6 # gate dielectric layer or channel oxide layer 108 edge 11 0 polycrystalline silicon floating gate 11 2 polycrystalline silicon interlayer dielectric layer 11 4 control gate 11 6 bits Line BL, Bit line terminal, Bit line 11 8 Word line terminal WL, Word line terminal, Word line WL 1 20 Source line terminal SL, Source line SL, Source line 1 2 2 Interlayer contact 124 Shallow trench isolation 1 2 6 'Edge 1 2 8 Select gate transistor, gate element 1 3 0 Select control line, select gate line, select gate SG 1 32 No area 1 3 8

Page 47 200421601 The diagram briefly illustrates the gate oxide layer 1 3 9 gate 1 4 0 block or sub-array 2 0 0, 2 0 5 gate transistor 2 1 0 a, ..., 2 1 0 m, 2 1 5 a, ..., 2 1 5 m Select gate line SG, gate line 220 character line 22 5a ..... 22 5k source line 230a ..... 2 30k main source line 240a, 240m second metal main bit Line 245a ..... 245m, 250a ..... 250m First metal bit line 255a, ..., 255m, 260a, ..., 260m Memory cell group 3 0 0a ..... 30 0k, 305a ... ... 30 5k gate line 320 Select gate line 320a ..... 320k character line 32 5a ..... 325k, 327a ..... 327k source line 33 0a, ..., 330k, 3 32a .. ... 332k main source line 34 0a, ..., 340m bit line 345a, ... ^ 345m, 350a, ..., 350m P-type silicon substrate 400 implanted oxide layer 4 0 2 photoresistor 404 layout value 406 high voltage (HV ) Gate electrode layer 408 Photoresistor 410 Distribution 412

Page 48200421601 Illustration of the photoresist 4 1 4, Channel oxide layer 416 First polycrystalline silicon layer, floating gate 4 1 8 Polycrystalline interlayer dielectric layer 4 2 0 Second polycrystalline silicon layer 4 2 2 photoresist 4 2 4 ion implantation 426 source area 4 2 8 &gt; and area 4 3 0 photomask 432 k implantation area 434, double diffusion area 436 insulation spacer 438 implantation 440 source area 442 and area 4 4 4 &gt; and zone 4 4 6

Page 49

Claims (1)

200421601 VI. Scope of patent application 1. A non-volatile memory unit formed on a substrate, including: a floating gate arranged above a channel area of the memory unit, and located in a source area of the memory unit and a Between the drain areas, the floating gate is aligned with the edge of the source area and the edge of the green area, and has a width defined by the width of the edge of the source area and the edge of the green area. 2. The non-volatile memory unit according to item 1 of the patent application scope, wherein the memory unit has a relatively small capacitance formed by a control gate disposed above the floating gate, the floating gate and the floating gate. Control the coupling coefficient of the total capacitance of the gate. 3. The non-volatile memory cell according to item 2 of the patent application scope, wherein the coupling coefficient is less than 50%. 4. The non-volatile memory cell described in item 2 of the scope of patent application, wherein the programming of the non-volatile memory cell is to place a charge on the floating gate, and the steps are as follows: Apply a moderately high positive voltage to The control gate; applying a medium positive voltage to the green zone; and applying a ground reference voltage to the source zone. 5. The non-volatile memory cell according to item 4 of the scope of patent application, wherein the moderately high positive voltage is between approximately + 10V and + 12V. 6. The non-volatile memory cell according to item 4 of the scope of patent application, wherein the medium positive voltage is approximately + 5.0V. 7. The non-volatile memory cell according to item 4 of the scope of patent application, wherein the time for applying the moderately high positive voltage, the medium positive voltage, and the ground reference voltage is about 1 to 100 microseconds (// S )between. Page 50 200421601 6. Application scope of patent 8. The non-volatile memory unit described in item 2 of the scope of patent application, wherein the erasing of the memory unit is to remove the charge from the floating gate, and the steps are as follows: A very high negative voltage is on the control gate; 9. The non-volatile memory cell as described in item 8 of the scope of the patent application, wherein the very high negative voltage is between about -15 V to -2 2 V. 10. The non-volatile memory unit as described in item 8 of the scope of patent application, wherein erasing the memory unit further includes the following steps: Separating the source region and the> and region 'to make the source region and the> and region float. Home. 11. The non-volatile memory cell according to item 8 of the scope of patent application, wherein erasing the memory cell further includes the following steps: applying a ground reference voltage to the source region and the no-region. 1 2. The non-volatile memory unit according to item 8 of the scope of patent application, wherein the time for erasing the memory unit is between about 1 millisecond (ms) and 1 second. 1 3. The non-volatile memory unit according to item 2 of the scope of patent application, further comprising a gate transistor having a source region connected to the drain region, a drain region, and a selection gate signal to A bit line voltage signal is selectively applied to the gate of the drain region. 14 4. The non-volatile memory unit as described in item 13 of the scope of the patent application, wherein the programming of the non-volatile memory unit places the charge on the floating gate, and the steps are as follows: Apply a moderately high positive Applying a voltage to the control gate; applying a medium positive voltage to the dead zone; applying a very high positive voltage to the gate of the gate transistor; and Page 51 200421601 6. Scope of patent application Apply a ground reference voltage to the source area. 15. The non-volatile memory cell as described in item 14 of the scope of patent application, wherein the moderately high positive voltage is between + 10V ~ + 12V. 16. The non-volatile memory cell according to item 14 of the scope of patent application, wherein the medium positive voltage is approximately +5.0 V. 1 7. The non-volatile memory cell according to item 14 of the scope of patent application, wherein the very high positive voltage is between about + 15V to +2 2V. 1 8. The non-volatile memory cell according to item 14 of the scope of patent application, wherein the time for applying the very high positive voltage, the moderately high positive voltage, the medium positive voltage, and the ground reference voltage is about 1 ~ 1 0 between 0 microseconds (// s). 19. The non-volatile memory cell as described in item 13 of the scope of patent application, wherein the erasing of the memory cell is to remove the charge from the floating gate, and the steps are as follows: Apply a very high negative voltage to the Controlling the gate; and applying a ground reference voltage to the selection gate. 2 0. The non-volatile memory unit described in item 19 of the scope of patent application, wherein erasing the memory unit further includes the following steps: Separating the source region and the &gt; and region 'such that the source region and the> and Area floating. 2 1. The non-volatile memory cell according to item 19 of the scope of patent application, wherein erasing the memory cell further comprises the following steps: applying a ground reference voltage to the source region and the drain region. 2 2. The non-volatile memory unit according to item 19 of the scope of patent application, wherein the time for erasing the memory unit is between about 1 millisecond (ms) and 1 second. 2 3. A non-volatile memory array formed on a substrate, including: Page 52 200421601 6. Scope of patent application: Multiple non-volatile memory cells are arranged in rows and columns. Each non-volatile memory cell includes: a source area arranged on the surface of the substrate; a drain area arranged on the surface of the substrate; The substrate surface is separated from the source area by a distance; a channel insulation layer is arranged on the substrate surface of the source area and a channel area between the source area and the source area; a floating gate is arranged on the channel insulation Above the layer, the floating gate is aligned with an edge of the source region and an edge of the non-region, and has a width defined by the width of the edge of the source region and the edge of the drain region; and a control gate, arranged at Above the floating gate, and separated from the # floating gate by an insulating layer; a plurality of bit lines, each bit line connecting the drain region of all non-volatile memory cells on a row of non-volatile memory cells ; A plurality of source lines, each source line connecting the source region of all non-volatile memory cells on a row of non-volatile memory cells; and a plurality of character lines, each character line connecting a row of non-volatile memory cells This control gate has a non-volatile memory cell. 2 4. The non-volatile memory array according to item 23 of the scope of the patent application, wherein each memory cell has a relatively small capacitance formed by the control gate and the total capacitance of the floating gate and the control gate Coupling coefficient. ^ 2 5. The non-volatile memory array according to item 24 of the scope of patent application, wherein the coupling coefficient is less than 50%. 2 6. The non-volatile memory array according to item 24 of the scope of the patent application, wherein one of the selected non-volatile memory cells is programmed to place a charge in Page 53 200421601 VI. Scope of patent application The floating gate of the selected non-volatile memory unit, the steps are as follows: Apply a moderately high positive voltage to the control gate of the selected non-volatile memory unit. Word line; applying a medium positive voltage to the bit line connected to the drain region of the selected non-volatile memory cell so that the medium positive voltage is transmitted to the drain region; and adding a ground reference voltage to the The source line of the source area of the selected non-volatile memory cell. 27. The non-volatile memory array according to item 26 of the scope of patent application, wherein the moderately high positive voltage is between about + 10V and + 12V. 2 8 · The non-volatile memory array described in item 26 of the patent application, wherein the medium positive voltage is approximately 6V, so approximately 5V is applied to the diode 29 · as described in item 26 of the patent application The non-volatile memory array, wherein the moderately high positive voltage, the medium positive voltage, and the ground reference voltage are applied for a time between about 1 to 100 microseconds (/ z S). 30. The non-volatile memory array as described in item 24 of the scope of patent application, wherein one of the selected non-volatile memory cells is erased to remove the charge from the floating gate. The steps are as follows: A high negative voltage is applied to the word line connected to the control gate of the selected non-volatile memory cell. Ο 1 • The non-volatile memory array described in item 30 of the scope of patent application, wherein the very high negative voltage is between approximately 15V and -22V. 〇 〇 • As for the non-volatile memory array described in item 30 of the scope of patent application, "the erasing of the selected non-volatile memory unit further includes the steps as follows: ·· Page 54 200421601 6. The scope of the patent application 7 open the source line connected to the source area of the selected non-volatile memory unit and the bit line connected to the drain area of the 4 selected non-volatile memory units, making the source The area and the no area are floating. 33. The non-volatile memory array as described in item 30 of the scope of patent application, wherein erasing the non-volatile memory unit further includes the following steps: Applying a ground reference voltage to the selected non-volatile memory unit The source line of the 5th source area and the bit line connected to the area of the selected non-volatile memory cell. The non-volatile memory array according to item 30 of the claim, wherein the time for erasing the memory unit is between about 1 millisecond and 1 second. 35. The non-volatile memory array as described in item 24 of Shenyan's patent scope, wherein the non-volatile memory unit further includes a source region of a sum zone, and a selective gate signal connected to the non-volatile memory unit to selectively A bit is applied; and the gate transistor has a drain region connected to the element line and a gate connected to a selected element line voltage signal in the drain region. The non-volatile memory array further includes a plurality of select lines, each A selection line is connected to the gate of the gate transistor of each non-volatile memory cell on a row of non-volatile memory cells. 36. The non-volatile memory array described in item 35 of the scope of the patent application, and / or the programming of the non-volatile memory unit is to place a charge on the floating space, and the steps are as follows: A moderately high positive voltage on the word line connected to the control gate of the selected non-volatile memory cell; 200421601 VI. Patent application scope% plus one medium and equal positive voltage on the bit line connected to the drain region of the selected non-volatile memory cell, so that the medium positive voltage is transmitted to the drain region; apply a ground reference voltage The source line connected to the source area of the selected non-volatile memory unit; and the selection line applying a very high positive voltage to the gate electrode of the sun-body of the selected non-volatile memory unit . 37. The non-volatile memory array according to item 36 of the scope of patent application, wherein the moderately high positive voltage is between about + 10V and H12V. 38. The non-volatile memory array according to item 36 of the patent application, wherein the order of the positive voltage is about 6V, so about 5V is applied to the drain region. 39. The non-volatile memory array according to item 36 of the scope of patent application, wherein the very high positive voltage is between about + 15V and + 22V. 40. The non-volatile memory array according to item 36 of the scope of patent application, wherein the time for applying the very high positive voltage, the moderately high positive voltage, the medium positive voltage, and the ground reference voltage is about 1 to 10 Between 0 microseconds (// s). 41. The non-volatile memory array according to item 35 of the scope of patent application, wherein the erasing of the memory cell is to remove the charge from the floating gate, and the steps are as follows: Apply a very high negative voltage to the The word line of the control gate of the selected non-volatile memory cell. A ground reference voltage is applied to the selection line connected to the gate of the gate transistor of the selected non-volatile memory cell. Page 56 200421601 6. Application for patent scope 4 2. The non-volatile memory array as described in item 41 of the patent application scope, wherein erasing the memory unit further includes the following steps: Separately connecting to the selected non-volatile memory The source line of the source region of the memory cell and the bit line connected to the drain region of the selected non-volatile memory cell. 4 3. The non-volatile memory array according to item 41 of the scope of patent application, wherein erasing the memory unit further includes the following steps: applying a ground reference voltage to a source connected to the selected non-volatile memory unit The source line of the region and the bit line connected to the drain region of the selected non-volatile memory cell. 44. The non-volatile memory array according to item 41 of the scope of patent application, wherein the time for erasing the memory unit is between about 1 millisecond (ms) and 1 second. 4 5. A method of operating a non-volatile memory array, including the following steps: forming the non-volatile memory array on a substrate, the forming including the following steps: a plurality of non-volatile memory cells are arranged in columns and rows, Each non-volatile memory unit includes: a source region arranged on the surface of the substrate; a drain region arranged on the surface of the substrate spaced apart from the source region; a channel insulation layer arranged in the source region And a substrate surface of a channel region between the drain region; a floating gate arranged above the channel insulation layer, the floating gate is aligned with one edge of the source region and one edge of the drain region, and has A width defined by the width of the edge of the source region and the edge of the drain region; and Page 57 200421601 VI. Patent application scope A control gate is arranged on the floating gate and separated from the floating gate by an insulating layer; a plurality of bit lines, each bit line is connected to a row of non-volatile Drain regions of all non-volatile memory cells on a non-volatile memory cell; multiple source lines, each source line connecting the source regions of all non-volatile memory cells on a row of non-volatile memory cells; and multiple character lines, each The word lines are connected to the control gates of all non-volatile memory cells in a row of non-volatile memory cells. To program a selected non-volatile memory cell, the charge is placed on the floating gate of the selected non-volatile memory cell. The steps are as follows: Apply a moderately high positive voltage to the selected non-volatile memory. The word line of the control gate of the unit; applying a medium positive voltage to the bit line connected to the drain region of the selected non-volatile memory cell so that the medium positive voltage is transmitted to the drain region; and applying a ground reference The voltage is applied to a source line connected to a source region of the selected non-volatile memory cell. 46. The method according to item 45 of the scope of patent application, wherein each memory unit has a relatively small coupling coefficient between the capacitance formed by the control gate and the total capacitance of the floating gate and the control gate. 4 7. The method according to item 46 of the scope of patent application, wherein the coupling coefficient is less than 50%. 48. The method of claim 45, wherein the moderately high positive voltage is between about + 10V and + 12V. 4 9. The method according to item 45 of the scope of patent application, wherein the medium positive voltage Page 58 200421601 VI. Patent Application Fan The voltage is approximately 6V ′ and therefore approximately 5V is applied to the drain region. 50. The method as described in item 45 of the scope of patent application, wherein the time for applying the moderately high positive voltage, the medium positive voltage, and the ground reference voltage is between about 1 to 100 microseconds (#S). . 5 1. The method described in item 45 of the scope of patent application, further comprising erasing a selected non-volatile memory cell to remove charge from the floating gate, the steps are as follows: Apply a very high negative voltage to The word line connected to the control gate of the selected memory cell. 5 2 · The method as described in item 51 of the patent application range, wherein the very high negative voltage is between approximately ~ -22V. 53. The method according to item 51 of the scope of patent application, wherein erasing the selected non-volatile memory unit further includes the following steps: Separate the source line connected to the source area of the selected non-volatile memory unit And the bit line connected to the drain region of the selected non-volatile memory cell, so that the source region and the light region are netted. 54. The method according to item 51 of the scope of patent application, wherein the step of erasing the selected non-volatile memory cell further includes the following steps: applying a ground reference voltage to a source region connected to the selected non-volatile memory cell The source line and the bit line connected to the drain region of the selected non-volatile memory cell. 5 5 The method according to item 51 of the scope of patent application, wherein the time for erasing the memory unit is between about 1 millisecond (ms) and 1 second. 5 6 · The method described in item 45 of the scope of patent application, wherein 200421601 6. The scope of patent application The non-volatile memory cell further includes a gate transistor, which has a source region connected to the drain region, a drain region connected to the bit line, and a selective k number to Selectively applying a one-bit line voltage: a signal to the gate of the area; and the non-volatile memory array further includes a plurality of selection lines, each selection line being connected to each non-volatile memory cell The gate of the gate transistor of the volatile memory list 70; and lengthening the selected non-volatile memory unit further includes the following steps: Add a very high positive voltage to the idle connected to the selected non-volatile memory unit. This selection line of the gate of the transistor. 5 The method according to item 56 of the scope of patent application, wherein the very high positive voltage is between about + 15V to + 22V. 5 ^ · The method according to item 56 of the scope of the patent application, wherein the time for applying the very south voltage, the moderately high positive voltage, the medium positive voltage, and the ground reference voltage is approximately 1 to 100 microseconds S )between. 2. The method according to item 56 of the scope of patent application, wherein erasing the selected 1 volatile memory unit further includes the following steps: Applying a very high positive voltage to the control connected to the selected non-volatile memory unit Between the word line in between; and a center reference voltage to the selection line connected to the gate of the transistor of the selected non-volatile memory cell. _Declares the method described in item 59 of the patent scope, wherein erasing the memory is about 1 millisecond (ms) to 1 second. 61. A method for forming a non-volatile memory unit, including the following steps: 200421601 6. The scope of the patent application forms a source region and a region on a substrate surface, separated by a distance; a channel insulation layer is formed on the substrate surface of a channel region between the source region and the region; A floating gate is formed above the channel insulation layer of the memory unit; the floating gate is aligned with an edge of the source region and an edge of the region; and the width of the floating gate is set to the edge of the source region and the A width defined by the edge of the pumping area; and forming an insulating layer above the floating gate; and forming a control gate above the insulating layer above the floating gate. 6 2 · The method for forming a non-volatile memory unit as described in item 61 of the scope of patent application, further comprising the steps as follows: Define an area of the floating gate so that the non-volatile memory unit has a-relatively small layout A coupling coefficient formed by a control gate above the floating gate and the total capacitance of the floating gate and the control gate. Each 6 3 · The method for forming a non-volatile memory cell as described in item 62 of the scope of the patent application, wherein the coupling coefficient is less than 50%. Ji 64. The method for forming a non-volatile memory cell as described in item 6 of the patent application scope, further comprising the steps as follows: the control gate is connected to a word line; The blank area is connected to a bit line; and the source area is connected to a source line. / 、 65 · The method for forming a non-volatile memory cell as described in item 62 of the scope of patent application, wherein the programming of the non-volatile memory cell is to place a charge on the floating gate, and the steps are as follows: 200421601 6. Application scope: Apply a moderately high voltage to the control gate through the word line; apply a medium positive voltage to the area through the bit line; and apply a ground reference voltage to the source through the source line Area. 6 6 · The method for forming a non-volatile memory cell as described in item 65 of the scope of patent application, wherein the moderately high positive voltage is between + 10V and + 12V. 67. The method for forming a non-volatile memory cell as described in claim 65, wherein the medium positive voltage is approximately 6V 'and therefore approximately 5V is applied to the green region. 6 8 · The method for forming a non-volatile memory cell as described in item 65 of the scope of patent application, wherein the time for applying the moderately high main voltage, the medium positive voltage, and the ground reference voltage is about 1 to 100 microseconds Seconds (#S). 6 9. The method for forming a non-volatile memory cell as described in item 64 of the scope of patent application, wherein the erasing of the memory cell is to remove the charge from the floating gate, and the steps are as follows: through the word line A very high negative voltage is applied to the control gate. 70. The method for forming a non-volatile memory cell as described in item 69 of the scope of patent application, wherein the very high negative voltage is between about -15V and -22V. 71. The method for forming a non-volatile memory cell as described in item 6 and 9 of the scope of patent application, wherein erasing the memory cell further includes the following steps: Separate the source line and the bit line so that the source area and the sink Area floating. 72. The method for forming a non-volatile memory cell as described in item 69 of the scope of the patent application] wherein erasing the memory cell further includes the following steps: a ground test voltage is applied to the source region through the source line and passes through the bit A line is applied to the drain region. Page 62 200421601 VI. Patent application scope 7 3 · The method for forming a non-volatile memory unit as described in item β 9 of the patent application scope, wherein the time for erasing the memory unit is about 1 millisecond (ms) to 1 second. between. 74. The method for forming a non-volatile memory cell as described in item 64 of the scope of patent application, further comprising the step of forming a gate transistor, the steps are as follows: forming a source region; connecting the source region to the drain region Forming a drain region; connecting the green region to the bit line; forming a gate; and connecting the gate to a selection line to selectively apply a bit line voltage signal to the drain region. 75. The method for forming a non-volatile memory cell as described in item 74 of the scope of patent application, wherein the programming of the non-volatile memory cell is to place a charge on the floating gate, and the steps are as follows: Through the character Apply a moderately high positive voltage to the control gate through the bit line; apply a medium positive voltage to the drain region through the gate transistor through the bit line; apply a very high positive voltage to the gate of the gate transistor through the gate line ; And applying a ground reference voltage to the source region through the source line. 76. The method for forming a non-volatile memory cell as described in item 75 of the scope of patent application, wherein the moderately high positive voltage is between about + 10V and + 12V. 77. The method for forming a non-volatile memory cell as described in item 75 of the scope of patent application, wherein the medium positive voltage is approximately 6V, and therefore approximately 5V is applied to the region. Page 63 200421601 VI. The scope of patent application = the formation of non-volatile memory cells described in item 75 of Fang Cheng 79 as claimed: special: the second very high positive electric mill is between + 15v ~ + m &lt; The formation of non-volatile = method described in Qianwei No. 75, in which the very high &gt; money, the moderate high // voltage ^ (the time between the two positive voltages and the ground reference voltage is about 1 ~ 10 ° micro Move Guang 80. The method of forming a non-volatile memory unit as described in item 74 of the scope of the patent application, wherein the erasing of the memory unit is to remove the load from the floating gate. The steps are as follows: μ Through the A very high negative voltage is applied to the control gate by the word line; and a ground reference voltage is applied to the selection gate through the selection line. 8 1 · The formation of a non-volatile memory cell as described in item 80 of the scope of patent application Method 'Where the erasing the memory unit further includes the steps as follows: Separate the source line and the bit line, so that the source area and the no-area area float. 8 2 · Form a non-line as described in item 80 of the scope of patent application Method for volatile memory unit, wherein erasing the memory unit is more inclusive The steps are as follows: ~ 70 A ground reference voltage is applied to the source region through the source line and is applied to the hidden region through the gate transistor through the bit line. A method for a volatile memory unit, wherein the time for erasing the memory unit is about 1 millisecond (ms) to 1 second. ^