TW200421061A - Electronic load apparatus - Google Patents

Electronic load apparatus Download PDF

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Publication number
TW200421061A
TW200421061A TW92126920A TW92126920A TW200421061A TW 200421061 A TW200421061 A TW 200421061A TW 92126920 A TW92126920 A TW 92126920A TW 92126920 A TW92126920 A TW 92126920A TW 200421061 A TW200421061 A TW 200421061A
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Prior art keywords
load
load current
current
voltage
circuit
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TW92126920A
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Chinese (zh)
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TWI237167B (en
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Kenji Nitadori
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Keisoku Giken Co Ltd
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  • Amplifiers (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)

Abstract

The present invention is provided to improve the frequency response characteristics of the load current for the tested power device of an electronic load apparatus. In the invention, impedance L1 is connected in series and attached to the source of transistor Q1 for load current control. In addition to improving the frequency response characteristic of the electronic load control loop and the electronic load transient response characteristics at the starting of the power supply to be tested, a better load current control characteristic is obtained in a wide load current range by providing a circuit device of a non-linear element between the input and output of an operational amplifier for the driving transistor of the controlling circuit.

Description

200421061 五、發明說明(1) 【發明所屬之技術領域 本發明係有關於一種作為直流電源 (放電後不能再使用)、二次電池(可☆帝、置或一久電池 % /1ίΗ可充電會;^ /由田、 電池等負載而使用的電子負載裝置,尤1 θ便用)、燃料 電流高速變化之被測試電源等特w二疋種测試負载 【先前技術】 特性之用的電子負載裝置。 第-圖為習知技術之電子負載裝置與被測試電源 路構成例及動作原理之說明。被測試電源2 ' 子f過連接電規3,與電子負載裝幻連接,藉由^出^ 丨» 定負載電流IL之電壓Ein設定為電流設定用㈣電厂所 以運算放大器A1比較該電流設定用控制電壓n的輸 載電流檢出用並聯電阻R1的電壓,藉由運算放大器Αι=二 出電壓驅動負載電晶體Q1之閘極,產生之負載電流I [如= 式1。 ’瓜 σ公 [數1 ] IL = Ein/Rl ............••公式1 進行被測試電源之動態負載動態測試時,電流設定用 控制電壓會得出不是直流電壓而是交互重複相當於1值負 載電壓值之控制電壓輸出之矩形波或電壓波狀的電壓,或 是任意波形相對於被測試電源的所要之負載電流波形。在 測試對於該負載電流高速變化之被測試電源的特性時,因 為電子負載裝置側要求高的直通率(through rate),所以 由運真放大器A1與負載電晶體Q1構成的負載電流控制迴路 之頻率特性,必須儘可能利用寬區域使控制響應特性達到200421061 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a rechargeable battery that can be used as a direct current power source (cannot be used again after discharging), a secondary battery (can be ☆ emperor, a battery, or a long-term battery; ^ / Electronic load devices used by loads such as fields and batteries (especially 1 θ), and two types of test loads such as power supplies under test where the fuel current changes at high speeds [prior art] Electronic load devices for characteristics. Fig.-Is a structural example of the electronic load device and the tested power circuit of the conventional technology and the description of the operation principle. The tested power source 2 'f is connected to the electrical gauge 3, and is connected to the electronic load. The voltage Ein of the fixed load current IL is set to the current setting. The power amplifier is used, so the operational amplifier A1 compares the current setting. The voltage of the parallel resistor R1 is detected by the load current of the control voltage n, and the gate of the load transistor Q1 is driven by the operational amplifier Aι = two output voltages, and the load current I [eg, Formula 1 is generated. 'Melon σ common [Number 1] IL = Ein / Rl ............ •• Equation 1 When the dynamic load dynamic test of the power supply under test is performed, the control voltage for current setting will not be DC The voltage is a rectangular wave or a voltage wave-like voltage that alternately repeats a control voltage output corresponding to a load voltage value, or an arbitrary waveform with respect to the desired load current waveform of the power supply under test. When testing the characteristics of the power supply under test for the high-speed change of the load current, because the electronic load device requires a high through rate, the frequency of the load current control loop composed of the real amplifier A1 and the load transistor Q1 Characteristics, it is necessary to use a wide area as much as possible to achieve control response characteristics

第5頁 200421061Page 5 200421061

南速0 要達到高速的負載電流流動,連接被測試電源2與電 子負載裝置1的連接電欖3之阻抗(i mpedance)必須要足夠 的低。雖然若該連接電纜3使用符合負載電流較粗之電纜 時,可以忽視該影響,但因電纜長度比例所產生的電纜阻 抗成分之增加,會對控制響應特性之高速化產生各種不良 的影響。 第二圖中,為了進行動態負載動態測試,負載電流控 制用電壓V3,可以產生一定時間間隔的矩形波電壓,利^ 負載電流檢出用並聯電阻R 1所檢出之符合負載電流的電壓 輸出,及利用運算放大器A1,將與前述負載電流控制用電 壓V3之電壓差輸出到增幅的負載電晶體Q1之閘極,並透過 連接電缆3,進行被測試電源2之動態負載動態測試。被測 試電源2是由電壓V2及内部電阻R2所構成。將連接電纜3的 單側線之等效阻抗當作L31及L32,將該一對電纜作成平行 線或絞線,使其磁束相互交叉,將該相互阻抗當作m時, 存在於被測試電源2與電子負載裝置1之間的連接電纜所產 生之阻抗成分,可以視為相當於公式2之[之等效阻抗。 [數2] L = L31 4* L32 - 2M............公式2 該連接電規3之等效阻抗L ,在動態負載電流增加時, 會呈如A式3所7F之直通率之$ ’與藉由連接電窺3之電壓 降6如公式4所f之關係式,該電Μ降e在接近被測試電源 之直机輸出電壓時’負載電晶體Q】之汲極、源極間的電壓South speed 0 In order to achieve high-speed load current flow, the impedance (i mpedance) between the power source 2 under test and the electronic load device 1 and the electrical impedance 3 must be sufficiently low. Although this effect can be ignored if the connection cable 3 uses a cable with a relatively large load current, the increase in the cable impedance component due to the cable length ratio can have various adverse effects on the speeding up of control response characteristics. In the second figure, in order to perform a dynamic load dynamic test, the load current control voltage V3 can generate a rectangular wave voltage at a certain interval, which facilitates the detection of load current and the voltage output that matches the load current detected by the parallel resistor R 1 And using the operational amplifier A1, output the voltage difference from the aforementioned load current control voltage V3 to the gate of the amplified load transistor Q1, and perform a dynamic load dynamic test of the power source 2 to be tested through the connection cable 3. The test power source 2 is composed of a voltage V2 and an internal resistance R2. The equivalent impedance of the single-sided wire of the connection cable 3 is taken as L31 and L32, and the pair of cables is made into parallel or twisted wires so that the magnetic beams cross each other. When the mutual impedance is taken as m, it exists in the power supply 2 under test. The impedance component generated by the connection cable to the electronic load device 1 can be regarded as the equivalent impedance of [in Equation 2]. [Equation 2] L = L31 4 * L32-2M ............ Equation 2 The equivalent impedance L of the connection electric gauge 3, when the dynamic load current increases, it will appear as A formula 3 The relationship between the direct current rate of 7F $ 'and the voltage drop 6 connected to the telescope 3 is as shown in f in Equation 4. When the electric drop e is close to the output voltage of the direct power of the tested power source,' load transistor Q] Voltage between drain and source

200421061 五、發明說明(3) 會達到飽合,從公式5所示之關係式,呈幾乎是公式6之直 通率。 [數3] S = di /dt…公式3 [數4] e = LxS = Lxdi/dt …公式4 [數5] L X di/dt = E …公式5 [數6 ] S = di/dt = E/L …公式6 在此,將被測試電源之輸出電壓當作E、負載電晶體 Q1之汲極、源極間電壓的飽合時間當作T,如公式7所示, 在該電壓飽合時間中,負載電流會產生不是原本的電流值 或非原來的電流波形之情形,而為了防止這樣的影響,習 知之簡便的方法是縮短連接電纜,減少連接電纜的等效阻 抗L ’使得到目的直通率之高負載電流波形。 [數7] T = L x E/Ι…公式7 、、吏觀點來看,在不論是被測試電源之靜態負載須 、過渡之電流波形之用途中,來試看看連接 ^ =生負急速增加時,前述的ΐ; Τ短時間發生,之後會穩定落在一定的設定電 題。作1,及時有電壓飽合時間,多半也不會有任何Ρ’: ^ 但疋,習知技術之電子f 1 7200421061 V. Description of the invention (3) It will reach saturation. From the relational formula shown in formula 5, it shows almost the through rate of formula 6. [Equation 3] S = di /dt...Equation 3 [Equation 4] e = LxS = Lxdi / dt… Equation 4 [Equation 5] LX di / dt = E… Equation 5 [Equation 6] S = di / dt = E / L… Equation 6 Here, let the output voltage of the power supply under test be E, the saturation time of the drain and source voltages of load transistor Q1 be T, as shown in Equation 7, where the voltage is saturated During the time, the load current will produce a situation other than the original current value or the original current waveform. In order to prevent such effects, a convenient and convenient method is to shorten the connection cable and reduce the equivalent impedance L 'of the connection cable to achieve the purpose. High load current waveform of shoot-through rate. [Equation 7] T = L x E / I ... Equation 7. From the point of view, in the application of the static load of the power supply to be tested and the current waveform of the transition, let's try to see the connection ^ = rapid increase in negative load At this time, the aforementioned ΐ; T occurs for a short time, and then it will steadily fall to a certain set problem. Operation 1, there will be voltage saturation time in time, most of the time there will not be any P ’: ^ But, the electron of the conventional technology f 1 7

200421061200421061

:難要:止超過設定電流值之過流(。ver切)問 須採取使電壓飽合現象不會發生的範圍之和緩 的直通率負載設定等權宜的裝置。 % # 2 Ϊ的問題之一是’連接電纜的等效阻抗L會對電子 2控制迴路特性產生很大的影響。若追求高速響應而使 工迴路的頻率區域放寬時,隨著連接電纜的阻抗L增 大,會使迴路特性的振幅餘裕及相位餘裕減少,產生過流 特性(over shunt),而引起電子負載連續振盪的問題。習 头技術為了讓連接電缓的阻抗即使增大到某一程度,也 不會發生振盪,會利用第二圖之運算放大器^藉由電容 C10、電阻R10之頻率過濾裝置,降低頻率區域,而大幅犧 牲應答速度。因此,對高速響應之電子負載是很大的障 礙0 以下就電子負載所要求的另一個特性作敘述。考慮到 被測试電源之電源啟動測試時,對於電子負載,多半是在 被測試電源的電源關閉時,預先設定啟動後的負載電流值 或負載阻抗值。此時,電子負載即使在未施加被測試電源 之輸出電壓的狀態下,仍可設定負載電流,所以,負載電 晶體Q1會呈最大驅動應該流動負載電流之閘極電壓。在此 狀態下,在被測試電源的電源打開時,有時會發生大幅超 過過渡性設定負載電流之短路電流流動的情形。這會因電 子負載之負載設定控制迴路之應答速度及被測試電源的輸 出電壓啟動時間而有所差異,但是,習知技術之電子負載 及一般的被測試電源中,會是很大的問題,即檢出電子負: Difficult: Stop over-current (. Ver cut) that exceeds the set current value. It is necessary to adopt an appropriate device such as a straight-through load setting that moderates the range where the voltage saturation phenomenon does not occur. One of the problems with% # 2 是 is that the equivalent impedance L of the connection cable has a great influence on the characteristics of the electronic 2 control loop. If the frequency range of the industrial circuit is widened in pursuit of high-speed response, as the impedance L of the connecting cable increases, the amplitude margin and phase margin of the circuit characteristics will decrease, resulting in over-current characteristics (over shunt), causing the electronic load to continue. The problem of oscillation. In order to make the impedance of the electrical connection to a certain extent increase, the head technology does not oscillate, it will use the operational amplifier of the second figure ^ through the frequency filter device of capacitor C10 and resistor R10 to reduce the frequency region, and Significantly sacrifice response speed. Therefore, the electronic load with high-speed response is a great obstacle. The following describes another characteristic required by the electronic load. Considering that during the power-on test of the power supply under test, for electronic loads, most of the time when the power of the power supply under test is turned off, the load current value or load impedance value after startup is preset. At this time, the electronic load can set the load current even when the output voltage of the power supply under test is not applied. Therefore, the load transistor Q1 will be at the maximum gate voltage that should flow the load current. In this state, when the power of the power supply under test is turned on, a short-circuit current that greatly exceeds the transient load current may occur. This will vary depending on the response speed of the load setting control loop of the electronic load and the start-up time of the output voltage of the tested power supply. However, the conventional electronic load and the tested power supply in conventional technology will be a big problem, that is, Detected negative

第8頁 200421061Page 8 200421061

載^端子電壓,在該檢出值於一定的臨界值(thresh〇u) 電壓以下時,將在被測試電源的電源關閉時所看不見的負 載電晶體之閘極驅動遮斷或降低,而在超過臨界值電壓時 使負載電流控制迴路動作等之裝置。附加該電路,會使被 測試電源的動作開始時間延遲,以及在臨界值電壓以下 經常會遮斷負載電流等的障礙產生。參照專利文獻丨及 利文獻2等: 【專利文獻1】 特開平06 - 1 1 3450號公報(第4-9項、第一圖) 【專利文獻2】 特開2 0 0 1 - 1 3 4 3 2 6號公報(第11 一 1 4項、第二圖) 【發明内容】 本發明所欲解決之技術問題 本發明在於提供一種具有急峻負載電流變動及廣範圍 頻率響應特性之電子負載裝置之電路方式及裝置,其可以 解決如上所述習知之電子負載裝置之課題,減輕在急峻的 負載電流變動時之電子負載裝置控制迴路特性的響應特 性、電子負載裝置與被測試電源連接電纜之阻抗&響,解When the load terminal voltage is below a certain threshold value, the gate drive of the load transistor, which is invisible when the power of the test power supply is turned off, is blocked or reduced, and A device that activates a load current control circuit when the threshold voltage is exceeded. Adding this circuit will cause delays in the start time of the power supply under test, and obstacles such as load current that are often interrupted below the threshold voltage. Refer to Patent Documents 丨 and Patent Documents 2, etc .: [Patent Document 1] JP 06- 1 1 3450 (items 4-9, first drawing) [Patent Document 2] JP 2 0 0 1-1 3 4 3 2 6 (items 11 to 14, item 2) [Summary] Technical problem to be solved by the present invention The present invention is to provide an electronic load device with sharp load current fluctuation and wide-range frequency response characteristics. The circuit method and device can solve the problems of the conventional electronic load device as described above, reduce the response characteristics of the control circuit characteristics of the electronic load device when the load current fluctuates sharply, and the impedance & Ring

決從電壓飽合狀態的恢復時間延遲之過流(over shunt)課 題。 本發明解決問題之技術手段 本發明係一種包含作為被測試電源2之負載而動作之Solve the over-shunt problem that delays the recovery time from the voltage saturation state. Technical means for solving the problems of the present invention The present invention relates to a method for operating as a load of the power source 2 to be tested.

200421061 五、發明說明(6) 電晶體Q1,盘批生丨 制電路的電g =并,心電流設定值之電流流入電晶體之控 源極而構成n裝f,將阻抗U串聯插人負載電晶體之 成該控制ΐ路;;2;:月將二極體之非直線元件插入構 J电路的運异放大器之回授電路而構成。 本發明對照先前技術之功效 如上述之說明,本發 電 術之電子負载裝置,且 相载裝置,比起習知技 應特性,且不異/ 7 K a 項率區域的負載電流響 的影響,戶斤測試電源的連接電欖之寄生阻抗 時之特性4二ίί電源之急峻負載動態測試及啟動 的測試,本發明之電子負電子負載裝置很難進行 響應特性測試。、、°以進行這樣的高速負載 【實施方式】 以下就參照圖表來說明本發明之實 為了避免本申請案件之實施例的說明=雜 個負載電晶體的情況加以說明,”缺二::僅就1 i苷帝、去” a 1一田然可以因應所必要夕 iimL載電力的大小,將包含負載電流控制迴路之 ^電路與複數個區塊(blQek)並聯,相所f要的電子路負之 電子範圍第1項所記載之一實施例,習知技術之 制用電壓V3之電壓差輸出’會透過電阻R1〇與從偏控 200421061 五、發明說明(7) " —--- (Of f set»)調整用電壓V4,透過電阻R4輸出的電壓合成,連 接於,=放大器A1之單側輸入,負載電流檢出用分流電阻 1之符合負載電流的電壓輸出,會透過電阻R3在平衡電阻 Ri 1與電容cio分流後,連接於運算放大器A1之單側輸入, 形成負回授控制迴路,藉由該運算放大器A1之電壓輸出, 驅動電晶體Q1,進行以連接電纜3所連接的被測試電源2 電子負載測試。 ^ 如第三圖所示之習知技術的電子負載裝置之電路,進 行其特性的模擬。一般是將cl〇插入運算放大器八丨之回授 電路,進行頻率特性之評價,因為很難達到原來的高速X響 應,所以運算放大器不使用這麼廣區域的情形很多,為^ 作特性的比較,在此以本發明相同的廣區域運算放大器進 行模擬。 ° 本發明專利申請範圍第1項所記載之一實施例如第四 圖所示,但將阻抗L1串聯插入場效電晶體Q1之源極。為了 發揮本發明之特徵,使用比場效電晶體Q1之順向導納 (admittance)之頻率特性更充分廣區域且輸出電壓的直通 率更高的運算放大器,連接電纜和被測試電源之輸出電壓 或負載電流設定等也以相同條件,進行模擬比較。 第三圖的電路圖之習知技術的各部頻率特性與回授迴 路特型如第五圖所示。設定條件為將被測試電源之輸出電 壓V2設定為5 [V]、負載電流設定為約5 [A]之條件,連接電 纜3的單側線之阻抗L31、L32設定為U/zIU'lOEvH]、 100[ //Η]、耦合係數Κ3 = 0· 9 時。200421061 V. Description of the invention (6) Transistor Q1, the electric circuit of the circuit produced by the plate g = and the current of the set value of the cardiac current flows into the control source of the transistor to form n and f, and the impedance U is inserted into the load in series. The control circuit is formed by the transistor; 2 ;: The non-linear element of the diode is inserted into the feedback circuit of the operation amplifier of the J circuit. The effect of the present invention is as described above in comparison with the effect of the prior art. The electronic load device and the phase load device of the power generation technology have the same effect as the conventional technical characteristics, and the load current response in the 7 K a rate area is the same. The characteristics of the household catapult test power supply when connected to the parasitic impedance of the power supply 42. The power load's severe load dynamic test and startup test, the electronic negative electronic load device of the present invention is difficult to perform response characteristic tests. To implement such a high-speed load [Embodiment] The following is a description of the embodiment of the present invention with reference to the chart to avoid the description of the embodiment of the present application = the case of a heterogeneous load transistor, "Missing 2 :: Only With regard to 1 glycoside, go to "a 1". Yita Ran can connect the circuit containing the load current control loop in parallel with a plurality of blocks (blQek) in accordance with the magnitude of the required iimL load power. One embodiment of the negative electron range described in the first item, the voltage difference output of the voltage V3 of the conventional technology is transmitted through the resistor R10 and the bias control 200421061 V. Description of the invention (7) " ----- (Of f set ») The adjustment voltage V4 is combined with the voltage output through the resistor R4 and connected to = one-sided input of the amplifier A1. The load current-matching voltage output of the shunt resistor 1 for load current detection will pass through the resistor R3 After the balancing resistor Ri 1 and the capacitor cio are shunted, they are connected to the single-sided input of the operational amplifier A1 to form a negative feedback control loop. The voltage output of the operational amplifier A1 drives the transistor Q1 to connect the cable 3 2 is connected to an electronic test power load test. ^ The circuit of a conventional electronic load device as shown in the third figure is used to simulate its characteristics. Generally, cl0 is inserted into the feedback circuit of the operational amplifier to evaluate the frequency characteristics. Because it is difficult to achieve the original high-speed X response, there are many cases where the operational amplifier does not use such a wide area. For comparison of characteristics, Here, simulation is performed with the same wide-area operational amplifier of the present invention. ° One of the embodiments described in item 1 of the patent application scope of the present invention is shown in the fourth figure, but the impedance L1 is connected in series to the source of the field effect transistor Q1. In order to take advantage of the characteristics of the present invention, an operational amplifier with a wider frequency range and a higher pass-through rate of output voltage than the field effect transistor Q1's admittance is used to connect the cable to the output voltage of the power supply under test or The load current setting and the like are also simulated and compared under the same conditions. The frequency characteristics and feedback loop characteristics of each part of the conventional technique of the circuit diagram in the third diagram are shown in the fifth diagram. The setting conditions are that the output voltage V2 of the power supply under test is set to 5 [V], the load current is set to about 5 [A], and the impedances of the single-sided wires of the connection cable 3 are set to U / zIU'lOEvH], 100 [// Η], when the coupling coefficient K3 = 0 · 9.

200421061 五、發明說明(8) 第五D圖及第五E圖表示負回 ^ 第五D圖為振幅特性、第五特性,其中 3的阻抗U卜L32,減少振幅 位。秸由連接電纜 路頻率特性下,預想有很高峰的頻率特1生餘。裕,在閉鎖迴 各部分的頻率特性而言,輸入場效 壓的汲極電壓之頻率特性,如第 Ba體…之閘極電 鏡3的阻抗L31、L32,頻率會上第/B,不,藉由連接電 ^只午I上升,同時呈比例捭 ,抗與場效電晶體Q1之没極、源極間電容日ζ 率具有高♦。在該電壓增幅度變高的頻率下,回:迴= 盈也會如第五D圖一般受到很大的影曰200421061 V. Description of the invention (8) The fifth D diagram and the fifth E diagram show the negative return ^ The fifth D diagram is the amplitude characteristic and the fifth characteristic, of which the impedance U3 is L32 and the amplitude is reduced. Under the frequency characteristics of the connecting cable, it is expected that there will be a very high frequency. Yu, in terms of the frequency characteristics of each part of the latch-back, the frequency characteristics of the drain voltage of the input field effect voltage, such as the impedance L31, L32 of the gate mirror 3 of the body Ba, the frequency will be on the / B, no, By connecting the electric voltage ^ I only rises at the same time, and at the same time proportionally 捭, the impedance and field-effect transistor Q1 have a high ζ rate between the source and the capacitor. At the frequency where the voltage increase becomes high, Hui: Hui = profit will also be greatly affected as in the fifth D diagram.

連續振盈。為了避免此-現象,在比連接電鏡3;;=起 L31、L32之共振頻率低之頻率下,為了使迴路增益在〇dB 以I,會加大回授電gC10,在輸入分流電阻们之電壓的 運算放大器A1之輸出電壓以下的頻率特性,如第五a圖所 示,其落在頻率區域内。 此外’第三圖及第四圖之電容⑵^及電阻R3〇,為了使 連接電纜的阻抗與場效電晶體…之汲極、源極間寄生容量 之共振現象損失’增加回授迴路的安定性,會採取不影響 負載電流波形範圍的阻抗。 將如第四圖所示的專利申請範圍第1項之一實施例的 f 電路,同樣亦進行模擬,結果如第六圖所示。各部分的電 壓增幅度之頻率特性,作為輸入分流電阻(R 1及R 2 )兩端之 電壓,運算放大器A1輸出以下之電壓增幅度的頻率特性, 如第六A圖所示,相對於運算放大器A1幾乎無回授的增幅Continuous vibration. In order to avoid this phenomenon, at a frequency lower than the resonance frequency of L31 and L32 connected to; in order to make the loop gain at 0dB to I, the feedback power gC10 will be increased. The frequency characteristics below the output voltage of the operational amplifier A1 of the voltage, as shown in the fifth a diagram, fall within the frequency region. In addition, the capacitors ⑵ ^ and R3 of the third and fourth diagrams increase the stability of the feedback circuit in order to reduce the impedance of the connection cable and the resonance phenomenon of the parasitic capacity between the drain and source of the field effect transistor ... The impedance will not affect the range of the load current waveform. The f circuit of one embodiment of the first item of the patent application scope shown in the fourth figure is also simulated, and the result is shown in the sixth figure. The frequency characteristics of the voltage increase amplitude of each part, as the voltage across the input shunt resistors (R 1 and R 2), the operational amplifier A1 outputs the frequency characteristics of the voltage increase amplitude below, as shown in Figure 6A, relative to the operation Amplifier A1 has almost no feedback increase

第12頁 200421061 五、發明說明(9) 度,其呈廣區域 極電壓的及極以 阻抗而定,但因 以該阻抗之電流 域不會有急峻的 徵。雖然因插入 增幅度和頻率特 流控制迴路全體 特性,都有充分 的值來達到廣區 此時,對於 特性’為了有效 該阻抗L 2有時只 外加。 且很高的增幅度。輸入場效電晶體Q1之閘 下之電壓增幅度,會視連接電纜3的等效 為將阻抗L1插入場效電晶體Q1之源極,所 回授會如第六B圖所示,在中間的頻率區 高峰,而是呈幾乎平坦的頻率特性為其特 場效電晶體Q1源極之阻抗L1的值不同,該 性會有變化,但如第六D圖所示,負載電 的迴路增益及如第六E圖所示的迴路相位 的增益餘裕及相位餘裕,且可選擇最適當 域。 田 負載電流之分流電阻R 1的輪出電壓之頻率 補償一巡迴路特性之頻率,插入阻抗L2。 要分流電阻固有的阻抗即已足夠,不需要 1時 分流電阻m及阻抗L2的頻率特性,將時間常數當作τ [數8] r 1 = L2/R1…公式8Page 12 200421061 V. Description of the invention (9) Degree, which is in a wide area. The pole voltage and pole are determined by impedance, but there will be no acute sign in the current domain with this impedance. Although the overall characteristics of the gain and frequency current control loop are inserted, they have sufficient values to achieve a wide area. At this time, for the characteristic ', the impedance L 2 may be applied only in some cases. And a very high increase. The increase in voltage under the gate of the input field effect transistor Q1 will be regarded as the equivalent of connecting cable 3 to insert the impedance L1 into the source of the field effect transistor Q1. The feedback will be as shown in Figure 6B, in the middle The peak in the frequency region of the frequency band has an almost flat frequency characteristic. The value of the impedance L1 of the source of the special field effect transistor Q1 is different. This characteristic will vary, but as shown in the sixth D diagram, the loop gain of the load current And the gain margin and phase margin of the loop phase as shown in the sixth E diagram, and the most appropriate range can be selected. Tian The frequency of the wheel-out voltage of the shunt resistor R 1 of the load current compensates the frequency of the circuit characteristic of a tour circuit and inserts the impedance L2. The inherent impedance of the shunt resistor is sufficient. The frequency characteristics of the shunt resistor m and the impedance L2 are not needed at 1 hour. Let the time constant be τ [Equation 8] r 1 = L2 / R1 ... Equation 8

為公式8,將工作頻率當作“ [數9] X R1) ····公式9 以高域頻率+6dB/oct之 位,對一巡迴路特性之 二 1 /(2 7Γ X rl) =L2 / (2 冗 為么式9,呈將頻率“當作邊界, 振幅特性,相位最大90〇之進行相 安定度的頻率補償具有效果。For Equation 8, consider the operating frequency as "[Equation 9] X R1) ···································································································· 2 L2 / (2 Redundant Equation 9 shows that frequency is used as a boundary, amplitude characteristics, and phase compensation with phase stability of up to 90 ° is effective for frequency compensation.

200421061 五、發明說明(ίο) 、此時’當然’除了以分流電阻R1及阻抗L2檢出的負載 ^流的頻率^性有微分要素之外,也會產生與負載電流不 同的波形之弊害。亦即,電流控制回授迴路的回授電路之 =率特性變的不平坦。為了防止此一現象的方法,是在回 授電路另一方的元件輪入電阻R1,並聯插入與前述時間常 ,Γ 1相同的電容C11 0,可以將從負載電流設定用輸入訊 说到負載電流為止的頻率特性保持平坦,達到與負載電流 σ又定用電壓V3之電流輸出波形同等之負載電流波形。 、二第四圖中,將電阻!^11〇並聯插入電容cn〇,為了改善 以。亥時間#數τ i決定的頻率更充分高的頻率之頻率特 性,會選擇比電阻1^1 0充分小的電阻R11 0之定數值。此 外為了使作為差動輸入訊號動作,會以與電阻β 1 〇盘電 容C110同等的常數,插入電阻R11與電容C111 、此外,以下就有助於一回授迴路特性的安定度之效果 力0 =明。㈣於作為負載冑晶體之場效電晶體的閉極輸 入電壓之汲極電流的頻率特性,順向導納yfs之特性,一 力率M0SFET電晶體時,會以卜叫妬]左右為邊界逐 ΐ I慮寄生於場效電晶體内部的靜電容量之源極電 二了日流動以順向導納yfs之特性決定的沒極電流之 外,閑極源極間容量之閘極電流,也會與源極重疊。200421061 V. Description of the Invention (ίο) At this time, 'Of course', in addition to the frequency of the load detected by the shunt resistor R1 and the impedance L2, there are differentiating elements, and it will also produce the disadvantage of a waveform different from the load current. That is, the rate characteristic of the feedback circuit of the current control feedback loop becomes uneven. The method to prevent this phenomenon is to insert a resistor R1 in the other element of the feedback circuit in parallel, and insert a capacitor C11 0 which is the same as the previous time and Γ 1 in parallel, and can input the load current from the load current setting input to the load current. The frequency characteristics so far remain flat and reach a load current waveform equivalent to the current output waveform of the load current σ and the fixed voltage V3. In the second and fourth figures, the resistor! ^ 11 is inserted in parallel with the capacitor cn〇 in order to improve it. The frequency characteristic of the frequency higher than the frequency determined by the Hai time #number τ i is sufficiently high, and a predetermined value of the resistance R11 0 which is sufficiently smaller than the resistance 1 ^ 1 0 is selected. In addition, in order to operate as a differential input signal, the resistor R11 and the capacitor C111 are inserted with constants equivalent to the resistance β 1 0 of the disk capacitor C110. In addition, the following will contribute to the effectiveness of the feedback circuit's stability. 0 = Ming. The frequency characteristics of the drain current of the closed-pole input voltage of the field effect transistor as a load crystal, the characteristics of the admittance yfs, and the power factor of the M0SFET transistor will be jealous.) Considering the source capacitance of the electrostatic capacitance parasitic inside the field effect transistor, in addition to the non-polar current determined by the characteristics of the admittance yfs, the gate current of the capacity between the free source and the source is also related to the source. Extremely overlapping.

=了忠實檢出除了閘極電流以外之負載電流 第八圖之方法。分流電阻雖然會正磁 曰H 載電流,但是,順向導納會隨著頻率=:間極電流的負 銥很大的相位延遲,使迴路特性產 午= The method of faithfully detecting the load current other than the gate current is shown in the eighth figure. Although the shunt resistor will be positively magnetized, that is, the H load current, the forward admittance will follow the frequency =: the negative pole current.

第14頁 200421061 五、發明說明(I” ------η 另方面,藉由如第七圖之本發明的電路,因為並非 只檢出負載電流,也可以檢出包含閑極電流的負=非 所以,在高頻率下的相位延遲可以被抑制在最小,對迴路 特性的安定度有报好的效果。此時’有不能檢出實際的負 載電流之缺點’但因為是比負載電流所必須的頻率區域十 分高的頻率,而且比起負載電流,其閘極電流值十分低, 所以該影響極低,但對高頻振盪等之安定度具有十分的效 果。 以上之頻率區域的習知技術與本發明之特性已比較說 · 明如上,以迴路增益是丨時的頻率來看,本發明幾乎可以 | 達到1 0 0倍之廣區域化,對於連接電纜的阻抗之變化,振 幅餘裕與相位餘裕都更勝一籌。 其次,就時間領域的特性,以模擬來比較習知技術與 本發明。 ^ 關於負載電流之響應特性,習知技術之電路圖如第三 圖所示、本發明之電路圖如第四圖所示,設定條件為將被 測試電源之輸出電壓V2設定為5[V]、負載電流設定訊號V3 之波形啟動時間為1 [ //S]、負載電流設定為〇〜5[Α]、連接 電纜3的單側線之阻抗L31、L32,設定單側線為1 [ //Η]、 1〇[ #Η]、100[ "Η]、耦合係數Κ3 = 0· 9,以模擬求出負載 - 電流波形。 第九圖為習知技術、第十圖為本發明之結果,第九A 圖、第十A圖為負載電流設定訊號V3之波形;第九B圖、第 十B圖為場效電晶體Q1之汲極源極間之電壓;第九C圖、第Page 14 200421061 V. Description of the invention (I ”------ η On the other hand, with the circuit of the present invention as shown in the seventh figure, because not only the load current can be detected, but also the one containing the idler current can be detected. Negative = No, so the phase delay at high frequencies can be suppressed to a minimum, which has a good effect on the stability of the loop characteristics. At this time, 'there is a disadvantage of not being able to detect the actual load current', but because it is lower than the load current The required frequency range is very high, and its gate current value is very low compared to the load current, so the effect is extremely low, but it has a very effective effect on the stability of high-frequency oscillations. The characteristics of the known technology and the present invention have been described in comparison. As explained above, in view of the frequency at which the loop gain is 丨, the present invention can almost achieve a wide area of 100 times. For the change in impedance of the connection cable, the amplitude is marginal. It is better than phase margin. Secondly, the conventional technology and the present invention are compared with respect to the characteristics of the time domain by simulation. ^ For the response characteristic of the load current, the circuit diagram of the conventional technology is shown in Figure 3. As shown in the figure, the circuit diagram of the present invention is shown in the fourth figure. The setting conditions are to set the output voltage V2 of the power supply to be tested to 5 [V], and the waveform start time of the load current setting signal V3 to be 1 [// S], The load current is set to 0 ~ 5 [Α], the impedance of the single-sided line of connection cable 3 is L31, L32, and the single-sided line is set to 1 [// Η], 1〇 [# Η], 100 [" Η], coupling coefficient Κ3 = 0.9, the load-current waveform is obtained by simulation. The ninth figure is a conventional technique, the tenth figure is the result of the present invention, and the ninth A and tenth A are the waveforms of the load current setting signal V3; Figures 9B and 10B are the voltages between the drain and source of the field effect transistor Q1;

第15頁 200421061Page 15 200421061

五、發明說明(12) 十C圖為負載電流波形。 習知技術下,即使連接電纜3的阻抗小時,因為汲極 源極電壓不是飽合的狀態,控制系統之頻率區域不足,所 以啟動時間會變慢;而連接電纜3的阻抗變大時,從飽合 到回復過程,會產生設定電流大幅超過之過流狀況。 其次,關於被測試電源啟動測試時之響應特性,習知 技術之電路圖以第十一圖、本發明之電路圖以第十二圖說 明。兩者均將負載電流設定電壓v 1預先設為負載電流β 5 [ A],模擬被測試電源啟動,從無輸出電壓到定格輸出電 壓啟動之輸出電壓波形,置換到台形波產生器,設定啟 動時間為1[//S]時,輸出電壓為5[V]之條件,連接電、纜3 的單側線之阻抗L31、L32,設定單側線為U “Η]、1〇[’ v Η]、100[ //H]、麵合係數Κ3 = 0· 9,以模擬求出負載電流波 第十三圖為習知技術、第十四圖為本發明之結果 弟 .Α圖、第十四Α圖為相當於被測試電源2之輸出電壓波 形;第十三B ®、第十四B圖為負載電流。在習知技術中, 因為被測試電源啟動以前所設定的負載電流應流動的場效 ,晶體以閘極電壓會呈最大限度的驅動,使被測試電源 啟動,所以,一旦極大負載電流流動之結果,即使是電流 ,制迴路的料,因為作為控制系統之頻率 舁放大器之回授電路之電容cl〇,結果會使運 :電壓之直通率會變得極慢,回到設定電流值的時間:會 持縯很長。因為运會依存頻率補償電路的方式,所以將運V. Description of the invention (12) Figure 10C is the load current waveform. Under the conventional technology, even if the impedance of the connection cable 3 is small, since the drain-source voltage is not saturated, the frequency range of the control system is insufficient, so the startup time will be slowed down; and when the impedance of the connection cable 3 becomes large, the Saturation to recovery process will produce an overcurrent condition where the set current greatly exceeds. Secondly, regarding the response characteristics of the tested power supply during the start-up test, the circuit diagram of the conventional technology is illustrated in Fig. 11 and the circuit diagram of the present invention is illustrated in Fig. 12. Both set the load current set voltage v 1 to the load current β 5 [A] in advance, simulating the output voltage waveform from the start of the tested power supply to the fixed output voltage startup, and replacing it with a table wave generator to set the startup. When the time is 1 [// S], the output voltage is 5 [V]. The impedance of the single-sided line connected to the power and cable 3 is L31 and L32. Set the single-sided line to U "Η", 1〇 ['v Η] , 100 [// H], surface area coefficient κ3 = 0 · 9, the load current wave is calculated by simulation. The thirteenth graph is a conventional technique, and the fourteenth graph is the result of the present invention. Α graph, fourteenth Figure A is the output voltage waveform corresponding to the power supply 2 under test; Figures 13B ® and 14B are the load currents. In the conventional technology, because the load current that is set before the power supply under test starts to flow, Effect, the crystal will be driven to the maximum with the gate voltage, so that the power supply under test will start, so once the load current flows, even the current, the material of the control circuit is used as the feedback of the frequency of the control system and the amplifier The capacitance of the circuit cl0, the result will be: Through rate becomes extremely slow, back to the time set current value: a long play will be held because the frequency compensation circuit operation will be dependent manner, so that the transport

第16頁 200421061Page 16 200421061

:動區域化是無法解決的。這對進行被測試電源 二!二:”子負載是很致命的,而權宜的對策,就是必 之負載電流遮斷電路,為其缺點所在。 以達月如第十四β圖所示之負載電流波形圖,可 二=接電镜3的阻抗之大小,都極少會發生負載 電/氣過流的情形。: Dynamic regionalization cannot be resolved. This is the second power source to be tested! Second: "The sub load is very fatal, and the expedient countermeasure is that the load current must block the circuit as its shortcoming. Load current waveform diagram, can be two = the size of the impedance of the power mirror 3, the load electricity / gas overcurrent will rarely occur.

、㈣、ϊϋ圖為將阻抗U連接於負載電晶體Q1之源極,11 =ϋ 、連接負載電流檢出用分流電阻κι,第十六圖肩 代、電流檢出用分流電阻R1連接於負載電晶體Qi之源 =,,過該負載電流檢出用分流電阻以連接於阻抗L1,才 毛=疋在分流電阻R丨的兩端,差動檢出負載電流進行回拍 f 1 ’所以’以阻抗L1及分流電阻r 1之順序連接於負載電 晶體Q1之源極,並不損本發明之效果。 其次’專利申請範圍第2項所記載之本發明一實施 例其原理以第十七圖及第十八圖表示。從運算放大器的 輸出到輸入端子,藉由插入二極體等非直線元件,電子負 載裝置的負載電流可以從極小到很大的電流,在廣範圍下 均了呈鬲速響應及安定的動作。以下就圖面及模擬結果作 更詳細的說明。在第十七圖及第十八圖中,是以1個運算, ㈣, ϊϋ are the impedance U connected to the source of the load transistor Q1, 11 = 连接, connected to the load current detection shunt resistor κι, Figure 16 shoulder generation, current detection shunt resistor R1 is connected to the load The source of the transistor Qi =, the shunt resistor for detecting the load current is connected to the impedance L1, and the hair = 疋 is at the two ends of the shunt resistor R 丨, and the load current is differentially detected to perform the f1 'so' Connecting the source of the load transistor Q1 in the order of the impedance L1 and the shunt resistor r 1 does not impair the effect of the present invention. Next, the principle of an embodiment of the present invention described in item 2 of the scope of the patent application is shown in Figs. 17 and 18. By inserting non-linear components such as diodes from the output of the operational amplifier to the input terminal, the load current of the electronic load device can be from very small to very large current, and it has a fast response and stable operation over a wide range. The drawings and simulation results are described in more detail below. In the seventeenth and eighteenth figures, one operation is performed.

放大器代表負載電流控制電路之增幅部,但亦可使用負數 個適當的運算放大器,在驅動負載控制用電晶體之場效電 晶體之最終段的運算放大器中,藉由將二極體等非直線元 件插入負回授電路,增幅度可以對應場效電晶體的閘極 壓而變化。The amplifier represents the increase part of the load current control circuit, but a negative number of appropriate operational amplifiers can also be used. In the operational amplifier that drives the final stage of the field effect transistor of the load control transistor, a non-linear The component is inserted into the negative feedback circuit, and the increase can be changed corresponding to the gate voltage of the field effect transistor.

第17頁Page 17

200421061200421061

非直線元件的具體例如第十九圖及第二十圖所示。 十九圖為實裝2端子之非直線元件的情形,其由1個乃至n 個二極體D(l)〜D(n) ’或電阻RD1及1個乃至η個二極 〜DU)構成’如第十九C圖、第十九D圖所示,亦可 納二極體(Zener diode)ZD(l)之構成。第二十圖為實麥3 端子之非直線元件的情形’第二十A圖為二極體 納二極體ZD(1)及電阻RD13之構成例;第二十b圖為附加電 阻RD11及電阻RD12之構成例;第二十C圖為連接點BJ1側之 一極體D J 1 —個乃至η個’連接點B J 2側之二極體j) j 2 一個乃 至m個之構成例;第二十D圖為前述第二十c圖構成例再附 加電阻RD11及電阻RD12之構成例,但效果都是相同的。除 二極體之外,亦可並用頻率補償用之電容,為了將非直線 特性最適化,亦可適當組合電阻及偏壓(bias)等使用。、 此外’本實施例是以N通道之電晶體來說明的,但使 用P通道之電晶體時,若變更第十九圖及第二十圖所示之 非直線性元件之連接極性,當然也可得到同樣之效果。 第二十一圖為本發明之一實施例,關於電路圖各部與 負載控制電路全體之頻率特性,負載電流從1〇[mA]到 ” 1 0 [ A ],調整偏壓電壓重複模擬之結果的特性如第二十二 圖所示。 關於負載控制用場效電晶體Q1之特性,因汲極電流亦 即負載電流之大小,順向導納y f S亦會變化。尤其是,將 汲極電流設定很小時,閘極電壓會接近夾持(pinch 〇f f ) 電壓,順向導納yfs會變的極小。Specific examples of the non-linear element are shown in FIGS. 19 and 20. The figure 19 shows the case of a 2-terminal non-linear component. It consists of 1 or even n diodes D (l) ~ D (n) 'or resistor RD1 and one or even n diodes ~ DU). 'As shown in Figures 19C and 19D, the structure of a Zener diode ZD (l) can also be incorporated. The twentieth figure is the case of non-linear components of real wheat 3 terminals. The twentieth figure A is an example of the structure of the diode nanodiode ZD (1) and the resistor RD13. The twentieth figure b is the additional resistor RD11 and Example of the configuration of the resistor RD12; FIG. 20C is an example of the configuration of one of the poles DJ 1 on the BJ1 side of the connection point, and n or two of the junctions of the BJ 2 side of the connection point j) j 2 or even m; The twentieth D chart is a configuration example in which the resistor RD11 and the resistor RD12 are added in the constitution example of the twentieth c, but the effects are the same. In addition to diodes, capacitors for frequency compensation can also be used in combination. In order to optimize non-linear characteristics, a combination of resistance and bias can also be used. In addition, 'this embodiment is described using an N-channel transistor, but when using a P-channel transistor, if you change the connection polarity of the non-linear elements shown in Figure 19 and Figure 20, of course, The same effect can be obtained. The twenty-first figure is an embodiment of the present invention. Regarding the frequency characteristics of each part of the circuit diagram and the entire load control circuit, the load current is from 10 [mA] to "10 [A]. The characteristics are shown in Figure 22. Regarding the characteristics of the field-effect transistor Q1 for load control, due to the drain current, that is, the load current, the forward admittance yf S also changes. In particular, the drain current is set For a very small time, the gate voltage will approach the pinch voltage and the forward admittance yfs will become extremely small.

200421061 五、發明說明(15) 第二十二C圖為相對於場效電晶體Q1之閘極電壓的 極電流特性,對於負載電流的變化,在低域頻率下,p “ 約有50[dB]之增幅度變化,頻率區域也會變化。具有 =成回授迴路之習知技術,即使進行頻率寺 補仏以使負載電流之全範圍都能呈安定狀態,但是 二:f f η*:為負回授量大幅不& ’負載電流對於目 才示之§又疋電 >瓜值會有很大的誤差,連 特性也都降低。 Η千匕A及響應 藉由本發明,可以利m # 構成的元#,來補償場效電晶體Q1之負回2 體所 大上:?圖,是將非直線特性元件插入中段的運算放 ::之情形時,負載電流從10[mA]到1〇 直線增幅段的頻率特性,在低域頻率τ,可下非 40 [dB]之增幅度,可以補償場效電晶化 外,將電容C11插入該非直線 之曰巾田度良化。此 程度的補償場效電晶體/之頻率區電路,亦\某 性、第二十二F圖所示之相\第_十;;=示之振幅特 保充分的負回授量與頻率區域寺之除了可以確 振幅餘裕及相位餘裕。 卜亦可確保回授迴路的200421061 V. Description of the invention (15) Figure 22C shows the polar current characteristics relative to the gate voltage of the field effect transistor Q1. For the change of the load current, at a low frequency, p "is about 50 [dB ], The frequency range will also change. With the conventional technique of = feedback loop, even if the frequency compensation is performed to make the entire range of load current stable, but two: ff η *: Negative feedback is significantly less & 'Load current will be very different from the value shown in the previous section> even the characteristics will be reduced. Η Thousands dagger A and the response With the present invention, it can benefit # 组合 的 元 #, to compensate for the negative return of the field effect transistor Q1: The figure is a calculation of inserting a non-linear characteristic element into the middle section :: In the case of a load current from 10 [mA] to The frequency characteristics of the 10 linearly amplified section can be increased by a non-40 [dB] in the low-domain frequency τ, which can compensate for the field effect electro-crystallization, and insert the capacitor C11 into the non-linear line to improve the field quality. Degree of compensation field effect transistor / frequency region circuit, also \ certain, figure 22F The phase shown in the figure is the tenth;; = the amplitude of the shown shows a sufficient negative feedback amount and the addition of the frequency region can determine the amplitude margin and phase margin. Bu can also ensure the feedback loop.

200421061 圖式簡單說明 【圖式簡單說明】 第一圓係習知技術之電子負載裝置之電路構成圖。 第二圖係考慮連接電纜的影響之習知技術的電跟 第三圖係習知技術的電路構成圖。 、圖。 第四圖係本發明專利申請範圍第1項所記載 — 電路構造。 貧細例的 第五A圖〜第五E圖係第三圖之電路構造的特性圖。 第六A圖〜第六E圖係第四圓之電路構造的特性圖。 ==明專利申請範圍第1項所記載之閘極電流測 疋的說明圖。 第八圖係顯示閘極電流測定方法之一例。 第九Α圖〜第九C圖係習知技術之響應特性圖。 ί = 係本發明專利申請範圍第1項所記載之- 貫施例的響應特性圖。 技術之啟動特性的電路構造圖。 第十二圖係、考慮本發明專利申範圍第i項所纪載之 施例的啟動特性之電路構造圖。 ° 貫 第十三A圖〜第十三B圖传習4钍 m + π Α圃m + D @糸I知技術啟動特性圖。 第十四Α圖〜第十四Β圖係本發明 之一實施例的啟動特性圖。 月軏圍第1項所δ己載 第十五圖係本發明專利申請笳 的電路構造圖。 項所記載之一實施例 第十六圖係習知技術之一實施例的 第十七圖係本發明專利申 電路構k圖。 闽系Z項所記載之一實施例200421061 Brief description of the drawings [Simplified description of the drawings] The first circle is a circuit configuration diagram of the electronic load device of the conventional technology. The second figure is a circuit diagram of the conventional technology in consideration of the influence of the connection cable. Figure. The fourth diagram is the circuit structure described in item 1 of the patent application scope of the present invention. The fifth and fifth diagrams A through E are the characteristic diagrams of the circuit structure of the third diagram. Figures 6A to 6E are characteristic diagrams of the circuit structure of the fourth circle. == Explanation diagram of gate current measurement as described in item 1 of the patent application scope. Figure 8 shows an example of a method for measuring the gate current. Figures 9A to 9C are response characteristic diagrams of conventional techniques. ί = is a response characteristic diagram of the embodiment described in item 1 of the scope of patent application of the present invention. Circuit diagram of start-up characteristics of technology. The twelfth figure is a circuit configuration diagram considering the startup characteristics of the embodiment described in item i of the patent application scope of the present invention. ° Through Figures 13A ~ 13B. 4 钍 m + π Α 圃 m + D @ 糸 I Know the technology startup characteristics. Figures 14A to 14B are startup characteristic diagrams of an embodiment of the present invention. The 15th figure of Yueyangwei No. 1 Institute is the circuit structure diagram of the invention patent application 笳. An embodiment described in the item The sixteenth figure is a k diagram of a circuit of a patent application of the present invention. An example recorded in the Fujian Z item

第20頁 200421061 圖式簡單說明 的電路構造區塊圖。 第十八圖係本發明專利申請範圍第2 的電路構造區塊圖。 、所記載之〜訾# 第十九A圖~第十九D圖係本發明專利 的非直線元件之一實施例。 月 第2項所記裁 第二十A圖〜第二十D圖係本發明專利申請範圍第2 的非直線元件之一實施例。 、。己载 第二十一圖係本發明專利申請範圍第2項所記载之一 例的電路構造圖。 第二十二A圖〜第二十二F圖係第二十一圖所記載之電路 造的特性圖。 圖式各元件符號之說明: 放大器 電晶體 電阻 電阻 電容 阻抗 1電子負載裝置 2被測試電源 3連接電纜 V1-V10 A1-A10 Q1 R1-R213 RD1-RD13 C10〜C101 U 〜L32 M 連接電纜之相互阻抗Page 20 200421061 Block diagram of the circuit structure for simple illustration. The eighteenth figure is a block diagram of the circuit structure in the second application scope of the present invention. The recorded ~ 訾 # Figures 19A to 19D are examples of non-linear elements of the patent of the present invention. Fig. 20A to XXD are examples of the non-linear element in the second application scope of the present invention. . The twenty-first figure already contained is an example of a circuit structure described in item 2 of the scope of patent application of the present invention. Figures 22A through 22F are characteristic diagrams of the circuit structure described in Figure 21. Explanation of each component symbol of the diagram: amplifier transistor resistance resistance capacitance impedance 1 electronic load device 2 tested power source 3 connection cable V1-V10 A1-A10 Q1 R1-R213 RD1-RD13 C10 ~ C101 U ~ L32 M mutual connection cable impedance

第21頁 200421061 圖式簡單說明 K3 Dl 、 D(l)〜D(n) ZD1 、 ZD(1) B1 B2 BJ 卜 BJ3Page 21 200421061 Brief description of the drawings K3 Dl, D (l) ~ D (n) ZD1, ZD (1) B1 B2 BJ BU BJ3

XI 連接電纜之耦合係數 二極體 齊納二極體 負載電流檢出裝置 非直線性附加裝置 非直線性附加裝置之連接點 切換裝置XI Coupling coefficient of connecting cable Diode Zener Diode Load current detection device Non-linear additional device Connection point of non-linear additional device Switching device

第22頁Page 22

Claims (1)

200421061 六 1· 、申請專利範圍 - 一種電子負載裝置,其具有一控制電路,# 載電流檢出用之分流電阻串聯連接於作為被5,感與負 源之負載而驅動的負載電流控制電晶體二試交流電 才辱,并 yf/ 使被測試交流電源的輸出電流流動的迴路,以於' ^ 於特定負載電流設定值之閘極驅動電流於該電^ 5符合 2. --電倉恭 y, 1項所記栽之齋、置,其特徵在於在構成申請專利範圍第 體的閘極驅氣子負載裝置之電流控制電路的負載電晶 直線性之雷4用運算放大器之輸出入電壓,採用具有非 <電路裝置。200421061 June 1 ·, patent application scope-An electronic load device having a control circuit, a shunt resistor for #load current detection is connected in series to a load current control transistor driven as a load that is sensed by a negative source The second test of AC power is humiliated, and yf / the circuit that makes the output current of the tested AC power source flow, so that the gate drive current of the set value of the specific load current in the power ^ 5 is in accordance with 2.-Electric warehouse Christine , The item 1 is described in the following paragraphs, which is characterized by the output and input voltages of the four operational amplifiers for the linearity of the load transistor in the current control circuit of the gate drive sub-load device constituting the scope of the patent application. Use non- < circuit devices.
TW92126920A 2003-04-09 2003-09-29 Electronic load apparatus TWI237167B (en)

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CN101206249B (en) * 2006-12-22 2010-09-29 鸿富锦精密工业(深圳)有限公司 Electronic load device
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CN102621410B (en) * 2012-02-26 2014-10-08 云南电力试验研究院(集团)有限公司电力研究院 Test of adopting random waveform power supply to measure voltage current characteristics of mutual inductor and calculation method
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CN104102268B (en) * 2014-07-16 2015-11-25 哈尔滨工业大学深圳研究生院 A kind of constant-current type high-power electronic load control circuit
CN110361570B (en) * 2019-06-25 2021-05-14 深圳市鼎阳科技股份有限公司 Electronic load
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