TWI237167B - Electronic load apparatus - Google Patents

Electronic load apparatus Download PDF

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TWI237167B
TWI237167B TW92126920A TW92126920A TWI237167B TW I237167 B TWI237167 B TW I237167B TW 92126920 A TW92126920 A TW 92126920A TW 92126920 A TW92126920 A TW 92126920A TW I237167 B TWI237167 B TW I237167B
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load
current
load current
voltage
circuit
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TW92126920A
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TW200421061A (en
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Kenji Nitadori
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Keisoku Giken Co Ltd
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Abstract

The present invention is provided to improve the frequency response characteristics of the load current for the tested power device of an electronic load apparatus. In the invention, impedance L1 is connected in series and attached to the source of transistor Q1 for load current control. In addition to improving the frequency response characteristic of the electronic load control loop and the electronic load transient response characteristics at the starting of the power supply to be tested, a better load current control characteristic is obtained in a wide load current range by providing a circuit device of a non-linear element between the input and output of an operational amplifier for the driving transistor of the controlling circuit.

Description

1237167 * 五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種作 (放電後不能再使用)、二次雷5广電源裝置或-次電池 電池等負載而使用的電;複使用)、燃料 電流高速變化之被測試電源,尤其是-種测試負载 【先前技術】 4特性之用的電子負載裝置。 ί:知技術之電子負載裝置與被測試電源之電 子透過連接電欖3,與電子負載裝幻連接,藉由將m 定負載電流IL之電壓Ein設定為電流設定用控制電壓νι,斤 以運算放大器A1比較該電流設定用控制電壓n的輸出盥負 載電流檢出用並聯電阻^的電壓,藉由運算放大器M的輪 出電壓驅動負載電晶體Q1之閘極,產生之負載電流況如 式1。 [數1] IL = Ein/Rl ............••公式11237167 * V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to electricity used as a load (cannot be reused after discharge), a secondary lightning 5 wide-band power supply device, or a secondary battery battery; (Re-use), the power supply under test whose fuel current changes at high speed, especially-a kind of test load [prior art] 4 electronic load device for characteristics. ί: The electronic load device of the known technology and the electronic of the tested power supply are connected to the electronic load through a connection to the electronic load 3, and the voltage Ein of the constant load current IL is set to the current setting control voltage νι, which is calculated by the calculation. The amplifier A1 compares the voltage of the output setting control voltage n with the load current detection shunt resistor ^, and drives the gate of the load transistor Q1 by the output voltage of the operational amplifier M. The load current generated is as shown in Equation 1. . [Number 1] IL = Ein / Rl ............ •• Formula 1

進行被測試電源之動態負載動態測試時,電流設定用 控制電壓會得出不是直流電壓而是交互重複相當於二值負 載電壓值之控制電壓輸出之矩形波或電壓波狀的電壓,或 是任意波形相對於被測試電源的所要之負載電流波形。在 測試對於該負載電流高速變化之被測試電源的特性時,因 為電子負載裝置側要求高的直通率(through rate),所以 由運算放大器A1與負載電晶體Q1構成的負載電流控制迴路 之頻率特性,必須儘可能利用寬區域使控制響應特性達到When the dynamic load dynamic test of the power supply under test is performed, the control voltage for current setting will not be a DC voltage but will alternately repeat a rectangular wave or voltage wave-shaped voltage equivalent to the control voltage output of the binary load voltage value, or any arbitrary voltage. The waveform is relative to the desired load current waveform of the power supply under test. When testing the characteristics of the power supply under test for the high-speed change of the load current, because the electronic load device requires a high through rate, the frequency characteristics of the load current control loop composed of the operational amplifier A1 and the load transistor Q1 , It is necessary to use a wide area as much as possible to achieve control response characteristics

12371671237167

南速。 要達!向速的負載電流流動,連接被測試電源2與電 子負載裝置1的連接電纜3之阻抗(impedance)必須要足夠 的低。雖然若該連接電纜3使用符合負載電流較粗之電镜 日ί ’、I以忽視該影響,但因電纜長度比例所產生的電纜阻 杬成分之增加,會對控制響應特性之高速化產生各種 的影響。South speed. To reach! The load current flows toward the speed, and the impedance of the connection cable 3 connecting the power supply 2 to be tested and the electronic load device 1 must be sufficiently low. Although if the connection cable 3 uses an electron microscope with a larger load current, I and I to ignore this effect, the increase in the cable resistance component due to the cable length ratio will cause various changes in the control response speed. Impact.

第^圖中’為了進行動態負載動態測試,負載電流控 制用電壓V3 ’可以產生一定時間間隔的矩形波電壓,利用 負載電流檢出用並聯電阻R1所檢出之符合負載電流的電壓 f出’及利用運算放大器“,將與前述負載電流控制用電 壓V3之電壓差輸出到增幅的負載電晶體Q1之閘極,並透過 連接電纜3,進行被測試電源2之動態負載動態測試。被測 f電源2是由電壓V2及内部電阻R2所構成。將連接電纜3的 單側線之等效阻抗當作L31及L32,將該一對電缆作成平行 線或絞線,使其磁束相互交叉,將該相互阻抗當作Μ時, 存在於被測試電源2與電子負載裝置丨之間的連接電纜所產 生之阻抗成分,可以視為相當於公式2之L之等效阻抗。 [數2]Figure ^ 'For dynamic load dynamic test, the load current control voltage V3' can generate a rectangular wave voltage at a certain time interval, and the load current is detected using the parallel resistor R1 to meet the load current voltage f. ' And using an operational amplifier ", output the voltage difference from the aforementioned load current control voltage V3 to the gate of the increased load transistor Q1, and perform a dynamic load dynamic test of the power source 2 to be tested through the connection cable 3. The measured f Power supply 2 is composed of voltage V2 and internal resistance R2. Take the equivalent impedance of the single-sided wire of connection cable 3 as L31 and L32, make the pair of cables parallel or twisted, and make their magnetic beams cross each other. When this mutual impedance is regarded as M, the impedance component generated by the connection cable existing between the power supply 2 under test and the electronic load device 丨 can be regarded as the equivalent impedance equivalent to L in Equation 2. [Equation 2]

L = L31 + L32 - 2Μ............••公式2 該連接電纜3之等效阻抗L,在動態負載電流增加時, 會呈如公式3所示之直通率之S,與藉由連接電纜3之電壓 降e如公式4所示之關係式,該電壓降e在接近被測試電源 之直流輸出電壓時,負載電晶體Q1之汲極、源極間的電壓L = L31 + L32-2M ............ • Equation 2 The equivalent impedance L of the connecting cable 3 will show the through rate as shown in Equation 3 when the dynamic load current increases. S, and the relationship between the voltage drop e of the connection cable 3 as shown in Equation 4, when the voltage drop e approaches the DC output voltage of the power supply under test, the voltage between the drain and source of the load transistor Q1

五、發明說明(3) 會達到飽合’從公式5所示之關係式,呈幾乎是公式6之直 通率。 [數3] S = di /dt ···公式3 [數4] e = L X S = L x di/dt …公式4 [數5] L X di/dt = E ···公式5 [數6] S = di/dt = E/L …公式 6 在此’將被測試電源之輸出電壓當作E、負載電晶體 Q1之汲極、源極間電壓的飽合時間當作T,如公式7所示, 在該電壓飽合時間中,負載電流會產生不是原本的電流值 或非巧來的電流波形之情形,而為了防止這樣的影響,習 知之簡便的方法是縮短連接電纜,減少連接電纜的等效阻 抗L,使得到目的直通率之高負載電流波形。 [數7]V. Explanation of the invention (3) It will reach saturation. From the relation shown in formula 5, it shows almost the through rate of formula 6. [Equation 3] S = di / dt ···· Equation 3 [Equation 4] e = LXS = L x di / dt… Equation 4 [Equation 5] LX di / dt = E ··· Equation 5 [Equation 6] S = di / dt = E / L… Equation 6 Here, the output voltage of the tested power supply is regarded as E, the drain of the load transistor Q1, and the saturation time of the source-to-source voltage is regarded as T, as shown in Equation 7. During the voltage saturation time, the load current may generate a current value that is not the original value or an unintentional current waveform. In order to prevent such effects, a convenient and convenient method is to shorten the connection cable, reduce the connection cable, etc. The effective impedance L makes a high load current waveform to the target through rate. [Number 7]

T L X E/Ι…公式7 改變觀點來看,在不論是被測試電源之靜態負載 :、過渡之電流波形之用途*,來試看看連=== 效阻抗大時的舉動;負載電流急速增加時連 2之等 :現象會短時間發生’之後會穩定落在一定的二5飽 ’所以’及時有電壓飽合時間,多半也電流 續。但是,習知技術之電子負載,從電屋飽::=種 1237167TLXE / I ... Equation 7 To change the point of view, whether it is the static load of the power supply under test :, the use of the current waveform of the transition *, let's try to see the behavior when the === effective impedance is large; Level 2 and so on: The phenomenon will happen in a short time, and then it will fall steadily to a certain level, so there will be a voltage saturation time in time, and most of the current will continue. However, the electronic load of the conventional technology is full from the electric house :: = kind 1237167

五、發明說明(4) 中’要防止超過設定電流值之過流(〇ver shunt)問題極為 困難,而必須採取使電壓飽合現象不會發生的範圍之和緩 的直通率負載設定等權宜的裝置。 》 另外的問題之一是,連接電纜的等效阻抗L會對電子 負載控制迴路特性產生很大的影響。若追求高速響應而使 控制迴路的頻率區域放寬時,隨著連接電缆的阻抗L增 大,會使迴路特性的振幅餘裕及相位餘裕減少,產生過流 特性(over shunt),而引起電子負載連續振盪的問題。習 知技術,為了讓連接電纜的阻抗即使增大到某一程度,也 不會發生振盪,會利用第二圖之運算放大器“藉由電容 C10、電阻R10之頻率過濾裝置,降低頻率區域,而大幅犧 牲應答速度。因此,對高速響應之電子負載是很大的障 礙。V. Explanation of the invention (4) 'It is extremely difficult to prevent the over current (0ver shunt) problem that exceeds the set current value, and it is necessary to adopt an expedient load setting such as a gentle through-rate load setting in which the range of voltage saturation will not occur. Device. 》 One of the other problems is that the equivalent impedance L of the connecting cable has a great influence on the characteristics of the electronic load control circuit. If the frequency range of the control loop is widened in response to the pursuit of high-speed response, as the impedance L of the connecting cable increases, the amplitude margin and phase margin of the loop characteristics will decrease, resulting in over-current characteristics and electronic load. The problem of continuous oscillation. In the conventional technology, in order to prevent the impedance of the connection cable from oscillating even if the impedance is increased to a certain level, the operational amplifier of the second figure is used to "reduce the frequency region by using the frequency filtering device of the capacitor C10 and the resistor R10, and The response speed is greatly sacrificed. Therefore, the electronic load for high-speed response is a great obstacle.

以下就電子負載所要求的另一個特性作敘述。考慮到 被測試電源之電源啟動測試時,對於電子負載,多半是在 被測試電源的電源關閉時,預先設定啟動後的負載電流值 或負載阻抗值。此時,電子負載即使在未施加被測試電源 f輸出電麼的狀態下,仍可設定負載電流,所以,負載電 晶體Q1會呈最大驅動應該流動負載電流之閘極電壓。在此 片大態下’在被測試電源的電源打開時,有時會發生大幅超 過過渡性設定負載電流之短路電流流動的情形。這會因電 子負載之負載設定控制迴路之應答速度及被測試電源的輸 出電壓啟動時間而有所差異,但是,習知技術之電子負載 及—般的被測試電源中,會是很大的問題,即檢出電子負The following describes another characteristic required by the electronic load. Considering that during the power-on test of the power supply under test, for electronic loads, most of the time when the power of the power supply under test is turned off, the load current value or load impedance value after startup is preset. At this time, the electronic load can set the load current even when the output power of the tested power source f is not applied. Therefore, the load transistor Q1 will be at the maximum gate voltage that should flow the load current. In this large state, when the power of the power supply to be tested is turned on, a short-circuit current that greatly exceeds the transient setting load current sometimes occurs. This will vary depending on the response speed of the load setting control circuit of the electronic load and the start-up time of the output voltage of the tested power supply. However, the electronic load of the conventional technology and the power supply under test will be a big problem. Electron negative

第8頁 1237167 五、發明說明(5) 載之端子電壓,在該撿出 電壓以下時,將在被測一定的臨界值(threshold) 載電晶體之閘極驅動遮斷 &lt; =的電源關閉時所看不見的負 使負載電流控制迴路動’而在超過臨界值電遷時 测試電源的動作開始時間=裝置。附加該電路,會使被 經常會遮斷負載電流等的;;m值電廢以下時 利文的P早礙產生》參照專利文獻1及專 【專利文獻1】 特開平06-1 1 3450號公報(第4_9項、 【專利文獻2】 第圖) 特開200 1 -1 34326號公報(第〗卜14項、第二圖) 【發明内容】 本發明所欲解決之技術問題 頻Ii ϊ ϋ在於提供一種具有急峻負載電流變動及廣範圍 ίί響應特性之電子負載裝置之電路方式及裝f,其可以 ^如上所述習知之電子負載裝置之課題,減輕在急峻的 ^载電流變動時之電子負載裝置控制迴路特性的響應特 ^ 、電子負載裝置與被測試電源連接電纜之阻抗影響,解 ,從電壓飽合狀態的恢復時間延遲之過流(。ver二; 喊〇 本發明解決問題之技術手段 本發明係一種包含作為被測試電源2之負載而動作之 第9頁 1237167Page 8 1237167 V. Description of the invention (5) When the terminal voltage is below the pick-up voltage, the gate drive of the transistor will be cut off at a certain threshold value (<=). The invisible negative causes the load current control circuit to move, and the test power source's operation start time when the electrical value exceeds the critical value = device. Adding this circuit will cause the load current to be interrupted frequently; P will be caused by Levin ’s P when the value of m is below the level of electrical waste. See Patent Document 1 and Patent [Patent Document 1] JP 06-1 1 3450 (Item 4_9, [Patent Document 2] Figure) JP 200 1 -1 34326 (item 14 and Figure 2) [Summary of the Invention] The technical problem to be solved by the present invention is Ii ϊ ϋ Provided is a circuit method and a device for an electronic load device having a sharp load current variation and a wide range of response characteristics, which can ^ the problem of the conventional electronic load device as described above, and reduce the electronic load in the case of a severe load current variation. Response characteristics of the characteristics of the device control loop, the impedance effect of the electronic load device and the cable connected to the power supply under test, and the overcurrent that delays the recovery time from the voltage saturation state. The present invention includes a page 9 which operates as a load of the power supply 2 under test 1237167

電晶體Q1,與控 制電路的電子負 源極而構成。再 成該控制電路的Transistor Q1 is configured with the negative electron source of the control circuit. Re-form the control circuit

制對應電流設定值 載裝置,將阻抗L1 者,本發明將二極 運算放大器之回授 之電流流入電晶體之控 串聯插入負載電晶體之 體之非直線元件插入構 電路而構成。 本發明對照先前技術之功效 術之Ϊ ΐ Ϊ明,本發明之電子負載裝置,比起習知技 應特料,、載裝置,具有廣範圍之頻率區域的負載電流響 m且不易受到與被測試電源的連接電纜之寄生阻抗 0# = # 1 f以,在被測試電源之急峻負載動態測試及啟動 ^ _ 5平饧測試等,習知技術之電子負載裝置很難進行 變^ Ϊ w本發明之電子負載裝置可以進行這樣的高速負載 警應特性測試。 【實施方式】 以下就參照圖表來說明本發明之實施態樣。 為了避免本申請案件之實施例的說明太繁雜,僅就1 個負載電晶體的情況加以說明,但當然可以因應所必要之 負載電流及負載電力的大小,將包含負載電流控制迴路之 本電路與複數個區塊(b 1 ock )並聯,達到所需要的電子負 Φ 載。 、 專利申請範圍第1項所記載之一實施例,習知技術之 電子負載裝置之基本電路構成如第三圖所示。負載電流控 制用電壓V3之電壓差輸出,會透過電阻Ri〇與從偏移According to the present invention, the load device corresponding to the current setting value is controlled, and the impedance L1 is used in the present invention. The current feedback from the two-pole operational amplifier flows into the transistor. The non-linear element inserted in the body of the load transistor is inserted into the circuit. The present invention contrasts the effectiveness of the prior art. The electronic load device of the present invention has a wider range of load currents in the frequency range and is less susceptible to being affected than conventional techniques. The parasitic impedance of the connection cable of the test power source is 0 # = # 1 f. During the severe load dynamic test and start-up of the test power source ^ _ 5 level test, it is difficult to change the electronic load device of the conventional technology ^ 本The electronic load device of the invention can perform such a high-speed load response characteristic test. [Embodiment] Embodiments of the present invention will be described below with reference to the drawings. In order to avoid that the description of the embodiment of this application is too complicated, only the case of a load transistor will be described, but of course, the circuit of the load current control circuit and the load current control circuit can be included according to the required load current and load power. A plurality of blocks (b 1 ock) are connected in parallel to achieve the required electronic load Φ. An embodiment described in item 1 of the scope of patent application. The basic circuit configuration of the electronic load device of the conventional technology is shown in the third figure. The voltage difference output of the load current control voltage V3 will pass through the resistor Ri0 and the offset

1237167 五、發明說明(7) (Offset)調整用電壓V4 接於運算放大器Al之單 之符合負載電流的電 RU與電容C10分流後, 形成負回授控制迴路, 驅動電晶體Q1,進行以 電子負載測試。 如第三圖所示之習 行其特性的模擬。一般 電路,進行頻率特性之 應,所以運算放大器不 作特性的比較,在此以 行模擬。 ’透過電阻R4輸出的電壓合成,連 侧輸入,負載電流檢出用分流電阻 壓輸出,會透過電阻在平衡電阻 連接於運算放大器A1之單侧輸入, 藉由該運算放大器Ai之電壓輸出, 連接電纜3所連接的被測試電源2之 知技術的電子負載裝置之電路,進 是將C10插入運算放大器人丨之回授 評價,因為很難達到原來的高速響 使用這麼廣區域的情形很多,為了 本發明相同的廣區域運算放大器進 本發明專利申請範圍第1項所記載之一實施例如第四 圖所示,但將阻抗L1串聯插入場效電晶體Q〗之源極。為了 發揮本發明之特徵,使用比場效電晶體Q1之順向導納 (admittance)之頻率特性更充分廣區域且輸出電壓的直通 率更高的運算放大器,連接電纜和被測試電源之輪出電壓 或負載電流設定等也以相同條件,進行模擬比較。 第三圖的電路圖之習知技術的各部頻率特性與回授迴| 路特型如第五圖所示。設定條件為將被測試電源之輸^電 壓V2設定為5 [V]、負載電流設定為約5 [A]之條件,連接電 纜3的單側線之阻抗L31、L32設定為1 [ H]、l〇[以H]、 1〇〇[ //Η]、耦合係數Κ3 = 0. 9 時。1237167 V. Description of the invention (7) (Offset) Adjustment voltage V4 is connected to the load current-carrying electric RU and capacitor C10 of the operational amplifier Al to form a negative feedback control loop to drive transistor Q1 to perform electronic Load test. The simulation of its characteristics is performed as shown in the third figure. The general circuit responds to the frequency characteristics, so the operational amplifier does not compare the characteristics, and it is simulated here. 'The voltage output through resistor R4 is connected to the side input, and the shunt resistor output for load current detection will be connected to the single-sided input of the operational amplifier A1 through the resistor at the balancing resistor, and connected by the voltage output of the operational amplifier Ai. The circuit of the electronic load device of the known technology of the power supply 2 connected to the cable 3 is a feedback evaluation of inserting C10 into the operational amplifier, because it is difficult to achieve the original high-speed response. There are many cases in which such a wide area is used. The same wide-area operational amplifier of the present invention is shown in the fourth embodiment of one of the items described in item 1 of the patent application scope of the present invention, but the impedance L1 is inserted in series to the source of the field effect transistor Q. In order to make use of the features of the present invention, an operational amplifier with a wider frequency range and a higher pass-through rate of output voltage than the field effect transistor Q1's admittance is used to connect the cable and the output voltage of the tested power supply Or load current setting, etc., are simulated and compared under the same conditions. The frequency characteristics and feedback of each part of the conventional technique of the circuit diagram in the third figure are shown in the fifth figure. The setting conditions are that the input voltage V2 of the power supply under test is set to 5 [V], the load current is set to about 5 [A], and the impedances of the single-sided wires of the connection cable L31 and L32 are set to 1 [H], l 〇 [to H], 1〇〇 [// Η], when the coupling coefficient K3 = 0.9.

第11頁 1237167 五、發明說明(8) 第五D圖及第五£圖表示負回授 第五D圖為振幅特性、第五Ε圖為,m,其中 3的阻抗⑶、L32,減少振幅餘裕 错由連接電镜 路頻率特性下,預想有很高峰的頻率特性餘;^,在閉鎖迴 各部分的頻率特性而言,輸入場效 壓的汲極電壓之頻率特性,如第 體Q1之閘極電 規3的阻抗L31、L32,頻率合上第井五不,藉由連接電 ^ f .¾ ^Q1 ^ , ^ ^ r/tPage 11 1237167 V. Description of the invention (8) The fifth D graph and the fifth £ graph indicate negative feedback. The fifth D graph is the amplitude characteristic and the fifth E graph is m. Among them, the impedances 3 and 32 of 3 reduce the amplitude. In the case of the frequency characteristics of the connected electron microscope circuit, the marginal frequency characteristics are expected to be very high; ^, in terms of the frequency characteristics of the latch-back circuit, the frequency characteristics of the drain voltage of the input field effect voltage, such as in Q1. The impedance L31, L32 of the gate gauge 3, the frequency close to the first five, by connecting the power ^ f .¾ ^ Q1 ^, ^ ^ r / t

:具有高♦。在該電壓增幅度變高的頻率下授ς路J ίίΐϊ第i?一般受到很大的影響,呈不安定而引起 連續振盛。為了避免此一現象,在比連接電 L31、L32之共振頻率低之頻率下 A 、、 几 1# 4· β M t r 在輸入分流電阻R1之電壓的 運算放大器A1之輸出電壓以下的頻率特性 示,其落在頻率區域内。 矛立Λ圃所 此外,第三圖及第四圖之電容C30及電阻R30,為 連接電纜的阻抗與場效電晶體…之汲極、源極間寄生容量 之共振現象損失,增加回授迴路的安定性,會採取不影 負載電流波形範圍的阻抗。 將如第四圖所示的專利申請範圍第丨項之一實施例的 電路,同樣亦進行模擬,結果如第六圖所示。各部分的電 壓增幅度之頻率特性,作為輪入分流電阻(R1&amp;R2)兩端之 電壓,運算放大器A1輸出以下之電壓增幅度的頻率特性, 如第六A圖所示,相對於運算放大器A1幾乎無回授的增幅 •---- 第12頁 1237167 的增幅度。輪入場效電晶體Q丨之閘 壓增幅度,會視連接電缦3的等效 抗11插入場效電晶體Q1之源極,所 如第六β圖所示,在中間的頻率區 而是呈幾乎平坦的頻率特性為其特 晶體Q1源極之阻抗L1的值不同,該 變化,但如第六D圖所示,負載電&quot; 增盈及如第六E圖所示的迴路相位 餘裕及相位餘裕,且可選擇最適當 流之分流電阻R 1的輸出電壓之頻率 巡迴路特性之頻率,插入阻抗L2。 電阻固有的阻抗即已足夠,不需要 五、發明說明(9) 且很高 下之電 為將阻 回授會 高峰, 場效電 性會有 的迴路 的增益 域。 負載電 補償一 要分流 度’其呈廣區域 極電壓的沒極以 阻抗而定,但因 以該阻抗之電流 域不會有急峻的 徵。雖然因插入 增幅度和頻率特 流控制迴路全體 特性,都有充分 的值來達到廣區 此時,對於 特性,為了有效 該阻抗L2有時只 外加。 及阻抗L2的頻率特性,將時間常數當作r 分流電阻R1 1時, [數8] r 1 = L2/R1…公式8 為公式8,將工作頻率當作“ [數9] U/il'x Γΐ) =L2 / (2 π X R1)·' 公式9 振幅特性,相將位頻最率^备=界,以高域頻率+6dB/oct2 安定度的頻率補=有效之果進,相位: With high ♦. At the frequency where the voltage increase becomes higher, the circuit J ί ΐϊ ΐϊ i? Is generally greatly affected, which is unstable and causes continuous prosperity. In order to avoid this phenomenon, at a frequency lower than the resonance frequency of the connected electrical L31, L32, A ,, several 1 # 4 · β M tr frequency characteristics below the output voltage of the operational amplifier A1 of the input shunt resistor R1 is shown , Which falls in the frequency region. In addition, the capacitor C30 and resistor R30 in the third and fourth pictures are the loss of resonance between the impedance of the cable and the field effect transistor, and the parasitic capacity between the source and drain, increasing the feedback loop The stability will take the impedance that does not affect the load current waveform range. The circuit of one of the embodiments of the patent application scope shown in the fourth figure is also simulated, and the result is shown in the sixth figure. The frequency characteristic of the voltage increase amplitude of each part is the frequency characteristic of the voltage increase amplitude below the output of the operational amplifier A1 as the voltage across the wheel-in shunt resistor (R1 &amp; R2). As shown in Figure 6A, compared to the operational amplifier Increase in A1 with almost no feedback • ---- Increase in 1237167 on page 12. The increase of the gate voltage of the wheel-in field-effect transistor Q 丨 will be inserted into the source of the field-effect transistor Q1 depending on the equivalent reactance 11 connected to the power source 3, as shown in the sixth β diagram. It has almost flat frequency characteristics. The value of the impedance L1 of the source of its special crystal Q1 is different. This change, but as shown in Figure 6D, the load current & And phase margin, and the frequency of the circuit characteristic of the frequency of the output voltage of the shunt resistor R 1 which is the most appropriate current can be selected, and the impedance L2 is inserted. The inherent resistance of the resistor is enough, and it is not necessary. 5. Invention description (9) and the power is very high. In order to block the peak of the feedback, the field-effect electrical field will have the gain range of the loop. The load electric compensation needs to be shunted, which has a wide range of pole voltage. The poles are determined by the impedance, but because of the impedance, the current domain will not have any severe characteristics. Although the overall characteristics of the insertion amplitude and frequency current control loops have sufficient values to achieve a wide area, at this time, for the characteristics, the impedance L2 may only be applied in order to be effective. And the frequency characteristic of the impedance L2, when the time constant is taken as the r shunt resistance R1 1, [Equation 8] r 1 = L2 / R1 ... Equation 8 is Equation 8, and the operating frequency is taken as "[Equation 9] U / il ' x Γΐ) = L2 / (2 π X R1) · 'Formula 9 Amplitude characteristics, phase frequency is the highest rate ^ preparation = bound, with high-domain frequency + 6dB / oct2 stability frequency compensation = effective fruit, phase

1237167 五、發明說明(10) 此日專,營缺,私7 雷μ植Ϋ1 = + 分流電阻以及阻抗L2檢出的負載 1¾的浊+刀要素之外,也會產生與負載電流不 π ^ ^。亦即,電流控制回授迴路的回授電路之 頻率特性變的不平坦。Α 幻U杈电峪之 户雪踗s 一女从-从為了防止此一現象的方法,是在回 ^ τ U. ^ ^ ^ aff. f 號到負載電流為止的頻率了特二生將/抖負平載土電流f定用輸入訊 嗖定用t e f早特性保持平坦,達到與負載電流 °笛Ξ:'輸出波形同等之負載電流波形。 以該時=a數’H阻RU0並聯插入電容cu〇,為了改善 Μ A 3吊數I· 1決又的頻率更充分高的頻率之頻率特 ^ I i選擇比電阻R1 Q充分小的電阻R11 G之定數值。此 -rn η I 3作Ϊ差動輸入訊號動作,會以與電阻R10與電 谷Clio同4的吊數,插入電阻RU與電容C111。 2,以下就有助於一回授迴路特性的安冑度之效果 口带^ B 。相對於作為負載電晶體之場效電晶體的閘極輸 入電壓之汲極電流的頻率特性,順向導納yfs之特性,一 般的功率MOSFET電晶體時’會以卜1〇[MHz]左右為邊界逐 漸降低。考慮寄生於場效電晶體内部的靜電容量之源極電 流,除了會流動以順向導納yfs之特性決定的沒極電流之 外’間極源極間容量之閘極電流,也會與源極重疊。 為了忠實檢出除了閘極電流以外之負載電流,會考慮 第八圖之方法。分流電阻雖然會正確檢出含閘極電流的^ f電流,但是,順向導納會隨著頻率的增大而變為零,伴 隨很大的相位延遲,使迴路特性產生不好的影響。1237167 V. Description of the invention (10) Today's special, business shortage, private 7 Thunder μ plant 1 = + shunt + knife element of load 1¾ detected by shunt resistance and impedance L2, it will also produce no load current π ^ ^. That is, the frequency characteristic of the feedback circuit of the current control feedback loop becomes uneven. Α Magic U 峪 电 峪 之 户 雪 踗 s A female slave-To prevent this phenomenon, the method is to return the frequency up to the load current ^ τ U. ^ ^ ^ aff. The input characteristics of the shake-negative flat-load earth current f are fixed and the early characteristics of tef are kept flat, achieving a load current waveform that is equivalent to the load current. At this time = a number 'H resistance RU0 is inserted in parallel with the capacitor cu〇, in order to improve the frequency characteristics of the frequency higher than the frequency of M A 3 I 1 1 ^ I i choose a resistance sufficiently smaller than the resistance R1 Q R11 G fixed value. This -rn η I 3 acts as a Ϊ differential input signal, and will insert the resistor RU and capacitor C111 with the same number as the resistor R10 and the valley Clio. 2. The following will contribute to the effect of the safety of the feedback loop characteristics. Oral band ^ B. Relative to the frequency characteristics of the drain current of the gate input voltage of the field-effect transistor as a load transistor, the characteristics of yfs are admissible. In general power MOSFET transistors, the boundary is about 10 [MHz]. Gradually decreases. Considering the source current of the electrostatic capacitance that is parasitic inside the field effect transistor, in addition to the non-polar current that is determined by the characteristics of the admittance yfs, the gate current of the inter-source-to-source capacity is also related to the source. overlapping. In order to faithfully detect the load current other than the gate current, the method of Figure 8 will be considered. Although the shunt resistor will correctly detect the ^ f current including the gate current, the forward admittance will become zero as the frequency increases, with a large phase delay, which will adversely affect the circuit characteristics.

第14頁 1237167Page 14 1237167

。丄:二藉ΐ如第七圖之本發明的電路,因為並非 /、檢出負載電流’也可以檢出包含 η 所以’在高頻率下的相位延遲可抑制:爭,載電流, 載電流之缺點,但因為是比負載檢出貫際的負 八古从此t二 疋貝戰電流所必須的頻率區域十 :冋的頻率’…匕起負載電流’其閑極電流值十分低, 所以該影響純,但對高頻振盪等之安定度具有十分的效 果0 以上之頻率區域的習知技術與本發明之特性已比較說 明如上,以迴路增益是1時的頻率來看,本發明幾乎可以 達到1 00倍之廣區域化,對於連接電纜的阻抗之變化,振 幅餘裕與相位餘裕都更勝一籌。 其次,就時間領域的特性,以模擬來比較習知技術與 本發明。 關於負載電流之響應特性,習知技術之電路圖如第三 圖所示、本發明之電路圖如第四圖所示,設定條件為將被 測試電源之輸出電壓V2設定為5[v]、負載電流設定訊號V3 之波形啟動時間為1 [ //S]、負載電流設定為〇〜5[A]、連接 電纜3的單側線之阻抗L31、L32,設定單侧線為1 [ &quot; η]、 10[ //Η]、100[ //Η]、耦合係數Κ3 = 0·9,以模擬求出負載 _ 電流波形。 第九圖為習知技術、第十圖為本發明之結果,第九A 圖、第十A圖為負載電流設定訊號V3之波形;第九B圖、第 十B圖為場效電晶體Q1之汲極源極間之電壓;第九C圖、第.丄: Secondly, the circuit of the present invention as shown in the seventh figure, because the load current is not detected / can also be detected including η, so the phase delay at high frequencies can be suppressed: contention, load current, load current Disadvantages, but because it is more than the load to detect the current negative Bagu from now on, the frequency range necessary for the current is 10: the frequency of 冋, the load current is very low, so the effect is very low. Pure, but has a very high effect on the stability of high-frequency oscillations, etc. The conventional technology of the frequency region above 0 and the characteristics of the present invention have been described in comparison with the above. From the frequency when the loop gain is 1, the present invention can almost achieve With a wide area of 100 times, the amplitude margin and phase margin are better for the change in the impedance of the connection cable. Next, the characteristics of the time domain are compared with the conventional technology and the present invention by simulation. Regarding the response characteristics of the load current, the circuit diagram of the conventional technology is shown in the third diagram, and the circuit diagram of the present invention is shown in the fourth diagram. The setting conditions are to set the output voltage V2 of the power supply to be tested to 5 [v], and the load current. Set the waveform start time of the signal V3 to 1 [// S], set the load current to 0 ~ 5 [A], the impedance of the single-sided line of the connection cable L31, L32, and set the single-sided line to 1 [&quot; η], 10 [// Η], 100 [// Η], coupling coefficient KK3 = 0 · 9, to simulate the load_current waveform. The ninth picture is the conventional technology, the tenth picture is the result of the present invention, the ninth picture A and the tenth picture A are the waveforms of the load current setting signal V3; the ninth picture B and the tenth picture B are field effect transistors Q1 Voltage between the drain and source of the drain;

第15頁 1237167 五、發明說明(12) 十C圖為負載電流波形。 習知技術下,即使連接電纜3的阻抗小時,因為沒極 源極電壓不是飽合的狀態’控制糸統之頻率區域不足,所 以啟動時間會變慢;而連接電纜3的阻抗變大時,從飽合 到回復過程,會產生設定電流大幅超過之過流狀況。 其次,關於被測試電源啟動測試時之響應特性,習知 技術之電路圖以第十一圖、本發明之電路圖以第十二圖說 明。兩者均將負載電流設定電壓VI預先設為負載電流 ^ 5,[ A ],模擬被測試電源啟動,從無輸出電壓到定袼輸出電 壓啟動之輸出電壓波形,置換到台形波產生器”,設定啟 動時間為1[ //S]時,輸出電壓為5 [V]之條件,連接°電窥3 的單側線之阻抗L 31、L 3 2,設定單側線為1 [ # η ]、1 〇 [ # Η]、1 00 [ // Η]、耦合係數Κ3 = 0· 9,以模擬求出負載電流波 形。 、 第十三圖為習知技術、第十四圖為本發明之結果,第 十三Α圖、第十四Α圖為相當於被測試電源2之輸出波 形;第十三B圖、第十四B圖為負載電流。在習知技術中, 被測試電源啟動以前所設定的負載電流應流動的場效 =體Qk閘極電壓會呈最大限度的驅動,使被測試電源 &gt; &amp;所以,一旦極大負載電流流動之結果,即使是電流· ί^路的動作’因為作為控制系統之頻率補償而插入運 11 =回授電路之電容cl〇,結果會使運算放大器輸 持績π Ϊ直通率會變得極慢,回到設定電流值的時間也會 、、、· κ長。因為這會依存頻率補償電路的方式,所以將運 第16頁 1237167 五、發明說明(13) 异放大器更廣區域化是無法解決的。這對進行被測試電源 啟動測試的電子負載是很致命的,而權宜的對策,就是必 須設置如前述之負載電流遮斷電路,為其缺點所在。 依據本發明如第十四B圖所示之負載電流波形圖,可 以達到不管連接電缆3的阻抗之大小,都極少會發生負載 電流過流的情形。 第十五圖為將阻抗L1連接於負載電晶體之源極,透 過該源極L1連接負載電流檢出用分流電阻^,第十六圖為 將負載電流檢出用分流電阻R1連接於負載電晶體Q1之源 極,透過該負載電流檢出用分流電阻Μ連接於阻抗I〗,本 發明是在分流電阻R1的兩端,差動檢出負載電流進行回授 控制,所以,以阻抗L1及分流電阻R1之順序連接於負載電 日日體Q1之源極’並不損本發明之效果。Page 15 1237167 V. Description of the invention (12) Figure 10C is the load current waveform. Under the conventional technology, even if the impedance of the connection cable 3 is small, the start-up time will be slow because the frequency range of the control system is not sufficient because the non-polar source voltage is not saturated. When the impedance of the connection cable 3 is increased, During the process from saturation to recovery, an over-current condition in which the set current is greatly exceeded will occur. Secondly, regarding the response characteristics of the tested power supply during the start-up test, the circuit diagram of the conventional technology is illustrated in Fig. 11 and the circuit diagram of the present invention is illustrated in Fig. 12. Both set the load current setting voltage VI to the load current ^ 5, [A] in advance, simulating the output voltage waveform from the start of the power supply under test to starting from the fixed output voltage and replacing it with a table wave generator. " When the startup time is set to 1 [// S], the output voltage is 5 [V], the impedance of the single-sided line connected to ° Telescope 3 is L 31, L 3 2, and the single-sided line is set to 1 [# η], 1 〇 [# Η], 1 00 [// Η], coupling coefficient κ3 = 0.9, and the load current waveform is obtained by simulation., The thirteenth figure is the conventional technology, and the fourteenth figure is the result of the present invention. Figures 13A and 14A are output waveforms corresponding to the power supply 2 under test; Figures 13B and 14B are load currents. In the conventional technology, the settings are set before the power supply under test is started. The field effect that the load current should flow = the body Qk gate voltage will be driven to the maximum, so that the tested power supply &gt; &amp; so, once the result of a large load current flow, even the current As the frequency compensation of the control system, insert the capacitor 11 of the feedback circuit. Making the operational amplifier's output performance π Ϊ through rate will become extremely slow, and the time to return to the set current value will also be long,…, κ. Because this will depend on the frequency compensation circuit, it will be operated on page 16 1237167 V. Explanation of the invention (13) The wider regionalization of different amplifiers cannot be solved. This is fatal to the electronic load for the start-up test of the tested power supply, and an expedient countermeasure is that a load current blocking circuit must be provided as described above. According to the present invention, the load current waveform diagram shown in FIG. 14B can achieve that the load current overcurrent rarely occurs regardless of the impedance of the connection cable 3. The fifteenth figure is Connect the impedance L1 to the source of the load transistor, and connect the shunt resistor for load current detection through the source L1. Figure 16 shows the shunt resistor R1 for load current detection to the source of the load transistor Q1. The shunt resistor M is connected to the impedance I through the load current detection. The present invention uses a differential detection load current at both ends of the shunt resistor R1 for feedback control. Therefore, the impedance L The order of 1 and the shunt resistor R1 is connected to the source of the load sun-body Q1 'without impairing the effect of the present invention.

其 例,其 輪出到 載裝置 均可呈 更詳細 放大器 個適當 晶體之 件插入 壓而變 次,專 原理以 輸入端 的負載 高速響 的說明 代表負 的運算 最終段 負回授 化。 利申請 第十七 子,藉 電流可 應及安 。在第 載電流 放大器 的運算 電路, 範圍第2項所記載之本發明_ 圖及第十八圖表示。從運算 由插入二極體等非直線元件 以從極小到很大的電流,在 定的動作。以下就圖面及模 十七圖及第十八圖中,是以 控制電路之增幅部,但亦可 ’在驅動負載控制用電晶體 放大器中,藉由將二極體等 增幅度可以對應場效電晶體 放大 ,電 廣範 擬結 1個ϋ 使用 之場 非直 的閘For example, its wheel-to-load device can be changed in more detail by inserting a suitable crystal. The principle is based on the description of the high-speed response of the load on the input side, which represents the negative operation. The final stage is negative feedback. Lee applied for the seventeenth son, and he was able to respond to the problem with electricity. The operational circuit of the current-carrying amplifier is shown in Fig. 18 and Fig. 18 of the invention as described in the second item. Slave operation By inserting non-linear elements, such as diodes, a small current to a large current, a fixed action. The following figure and the seventeenth and eighteenth figures are based on the control circuit's amplifier, but it can also be used to drive the load control transistor amplifier, which can correspond to the field by increasing the diode and the like. The effect transistor is enlarged, and the electric range fan intends to close a ϋ field non-straight gate.

1237167 五、發明說明(14) 非直線元件的具體例如第十九圖 十九圖為實裝2端子之非直線元件的情形第-二第 〜D(n)構成’如第十九c圖、第十九㈣所示體=) 納一極體(Zener diode)ZD(1)之構成。第二十 1 端子之非直線元件的情形,第二十A圖為二極,&quot;〗貫/3 納二極體ZD(1)及電阻RD13之構成例;第_ 盼、背 阻Rim及電阻RD12之構成例;第 圖為附加電 :極體Dn-個乃至_,連接點Bm則之二極體奶 ,個之構成例;第二十0圖為前述第二十c圖構成 乃 加電阻RD11及電阻心12之構成例,但效果都是相同的。除 可並用頻率補償用之電容,為了將非直線 特〖生最適化,亦可適當組合電阻及偏壓(bias)等使用。 此外,本實施例是以N通道之電晶體來說明的,但 用p通道之電晶體時,若變更第十九圖及第二十圖所示之 非直線性元件之連接極性,當然也可得到同樣之效果。 第二十一圖為本發明之一實施例,關於電路圖各部與 負載控制電路全體之頻率特性,負載電流從j 〇 [ m A ]到 10 [A],調整偏壓電壓重複模擬之結果的特性如第二十二 圖所示。 關於負載控制用場效電晶體Q1之特性,因汲極電流亦 即負載電流之大小,順向導納y f S亦會變化。尤其是,將 沒極電流設定很小時,閘極電壓會接近夾持(pinch 〇ff) 電壓,順向導納y f S會變的極小。1237167 V. Description of the invention (14) Specific examples of non-linear components Fig. 19 Figure 19 shows the case of non-linear components mounted with 2 terminals.-2nd ~ D (n) configuration 'as shown in Figure 19c, The body shown in the nineteenth stage =) The structure of a Zener diode ZD (1). In the case of a non-linear component of the 21st terminal, the twentieth A picture is a two-pole, &quot;〗 / 3 nano-diode ZD (1) and an example of the composition of the resistor RD13; Example of the configuration of the resistor RD12; the figure is an example of the additional electricity: the electrode body Dn-a or even _, and the connection point Bm is the example of a diode milk or a body; The configuration examples of the resistor RD11 and the resistor core 12 have the same effect. In addition to using capacitors for frequency compensation in combination, in order to optimize non-linear characteristics, it is also possible to use a combination of resistance and bias. In addition, this embodiment is described with an N-channel transistor. However, when using a p-channel transistor, it is of course possible to change the connection polarity of the non-linear elements shown in Figure 19 and Figure 20. Get the same effect. The twenty-first figure is an embodiment of the present invention. Regarding the frequency characteristics of each part of the circuit diagram and the entire load control circuit, the load current is from j 0 [m A] to 10 [A]. As shown in the twenty-second figure. Regarding the characteristics of the field-effect transistor Q1 for load control, the sink current y f S also changes due to the drain current, that is, the magnitude of the load current. In particular, when the non-polar current is set to be very small, the gate voltage will approach the pinch voltage and the forward admittance y f S will be extremely small.

第18頁 1237167 1、發明說明(15) ~~ ~^- 第二十二C圖為相對於場效電晶體Q1之閘極電壓的汲 極電流特性’對於負載電流的變化,在低域頻率下,隨著 約有50 [dB]之增幅度變化,頻率區域也會變化。具有此特 性構成負載電流控制回授迴路之習知技術,即使進行頻率 補償,以使負載電流之全範圍都能呈安定狀態,但是在微 小負載電流時,因為負回授量大幅不足,負載電流對於目 標之設定電流值會有很大的誤差,連帶使頻率區域及響應 特性也都降低。 “ 藉由本發明,可以利用以具有非直線特性之二極體所 構成的元件,來補償場效電晶體Q1之負回授量之變動。 第二十二B圖是將非直線特性元件插入中段的運算放 大器之情形時,負載電流從10[111幻到1〇[幻的變化下之非 直線增幅段的頻率特性,在低域頻率下,可以變化約 40 [dB]之增幅度,可以補償場效電晶體之增幅度變化。此 外,將電容C11插入該非直線增幅段之回授電路,亦可某 程度的補償場效電晶體段之頻率區域的變動,負載電流押 制電路的總和迴路特性,由第二十二㈣所示之振幅特= 性、第二十二F圖:斤不之相位特性可以知道,除了可以確 保充分的負回授量與頻率區域之外,亦可確保回授迴路的 振幅餘裕及相位餘裕。Page 1237167 1. Description of the invention (15) ~~ ~ ^-Figure 22C shows the characteristics of the drain current relative to the gate voltage of the field-effect transistor Q1 'for changes in load current at low frequency Next, with an increase of about 50 [dB], the frequency region also changes. The conventional technology that has this characteristic to form a load current control feedback loop, even if frequency compensation is performed so that the entire range of the load current can be stable, but at a small load current, the load current is greatly insufficient because of the negative feedback amount. There will be a large error in the set current value of the target, and the frequency region and response characteristics will also be reduced. "With the present invention, an element composed of a diode with non-linear characteristics can be used to compensate for the change in the negative feedback amount of the field-effect transistor Q1. Figure 22B shows the insertion of a non-linear characteristic element in the middle In the case of an operational amplifier, the frequency characteristic of the non-linear gain section under the change of load current from 10 [111 magic to 10 [magic] can be changed by about 40 [dB] in the low-domain frequency, which can be compensated. Variation of the field effect transistor. In addition, inserting the capacitor C11 into the feedback circuit of the non-linear amplifier section can also compensate the variation of the frequency region of the field effect transistor section and the sum of the circuit characteristics of the load current holding circuit. The amplitude characteristic shown by the twenty-second ㈣ = characteristic, the twenty-second F figure: You can know the phase characteristics of Jinbu, in addition to ensuring sufficient negative feedback amount and frequency region, you can also ensure feedback The amplitude and phase margins of the loop.

I237l67I237l67

圖式簡單說明 C圖式簡單說明】 ίIf係習知技術之電子負載裝置之電路構成圖。 第二阁係考慮連接電纜的影響之習知技術的電路構成圖。 一圖係習知技術的電路構成圖。 電本發明專财請範圍第1項所記載之—實施例的 :f A圖〜第五£圖係第三圖之電路構造的特性圖。 ’、A圖〜第六E圖係第四圖之電路構造的特性圖。 ί =係本發明專利申請範圍第1項所記載之問極電流測 疋的說明圖。 第八圖係顯示閘極電流測定方法之一例。 第九Α圖〜第九C圖係習知技術之響應特性圖。 ΐ 乂圖二ΐ十°圖係本發明專利申請範圍第1項所記載之-實施例的響應特性圖。 第十:圖係考慮習知技術之啟動特性的電路構造圖。 第十二圖係考慮本發明專利申請範 ㈣㈣㈣$貝尸I己戰之π 第十三Α圖〜第十三Β圖係習知技術之啟動特性圖。 第十四A圖〜第十四b圖将太日奎立· ^眘γ ^ Μ π去圖係本發月專利申請範圍第1項所記載 之一實施例的啟動特性圖。 第十五圖係本發明專利申諳笳園 的電路構造圖。 明範圍第1項所記載之-實施例 第十六圖係習知技術之一實施例的電 第十七圖係本發明專利申請範構仏圖。 靶圍第2項所記載之一實施例Simple illustration of the diagram C Simple description of the diagram ίIf is a circuit configuration diagram of the electronic load device of the conventional technology. The second cabinet is a circuit configuration diagram of a conventional technique that considers the influence of connecting cables. A picture is a circuit configuration diagram of the conventional technology. According to the description in item 1 of the scope of the present invention, the figures: f A to F5 of the embodiment are characteristic diagrams of the circuit structure of the third figure. ', A to sixth E diagrams are characteristic diagrams of the circuit structure of the fourth diagram. ί = is an explanatory diagram of the interrogator current measurement described in item 1 of the scope of patent application of the present invention. Figure 8 shows an example of a method for measuring the gate current. Figures 9A to 9C are response characteristic diagrams of conventional techniques.乂 乂 Figure 20 and Figure 10 are response characteristics of the embodiment described in item 1 of the patent application scope of the present invention. Tenth: The diagram is a circuit configuration diagram considering the starting characteristics of the conventional technology. The twelfth figure is a consideration of the patent application scope of the present invention. Figure 13A through 13th B are startup characteristic diagrams of conventional technologies. Figures 14A to 14B show Tairi Kuili · ^ Shen γ ^ π π to Figure 1 is a startup characteristic diagram of an embodiment described in item 1 of the scope of this month's patent application. The fifteenth figure is a circuit configuration diagram of the patent application park of the present invention. The embodiment described in item 1 of the scope of the present invention-the sixteenth figure is an example of an example of conventional technology. The seventeenth figure is a schematic diagram of a patent application for the present invention. Example of target item 2

第20頁 1237167 圖式簡單說明 的電路構造區塊圖 f十八圖孫本發明專利申請範圍第? 的電路構造區塊圖。 2項所記載之一實施例 第十九A圖〜第十九D圖係太狢蜜 的非直線元件之一實施例。專利申請範圍第2項所記載 ^ =十A圖~第二十D圖係本發明專利申請範圍第2項所記載 的非直線元件之一實施例。 圖係第二十一圖所記載之電路構 · 第一十一圖係本發明專利申請範圍第2項所記載之一實施 例的電路構造圖 第一十二A圖〜第 造的特性圖。 圖式各元件符號之說明: 1電子負載裝置 2被測試電源 3連接電纜 V1-V10 電源 A1-A10 放大器 Q1 電晶體 R1-R213 電阻 RD1-RD13 電阻 CIO〜C101 電容 U 〜L32 阻抗 Μ 連接電缆之相互阻抗Page 20 1237167 Block diagram of the circuit structure for simple illustration f. Figure 18. The scope of patent application for this invention? Block diagram of the circuit construction. One of the embodiments described in two items Figures 19A to 19D are examples of non-linear elements of the honey. Document ^ described in item 2 of the scope of patent application ^ = Figures A through Twenty-D are examples of non-linear elements described in item 2 of the scope of patent application of the present invention. The diagram is the circuit structure described in the twenty-first diagram. The eleventh diagram is a circuit structure diagram of an embodiment described in item 2 of the patent application scope of the present invention. Explanation of the symbols of each component of the figure: 1 Electronic load device 2 Power supply to be tested 3 Connection cable V1-V10 Power supply A1-A10 Amplifier Q1 Transistor R1-R213 Resistor RD1-RD13 Resistor CIO ~ C101 Capacitor U ~ L32 Impedance M Connection cable Mutual impedance

1237167 圖式簡單說明 K3 Dl 、 D(l)〜D(n) ZD1 、 ZD(1) B1 B2 BJ1〜BJ31237167 Brief description of drawings K3 Dl, D (l) ~ D (n) ZD1, ZD (1) B1 B2 BJ1 ~ BJ3

XI 連接電纜之耦合係數 二極體 齊納二極體 負載電流檢出裝置 非直線性附加裝置 非直線性附加裝置之連接點 切換裝置XI Coupling coefficient of connecting cable Diode Zener Diode Load current detection device Non-linear additional device Connection point of non-linear additional device Switching device

第22頁Page 22

Claims (1)

1237167 、申請專利範圍 一種電子負载裝置,I且古一 載電流檢出用之分流^阻=二,制電路,係將電感與負 源之負載而驅動的負栽雷^二 於作為被測試交流電 #電流控制電晶體夕、、塔H # |被測試交流電源的輪丨f^ “、 、 - “ f-佘:動的迴路,以輸出符合 於特定負載電机汉弋值之閘極驅動電流於該電晶體。 2. —種電子負載裝置’其特徵在於在構成申請專利範圍第 1項所記載之電子負載裝置之電流控制電路的負載電晶 體的閘極驅動用運其放大器之輸出入電壓,採用具有非 直線性之電路裝置。1237167, the scope of the application for an electronic load device, the current shunt used for the detection of the current of the first load ^ resistance = two, the system is a load that is driven by the load of the inductor and the negative source ^ 2 as the tested alternating current #Current Control Transistor Xi 、、 塔 H # | The wheel of the AC power source to be tested 丨 f ^ ",,-" f- 佘: a moving circuit to output the gate drive current that meets the threshold of the specific load motor To the transistor. 2. —An electronic load device 'characterized in that the input and output voltages of its amplifiers are used to drive the gate of the load transistor that constitutes the current control circuit of the electronic load device described in item 1 of the patent application. Sexual circuit device.
TW92126920A 2003-04-09 2003-09-29 Electronic load apparatus TWI237167B (en)

Applications Claiming Priority (1)

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JP2003105718A JP3470296B1 (en) 2003-04-09 2003-04-09 Electronic load device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101206249B (en) * 2006-12-22 2010-09-29 鸿富锦精密工业(深圳)有限公司 Electronic load device
CN101498753B (en) * 2008-02-01 2011-04-13 中茂电子(深圳)有限公司 Load apparatus for regulating operation frequency range according to impedance of article to be measured, and regulation method thereof
CN102621410B (en) * 2012-02-26 2014-10-08 云南电力试验研究院(集团)有限公司电力研究院 Test of adopting random waveform power supply to measure voltage current characteristics of mutual inductor and calculation method
JP5210448B1 (en) * 2012-11-01 2013-06-12 株式会社計測技術研究所 Load device
CN104102268B (en) * 2014-07-16 2015-11-25 哈尔滨工业大学深圳研究生院 A kind of constant-current type high-power electronic load control circuit
CN110361570B (en) * 2019-06-25 2021-05-14 深圳市鼎阳科技股份有限公司 Electronic load
CN115185326B (en) * 2021-04-07 2023-08-01 炬芯科技股份有限公司 Active load circuit and active load module

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