TW200416820A - Aligner, alignment method and semiconductor device manufacturing method - Google Patents

Aligner, alignment method and semiconductor device manufacturing method Download PDF

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Publication number
TW200416820A
TW200416820A TW092128128A TW92128128A TW200416820A TW 200416820 A TW200416820 A TW 200416820A TW 092128128 A TW092128128 A TW 092128128A TW 92128128 A TW92128128 A TW 92128128A TW 200416820 A TW200416820 A TW 200416820A
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TW
Taiwan
Prior art keywords
pattern
wafer
exposure
aforementioned
mask
Prior art date
Application number
TW092128128A
Other languages
Chinese (zh)
Inventor
Shinichiro Nohdo
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Sony Corp filed Critical Sony Corp
Publication of TW200416820A publication Critical patent/TW200416820A/en

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Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7084—Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography
    • G03F9/7073—Alignment marks and their environment
    • G03F9/7076—Mark details, e.g. phase grating mark, temporary mark
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/5442—Marks applied to semiconductor devices or parts comprising non digital, non alphanumeric information, e.g. symbols
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Electron Beam Exposure (AREA)

Abstract

The present invention satisfactorily maintains the connecting accuracy between complementarily divided areas even when, for example, a shot rotation in substrate pattern occurs and, in addition, suppresses the deterioration of yield as much as possible at the time of forming a pattern through complementary division. At the time of transferring a pattern by using a complementarily divided mask (4), alignment marks (3a, 3b) are put on the scribed line (2) of a wafer 1 to be exposed and, at the same time, commonly used by the adjacent original pattern regions in a shared state. In addition, the wafer (1) is aligned relatively to the complementary mask (4) by optically detecting the alignment marks (3a, 3b) and alignment marks (5a, 5b) put on the mask (4).

Description

200416820 欢、發明說明： 【發明所屬之技術領域】 本發明係有關半導體裝置之製程之微影工序中所使用之 曝光裝置及對準方法，以及有關使用該等所進行之半導體 裝置之製造方法。 【先前技術】 近年半^^體瓜置之製程隨著應形成之積體電路圖案之 微細化，以往使用一般紫外線之光微影法已超過光學系統 之解像度限度，故開發使用電子束或離子束等電荷粒子束 4田晝之被細加工技術。作為微細加工技術，例如： (Low Energy E-beam Proximity Projection Lithography :低 月b i彳又影式電子束近接微影）技術係為人所知。此LEEPL技 術中’於被曝光體之晶圓之正上方約5 q A m之位置，設置電 子束透過型之圖規光罩（Stencil Mask)，進行近接曝光，藉 此以轉印微細圖案至晶圓上。 然而，LEEPL技術所使用之圖規光罩在其性質上例如： 甜甜圈形狀圖案一般，由於產生中心空白等，故有不能形 成之圖案形狀。又，例如：關於線及間距圖案，視該長度 亦可能導致圖案倒塌，故有無法形成之情況。由此，關於 圖規光罩’必須將不能形成之圖案形狀互補性地分割，組 合使用該分割後之圖案。具體而言，例如：如圖3 A及圖3B 所示’所謂四分割互補光罩係作為LEEPL技術中所使用之 圖規光罩而設計；該四分割互補光罩，其係互補性地四分 割應轉印至晶圓上之原圖案1 〇，同時將該分割後之各圖案 87369 200416820 排列為2x2 ’於分別之圖案區域配置對應該圖案之開口部i j ’並進一步採用為了補強光罩之樑構造12者。 使用四分割互補光罩進行圖案轉印時之轉印順序係例如 圖4A至圖4D所示。亦即，如圖4A所示，一次轉印2x2排列 之各圖案後（步驟1 )，使晶圓與四分割互補光罩之相對位置 僅移動1圖案區域份（例如：將分割互補光罩朝右方錯開）， 如圖4B所示，再度一次轉印2X2之各圖案（步驟2)。其後， 使晶圓與四分割互補光罩之相對位置朝別的方向僅移動1 圖案區域份（例如：將分割互補光罩朝上方錯開），如圖4C 所示 夂轉印2x2之各圖案（步驟3)，並進一步使晶圓與四 分割互補光罩之相對位置朝別的方向僅移動丨圖案區域份（ 例如：將分割互補光罩朝左方錯開），如圖4D所示，再度一 次轉印2x2之各圖案（步驟4)。藉此，原圖案1〇係復原並轉印 於進行4次曝光之部分。 此時，於晶圓與四分割互補光罩之間，每當使其相對位 置移動時，須要進行用以互相定位之對準。對準通常係分 別光學檢出預先標示於晶圓上之特定處之對準標記（以下 稱「晶圓標記」），及與此同樣而標示於四分割互補光罩之 對準標記（以下稱「光罩標記」），根據該檢出結果，控制晶 圓或四分割互補光罩之位置而進行。200416820 Description of the invention: [Technical field to which the invention belongs] The present invention relates to an exposure device and an alignment method used in a lithography process of a semiconductor device manufacturing process, and a method of manufacturing a semiconductor device using these. [Previous technology] In recent years, with the miniaturization of the integrated circuit pattern that should be formed, the conventional light lithography method using ordinary ultraviolet light has exceeded the resolution limit of the optical system, so the use of electron beams or ions was developed. Beam isocharged particle beam 4 Tian Tianzhi fine processing technology. As the microfabrication technology, for example: (Low Energy E-beam Proximity Projection Lithography: Low Moon Bi-Ion Electron Beam Proximity Lithography) is known. In this LEEPL technology, an electron beam transmission type Stencil Mask is set at a position of about 5 q A m directly above the wafer of the object to be subjected to close exposure to transfer the fine pattern to On the wafer. However, the plan photomasks used by LEEPL technology are, for example, in the form of donut-shaped patterns, and there is a pattern shape that cannot be formed because of a center blank. For example, regarding the line and space pattern, depending on the length, the pattern may collapse, so it may not be formed. Therefore, regarding the plan mask ', it is necessary to divide the shapes of the patterns that cannot be formed complementarily, and use the divided patterns in combination. Specifically, for example, as shown in FIG. 3A and FIG. 3B, the so-called four-part complementary reticle is designed as a plan reticle used in LEEPL technology; the four-part complementary reticle is complementary to four The division should be transferred to the original pattern 10 on the wafer. At the same time, the divided patterns 87369 200416820 are arranged as 2x2 'the openings ij' corresponding to the patterns are arranged in the respective pattern areas and further used to strengthen the mask Beam structure 12 people. The transfer sequence when using a four-part complementary reticle for pattern transfer is shown in Figs. 4A to 4D. That is, as shown in FIG. 4A, after transferring the 2x2 array patterns in one step (step 1), the relative position of the wafer and the quadrant complementary mask is moved by only 1 pattern area (for example, the split complementary mask is facing toward The right side is staggered), as shown in FIG. 4B, each pattern of 2X2 is transferred again (step 2). After that, the relative position of the wafer and the quadruple complementary mask is moved by only 1 pattern area in other directions (for example, the split complementary mask is shifted upward), as shown in FIG. 4C. 2x2 patterns are transferred. (Step 3), and further move the relative position of the wafer and the quadruple complementary photomask in other directions by only 丨 the pattern area (for example, stagger the split complementary photomask to the left), as shown in FIG. 4D, again Each pattern of 2x2 is transferred (step 4). Thereby, the original pattern 10 is restored and transferred to a portion subjected to 4 exposures. At this time, whenever the relative position of the wafer and the quadruple complementary mask is moved, alignment for mutual positioning is required. Alignment is usually performed by optically detecting an alignment mark (hereinafter referred to as a "wafer mark") marked in advance on a specific location on a wafer, and an alignment mark (hereinafter referred to as a "quadrature complementary mask") "Mask mark"), based on the detection result, control the position of the wafer or the quadruple complementary mask.

光子才双出係使用二軸之SLA •政射光對準）光學系統而進行。例如：圖5A所示，SLA光 學系統係具備：光源21、鏡22、物鏡23及CCD (Charge Coupled Device ·電荷耦合元件）攝像部24，以光學檢出晶 87369 200416820 圓上之晶圓標記及四分割互補光罩避之光 且，例如：圖5B所示，由四分 不。己者。 此種SLA光學系統若配置於χΐ:”:二：上面觀察’ 各轴之對準標記，可分別辨識卿之1:上之二， 移及旋轉成分，以及X1轴之—軸上 車上之戌向的偏 於各軸，CCD攝像部24檢出例如 之偏移。亦即， 3!及可能位於其間之光罩桿紀41ϊ故；^不之1對晶圓標記 ^ ^ 铩。己41，故错由辨識分別之曹、、 置，可得知偏移量或旋轉量若根據該辨識杜果、 ，制晶圓30或四分割互補光罩4Q之位置’可使該等不 產生偏移或旋轉等而進行定位（對準）。 + 其中，為了進行此種光學檢出’對準標記(晶圓標記及光 罩標§己)亦必須於2x2之各圖案區域，對應χΐ、” 之夂 軸而配置。此乃由於晶圓30與四分割互補光罩4〇之相對： 置係以2X2排列之各圖案區域作為_單位而㈣所H 者：配置於各圖案區域之對準標記中，關於晶圓標記，可 經過例如：對於晶圓30以-般之光微影形成圖帛，以乾式 蝕刻賦予0.3/zm程度之階差後，除去光阻之步驟，實現二 應各軸之配置。 若-面進行以上對準，一面於作為被曝光體之晶圓3〇之 全面重複進行上述曝光動作（圖案轉印處理），則於該晶圓％ 上，原圖案10將以規則地排列之狀態（具體而言，矩陣配置 之狀態）而被轉印。且，規則地排列之各圖案之間係作為用 以切割各圖案之部分（成為半導體裝置之晶片之部分）之割 線（典型為100# m寬）而使用。一般而言，此稱為劃線之區 87369 416820 域上係標示晶圓標記3 1。 然而，先前之對準標記中’晶圓3〇上之晶圓標記31個別 對應分別之各圖案區3或而配置。例如：若考慮關於三袖似 對準之各軸，於分別之各圖案區域係配置對心 之各轴之1對晶圓標記。故，於劃線上，如圖6八及圖讀 丁。隔著互相鄰接之圖案區域之境界線32，關於分別之圖 案區域之晶圓標記31a、31b係排列而配置，例如：對應一 方之區域之yl之晶圓標記31a與對應另一方之區域之”之 晶圓標記31b排列。因此’先前之對準標記將產生以下所述 之困難點。 女已次明者，晶圓標記31a、3lb藉由對於晶圓川之光微 影進行圖案形成而形成即可，然而，藉由該光微影進行圖 案幵V成之卩不所形成之底層圖案若發生照射旋轉，後續使用 四刀割互補光罩40進行圖案轉印時，各互補分割區域間之 轉印圖案之連接精度恐將惡化。亦即，如圖7Α所示，若底 層圖案正確排列，後_即使進行使用四分割互補光罩扣之 圖案轉印，互補間之連接精度仍良好。然而，如圖7Β所示 ，例如：若底層圖案於進行圖案形成之際，產生1 V㈤ ad(rad弪度）之妝射旋轉，則後續使用四分割互補光罩4〇 進订圖案轉印時’該旋轉成分將造成不良影響，各互補分 剔區域間產生定位偏差。具體而言，假設晶片大小為麵 之U况表大务生4〇 nm ( = 1 cr2mx 1 〇_6radx2)之互補偏差， 結果將無法對應關於5G nm世代之半導體裝置之互補曝光。 :又而。用以製造半導體裝置之微影工序係經過 87369 200416820 對於數十層之層（Layer)之製程，然而，若於劃線上配置考 慮其製私範圍之複數個晶圓標記，亦恐標記配置區域不足 1言之’標記配置區域不足之情況，必須擴張劃線，故 減少由1片晶圓所能獲得之半導體裝置之數目，結果恐導致 半導體裝置之良率之惡化。 因此，本發明之目的在於提供一種曝光裝置、對準方法 及半導體裝置之製造方法，其係在藉由互補分割形成圖案 之情況，即使例如：於因其之底層圖案發生照射旋轉，亦 可良好保持互補分割區域間之連接精度，並且可極力抑制 良率惡化者。 【發明内容】 ’配置用以進行前述曝光用光罩與前述晶圓之定位之對準 標記’同時以鄰接之前述圖案區域彼此共有前述劃線區域 之對準標記者。 本發明係為了達成上述目的而設計之曝光裝置。亦即， 種曝光▲置’其特徵在於：使用具有互補性地分割原圖 案之圖案之曝光用光罩’―面使該曝光用光罩與作為被曝 光體之晶圓之相對位置移動’ 一面進行複數次曝光，於前 述晶圓上，使前述原圖案規則地排列而進行圖案轉印；且 於位在前述晶圓上規則地排列之前述圖案之間之劃線區域 又本發明係為了達成上述目的而設計之對車 即’ -種對準方法，其特徵在於:於使用具有 割原圖案之圖案之曝光用光罩…面使該曝光用光罩與被 曝光體之晶圓之相對位置移動，—面進行複數次曝光，於 87369 200416820 别述晶圓上，使前述圖案規則地排列而進行圖案轉印時， 為了前述曝光用光罩與前述晶圓之定位而使用者；且於位 在則述晶圓上配置規則地排列之圖案之各區域間之劃線區 域，配置用以進行前述曝光用光罩與前述晶圓之定位之對 準標記，同時以配置鄰接之圖案之各區域共有位於前述劃 區或之對準軚记，分別光學檢出配置於前述劃線區域之 對準標記及配置於前述曝光用光罩之對準標記，根據該檢 出結果’進行前述曝光用光罩與前述晶圓之相對的定位。 〗又’本發明係為了達成上述目的而設計之半導體裝置之 製仏方法。亦即，其特徵在於··經過微影工序而製造半導 體裝置之製造方法，兮與旦/壯变〆 μ 〃衫装置係使用具有互補性地分宝j 原圖案之圖案之曝光用# ° g ^ 用先罩，一面使該曝光用光罩與被曝 先脰之日日圓之相對位置移動 夏矛夕勳一面進仃稷數次曝光，於前 逃日日圓上，使配置前诚 安# . 引11圖案之各區域規則地排列而進行圖 案轉印者；且於前诚外_旦/ 曰 p衫工序進行前述曝光用光罩與前述 曰曰圓之疋位之際，配冑& fm n U 置為了该定位之對準標記，於位在配 置刚述日日圓上規則地排 ， 圖案之各區域之間之劃線區域 同日年以鄰接之原圖幸 對準標記。 *£域彼此共有位於前述劃線區域之 根據上述構成之曝丼 步驟之半導體裝置之上述步驟之對準方法及上述 域共有劃線上之對準；法’以配置圖案之鄰接之各區 案形成之際產生照射；轉己：:;即使例如：該對準標記之圖 ,. °亥疑轉成分亦被取消。故，其 根據該共有之對準俨々 j攸取肩故，右 ，進行曝光用光罩與晶圓之相對的 87369 -10- 200416820 定位，即使藉由互補分割之圖案形成之情況，亦可獲得良 好之互補間之圖案連接。又，藉由共有對準標記，可削減 该對準標記數，藉此亦可縮小作為標記配置區域之劃線。 【實施方式】 以下，根據圖式，說明關於本發明之曝光裝置、對準方 法及半導體裝置之製造方法。在此，舉例進行藉由LEEpL 技術之四分割互補曝光之情況之例。 首先，說明曝光裝置之概要。在此所說明之曝光裝置係 半導體裝置之製程之微影工序中所使用者。進一步詳細而 言，其係使用電子束透過型之圖規光罩，轉印形成於該圖 規光罩上之圖案至半導體晶圓，為了藉此於半導體晶圓上 形成彳政細之電路圖案而使用者。 此曝光裝置所使用之圖規光罩係對應LEEPL技術者。亦 即四分割互補光罩，其係具有互補性地分割應轉印於晶圓 上之原圖案之圖案，且分割後之各圖案排列為2χ2而配置， 並進一步採用為了補強光罩之樑構造者。 曝光裝置係使用此四分割互補光罩，一面使其與晶圓之 相對位置移動，一面進行複數次之曝光。&，進行以此曝 光裝置之曝光後，於曝光對象物之晶圓上，應轉印之原圖 案係在規則（例如：矩陣狀）排列之狀態下而轉印。 又，曝光裝置係一面使晶圓與四分割互補光罩之相對位 置移動，―面進行複數次之曝光，故具有為了每次都進行 •十準而進行互相疋位之機能。具體而言，與已經說明之先 刖之情況大致相同，其係具備三軸之SLA光學系統，使用 87369 200416820 人 光干系統，分別檢出預先標示於晶圓上之晶圓標記 及標示於分割互補光罩之光罩標記。 …、而，在此所說明之曝光裝置中，進行對準之際作為根 據之對準標記，特別是其中之晶圓標記具有重大的特徵。 圖1A圖ic係表不晶圓標記之配置例之說明圖。如圖1八所 示，關於位於晶圓丨上規則地排列之各圖案區域間之劃線2 上之點係與先前者大致相同，然@，本實施型態所說明之 晶圓標記並非如先前一般，個別對應分別之各圖案區域而 配置，而疋以鄰接之圖案區域彼此共有i對晶圓標記化、讣 而配置。 此日寸，共有之晶圓標記3 a、3b亦可與三軸之slA光學系 統中之至少y 1’及y2之各軸對應。亦即，關於分開配置於各 圖案區域之相對端緣附近之yl、y2之各軸，其晶圓標記& 、3 b係於劃線2上共有，然而，關於對應χ1之晶圓標記（但 不圖示）亦可不與鄰接之圖案區域彼此共有，而與先前相同 配置於各圖案區域。 此種晶圓標記3若以下述之步驟形成即可。具體而言，與 先前大致相同，例如：經過以一般之光微影對於晶圓丨形成 圖案，以乾式蝕刻賦予0.3 // m程度之階差後，除去光阻之 步驟即可。其中，形成圖案之際，由於以鄰接之圖案區域 彼此共有1對晶圓標記3 a、3 b，故對於一方之圖案區域進行 圖案形成時’對於1對晶圓標記3中之一方進行圖案形成， 對於另一方之圖案區域進行圖案形成時，對於1對之晶圓標 記3中之另一方進行圖案形成。進一步具體而言，例如··於 87369 -12- 200416820 圖1A中之左侧之區域之圖素形a、。士 X茶形成時，形成晶圓標記3a，於 同圖中之右側之區域之圖案形成時，形成晶圓標記儿。 其次’說明關於使用如以上形成之晶圓標記3a、3b，曝 光裝置進行對準之情況之步驟，亦即說明本發明之對準方 法。再者’關於使用對準所必須之四分割互補光罩之轉印 顺序由於與先刖之情況大致相同（參考圖从至4D)，在此 省略其說明。 士圖1B至圖1C所π，對準係藉由使用三軸之SLA光學系 先光子榀出日日圓1上之晶圓標記3a、3b及四分割互補光罩 上之光罩‘ 5己5a、5b ’使分別之重心對準而移動晶圓1或 四分割互補光罩4。 其中，此時於書丨]魂2卜，丨、/抑w + 深2上以鄰接之圖案區域彼此共有1對 晶圓標記3a、3b。,欠，對準之際，鄰接之圖案區域彼此亦 /'有1對aa m己3a、3b。具體而言，鄰接之圖案區域彼此 中，一方之區域之對準之際，如圖1B所示，對於劃線2上之 對日日圓；^ σ己3a、3b，使四分割互補光罩4上之關於例如： yl之光罩標記5a之重心對準，另一方之區域之對準之際， 圖C所不，對於劃線2上之1對晶圓標記3 a、3 b，使四分 」互補光罩4上之關於例如：y2之光罩標記5b之重心對準。 ，如此，使晶圓標記3a、3b與光罩標記5a、几之重心位置 對準可於晶圓1及四分割互補光罩4之間不產生偏移或旋 轉而進:丁疋位(對準)。且，該對準之際所使用之晶圓標記h 西為郯接之圖案區域彼此所共有者。故，若根據該晶圓 〇b進行對準’不僅進行晶圓1及四分割互補光罩4 87369 之間的定值 如已經說明者， 圖案形成時，亦可 使為此種情況，若 圓標記3 a、3 b，則 取消。 亦可獲得以下所述之優點。 用以形成晶圓標記3a、3b之底層圖案之 能發生照射旋轉（參考圖7B)。然而，即 以鄰接之圖案區域彼此共有劃線2上之晶 藉由該照射旋轉所產生之旋轉成分將被 "及圖2Β為圖案形成時之產生照射旋轉之情況之 =己之配置例之說明圖。如圖2Α所示，於劃線2上共有 昭1:::、3b之情況’即使底層圖案於圖案形成之際產 ’’、、、疋轉’各晶圓標記3a、3b均往相反之方向偏離。總 :射=圓標記3a、3b之重心位置不變。因此，即使產 、疋轉，違方疋轉成分亦被取消。此係如圖2B所示 改變晶圓標記之分割方法之情況亦完全相同。 故’根據如上述之共有之晶圓標記3a、3b進行對準時 '即使底層圖案於圖案形成時發生照射旋轉，該旋轉成分; 被取消，故對Μ互補分割區域間之轉印圖案之連接精乂 3成旋轉偏差的影響。亦即，即使為藉由互補分割开 h 圖案，情況，亦可獲得良好之互補間之圖案連接精度，^ 果可獲得實現高精度之四分割互補曝光之優點。藉此亦; 充分對應例如：關於5G nm世代之半導體I置之互補曝光。 又，於劃線2上共有晶圓標記3a、3b之情況，藉由 爾晶圓標記數’藉此亦可縮小作為標記配置區域：書彳 線2。總§之’縮小晶旧上用於劃線2之區域，可充分 圖案區域’故由〗片晶圓1可獲得之半導體裝置之數目將不 87369 14 200416820 曰減J，結果可獲得避免半導體裝置之良率惡化之優點。 再者，上述實施型態中係說明適用本發明於UEPL技術 ，凊况為例，然而無需贅述，本發明並不限定於此，即使 為^ $體製程之微影工序中所使用之其他微細加工技術， 亦可几全同樣適用。又，與此相同，互補分割亦不限定於 本貫施型態所說明之四分割互補曝光者。 產業上之利用可能性 如以上說明，根據本發明之曝光裝置、對準方法及半導 體裝置之製造方法，由於以鄰接之原目帛區域彼此共有劃 線上之對準標記，故於藉由互補分割形成圖案之情況，即 使例士因其之底層圖案發生照射旋轉，亦可避免因該照 射旋轉所造成之不良影m好保持互補分割區域間之 連接精度。且，經由削減晶圓標記數，可縮小作為標記配 置區域之劃線之縮小化。由該等理由，若適用本發明於藉 由互補分割形成圖案之情況，可實現高精度之互補連接精 度，同時可極力抑制半導體裝置之良率惡化。 【圖式簡單說明】 圖1A〜圖1C係表示適用本發明之對準標記之配置例之說 明圖’圖1A為劃線上之晶圓標記之例之示意圖，·圖a及圖 1C為晶圓標記及光罩標記之例之示意圖。 圖2A及圖2B係表示關於適用本發明之對準標記之圖案 時之產生照射旋轉之情況之配置例之說明圖m為其一 例之示意圖，圖2B為其他例之示意圖。 ” ” 圖3A及圖3B係表 示四分割互補光罩之一 具體例之說明 87369 15 200416820 圖 圖4A〜圖4D係表示使用四分割互補光罩進行圖案轉印之 情況之轉印順序之一例之說明圖。 Θ 5A圖5Ci丁、表示二軸SLA光學系統之一例之說明圖。圖 5A係表示其概略構成圖，圖5B為三軸之配置例之示意圖， 圖5C為對準標記之檢出例之示意圖。 圖6A及圖6B係表示先前之對準標記之配置例之說明圖。 圖7A及圖7B係表示底層圖案之排列例之說明圖。圖了八為 底層圖案正確排列之狀態圖 照射旋轉之狀態圖。 【圖式代表符號說明】 2 3、 3a、3b、31、3 la、3 lb 4、 40 5a v 5b 10 11 12 21 22 23 24 32 圖7B係表示於底層圖案產生 劃線 晶圓標記 四分割互補光罩 光罩標記 原圖案 開口部 樑構造 光源 鏡 物鏡 CCD攝像部 境界線 87369The photon dual output is performed using a two-axis SLA (political light alignment) optical system. For example, as shown in FIG. 5A, the SLA optical system is provided with a light source 21, a mirror 22, an objective lens 23, and a CCD (Charge Coupled Device) imaging unit 24 to optically detect wafer marks on a circle of 87369 200416820 and The four-part complementary reticle avoids light and, for example, as shown in FIG. 5B, it is not divided by four. Oneself. If this SLA optical system is arranged on χΐ: ": 2: Observe the alignment marks of each axis, you can distinguish the components of 1: 1: 2, moving and rotating components, and X1-the vehicle on the axis The orientation is deviated from each axis, and the CCD imaging unit 24 detects, for example, an offset. That is, 3! And the mask rod period 41 which may be located therebetween; ^ No. 1 pair of wafer marks ^ ^ 己. Ji 41 Therefore, it is wrong to identify the difference between Cao, and Zhi. It can be known that if the offset or rotation is based on the identification, the position of the wafer 30 or the quadruple complementary reticle 4Q can be made without bias. Positioning (alignment) by moving or rotating, etc. + Among them, the alignment marks (wafer marks and photomask marks) must also be located in each pattern area of 2x2, corresponding to χΐ, " Y axis. This is due to the relative relationship between the wafer 30 and the quadruple complementary mask 40: The arrangement is based on the pattern areas arranged in a 2X2 array as the unit, which is arranged in the alignment marks of each pattern area. For example, the wafer 30 can be patterned with a light-like lithography, and a step of 0.3 / zm is given by dry etching, and then the photoresist is removed to realize the configuration of the two axes. If the above-mentioned alignment is performed on one side, and the above-mentioned exposure operation (pattern transfer processing) is repeated on one side of the wafer 30 as the object to be exposed, the original pattern 10 will be regularly arranged on the wafer%. The state (specifically, the state of the matrix arrangement) is transferred. In addition, the regularly arranged patterns are used as scribe lines (typically 100 #m wide) for cutting portions of each pattern (become a portion of a wafer of a semiconductor device). Generally speaking, this area called scribe line 87369 416820 is marked with wafer mark 31. However, among the previous alignment marks, the wafer marks 31 on the 'wafer 30' are individually arranged corresponding to the respective pattern areas 3 or. For example, if we consider the axes of the three-sleeve-like alignment, one pair of wafer marks on each axis of the center are arranged in the respective pattern areas. Therefore, on the scribing line, see Figure 6-8 and Figure D. With the boundary line 32 of adjacent pattern areas, the wafer marks 31a and 31b of the respective pattern areas are arranged, for example, the wafer mark 31a of the yl corresponding to one area and the area corresponding to the other " The wafer marks 31b are aligned. Therefore, the 'previous alignment marks will cause the following difficulties. For women who are less clear, the wafer marks 31a and 3lb are formed by patterning the light lithography of the wafer. That is, however, if the underlying pattern that is not formed by the pattern is formed by the light lithography, if the underlying pattern is irradiated and rotated, and the pattern is transferred using the four-knife complementary mask 40 for subsequent pattern transfer, The connection accuracy of the transferred patterns may deteriorate. That is, as shown in FIG. 7A, if the bottom layer pattern is correctly aligned, even if the pattern transfer using the four-part complementary photomask buckle is performed, the connection accuracy between the complements is still good. However, As shown in FIG. 7B, for example: if the underlying pattern is subjected to a pattern rotation of 1 V㈤ ad (rad 弪 degree) during pattern formation, a four-part complementary mask 40 is used for pattern transfer This rotation component will cause adverse effects, resulting in positioning deviations between the complementary decimation regions. Specifically, assuming that the size of the wafer is a surface of the U-shaped table, the complementary deviation of 40nm (= 1 cr2mx 1 〇_6radx2), As a result, it will not be able to correspond to the complementary exposure of the semiconductor devices of the 5G nm generation.: Again. The lithography process used to manufacture semiconductor devices has undergone a process of 87369 200416820 for dozens of layers. However, if it is on a scribe line, The configuration considers the multiple wafer marks in its private area. It is also feared that the mark allocation area is less than 1. If the mark allocation area is insufficient, the scribing must be expanded, so the number of semiconductor devices that can be obtained from one wafer is reduced. As a result, the yield of the semiconductor device may be deteriorated. Therefore, an object of the present invention is to provide an exposure device, an alignment method, and a method for manufacturing a semiconductor device, which are used to form a pattern by complementary division, even if, for example: Due to the irradiation and rotation of the underlying pattern, the connection accuracy between the complementary divided regions can be well maintained, and the deterioration of the yield can be suppressed as much as possible. [Summary of the invention] 'Arrangement of alignment marks for positioning of the aforementioned exposure mask and the wafer' and sharing the alignment marks of the scribe areas with the adjacent pattern areas at the same time. The present invention is directed to An exposure device designed to achieve the above-mentioned purpose. That is, a type of exposure set is characterized in that an exposure mask having a pattern that complementaryly divides an original pattern is used to make the exposure mask and the object to be exposed. The relative position of the wafer is shifted, and multiple exposures are performed. On the wafer, the original patterns are regularly arranged for pattern transfer; and between the aforementioned patterns regularly arranged on the wafer. The scribe region is another alignment method designed to achieve the above-mentioned purpose. It is characterized by using an exposure mask with a pattern with a cut original pattern ... The relative position of the wafer of the exposed object is moved, and multiple exposures are performed on the surface. On the 69369 200416820 separate wafer, the aforementioned patterns are regularly arranged for pattern conversion. For the positioning of the exposure mask and the wafer; and a scribe line region between the regions in which the regularly arranged pattern is arranged on the wafer is arranged to perform the exposure light. The alignment marks of the positioning of the mask and the aforementioned wafer, and the areas where the adjacent patterns are arranged share the alignment marks located in the aforementioned zone or areas, and the alignment marks arranged in the aforementioned scribe areas are optically detected and arranged in The alignment mark of the exposure mask is used to perform relative positioning of the exposure mask and the wafer based on the detection result. The present invention is a method for manufacturing a semiconductor device designed to achieve the above-mentioned object. That is, it is characterized by a manufacturing method for manufacturing a semiconductor device through a lithography process, and the micro-shirt device is for exposure using a pattern with a complementary original pattern. # ° g ^ Use the mask first, while moving the relative position of the exposure mask and the exposed Japanese yen to Xia Maoxixun, and make several exposures, and escape the Japanese yen to make the configuration before Cheng An #. 引11 areas where the patterns are regularly arranged for pattern transfer; and when the aforementioned exposure mask and the aforementioned position of the circle are carried out in front of the front _Dan / p-shirt process, matching & fm n U is set as the alignment mark for this positioning, and is arranged regularly on the Japanese yen just arranged, and the dashed area between the areas of the pattern is aligned with the adjacent original picture on the same day. * The domains share with each other the alignment method of the above steps of the semiconductor device in accordance with the above-mentioned exposure steps and the alignment on the domains with the domains; the method is formed by arranging adjacent areas of the pattern. On the occasion of irradiation; turn yourself ::; even if for example: the map of the alignment mark, the ° suspect transfer component is also canceled. Therefore, according to the common alignment, the right and left positions of 87369 -10- 200416820 relative to the wafer are used for the positioning of the exposure mask and the wafer, even if the pattern is formed by complementary division. Get good pattern connections between complements. In addition, by sharing the alignment marks, the number of the alignment marks can be reduced, thereby reducing the scribe line as a mark arrangement area. [Embodiment] Hereinafter, an exposure apparatus, an alignment method, and a manufacturing method of a semiconductor device according to the present invention will be described with reference to the drawings. Here, an example of a case where the four-part complementary exposure by the LEEpL technology is performed is exemplified. First, the outline of an exposure apparatus is demonstrated. The exposure device described here is a user used in a lithography process of a semiconductor device manufacturing process. In more detail, it uses an electron beam transmission type photomask to transfer a pattern formed on the photomask to a semiconductor wafer, so as to form a thin circuit pattern on the semiconductor wafer. And users. The plan photomask used in this exposure device is compatible with LEEPL technology. That is, a four-division complementary reticle, which is a pattern that complementaryly divides the original pattern that should be transferred on the wafer, and the divided patterns are arranged in a 2 × 2 arrangement, and further uses a beam structure to strengthen the reticle. By. The exposure device uses this four-part complementary reticle to perform multiple exposures while moving its relative position to the wafer. & After the exposure with this exposure device, the original pattern to be transferred on the wafer to be exposed is transferred in a regular (eg, matrix) arrangement. In addition, the exposure device moves the relative position of the wafer and the four-part complementary reticle while carrying out multiple exposures. Therefore, it has the function of positioning each other in order to perform the ten-point calibration each time. Specifically, it is roughly the same as the case of the previous description, which is a three-axis SLA optical system, using the 87369 200416820 human light-drying system to detect the wafer marks pre-marked on the wafer and marked on the division Mask mark for complementary mask. ... In the exposure apparatus described here, the alignment mark is used as the basis for alignment, and especially the wafer mark has significant characteristics. FIGS. 1A and 1C are explanatory diagrams showing an example of the arrangement of wafer marks. As shown in Figure 18, the dots on the scribe line 2 between the pattern regions regularly arranged on the wafer are substantially the same as the former, but @, the wafer marks described in this embodiment are not as In the past, generally, each pattern area was individually arranged, and the adjacent pattern areas were arranged i. In this day, the common wafer marks 3a, 3b can also correspond to each axis of at least y1 'and y2 in the three-axis slA optical system. That is, regarding the axes of yl and y2 separately arranged near the opposite end edges of the respective pattern areas, the wafer marks & 3b are shared on the scribe line 2. However, the wafer marks corresponding to χ1 ( (But not shown) may not be shared with adjacent pattern regions, but may be disposed in each pattern region in the same manner as before. Such a wafer mark 3 may be formed by the following steps. Specifically, it is substantially the same as before, for example, the steps of removing the photoresist may be performed after forming a pattern on the wafer with a general photolithography and applying a step difference of about 0.3 // m by dry etching. Among them, when a pattern is formed, a pair of wafer marks 3 a and 3 b are shared with adjacent pattern areas. Therefore, when patterning one pattern area, 'form one of one pair of wafer marks 3'. When patterning is performed on the pattern area of the other party, patterning is performed on the other of the pair of wafer marks 3. More specifically, for example, the pixel shape a, of the region on the left side in FIG. 1A in 87369-12-12200416820. When the X tea is formed, the wafer mark 3a is formed, and when the pattern is formed in the area on the right side in the same figure, the wafer mark is formed. Next, a description will be given of the steps in the case where the exposure is performed by using the wafer marks 3a and 3b formed as described above, that is, the alignment method of the present invention will be described. Furthermore, since the transfer order of the four-part complementary reticle required for alignment is almost the same as that of the first case (refer to the figure from 4D to 4D), the description is omitted here. Figure 1B to Figure 1C. Alignment is performed by using three-axis SLA optics to advance the photon to the wafer marks 3a, 3b on the Japanese yen 1 and the mask on the quadruple complementary mask. 5b 'Align the respective centers of gravity and move the wafer 1 or the four-part complementary reticle 4. Among them, at this time in the book 丨] soul 2 bu, / / w + depth 2 with a pattern region adjacent to each other, there is a pair of wafer marks 3a, 3b. On the occasion of alignment, the adjacent pattern areas also have a pair of aa m 3a, 3b. Specifically, when the adjacent pattern areas are aligned with one of the areas, as shown in FIG. 1B, for the pair of Japanese yen and Japanese yen on the scribe line 2; ^ σ 3a, 3b, the four-part complementary mask 4 For example, the alignment of the center of gravity of the mask mark 5a of the yl and the alignment of the other area is not shown in Figure C. For a pair of wafer marks 3a and 3b on the scribe line 2, make four The centroid on the complementary mask 4 is, for example, aligned with the center of gravity of the mask mark 5b of y2. In this way, aligning the center of gravity of the wafer marks 3a and 3b with the mask marks 5a and Gui can advance without offset or rotation between the wafer 1 and the four-part complementary mask 4: quasi). In addition, the wafer mark h west used in the alignment is shared by the pattern areas connected to each other. Therefore, if the alignment is performed based on the wafer 0b, not only the fixed value between the wafer 1 and the quadruple complementary reticle 4 87369, as already explained, can also be the case when the pattern is formed. Mark 3 a, 3 b, then cancel. The advantages described below can also be obtained. The underlying patterns used to form the wafer marks 3a, 3b can be irradiated (see Fig. 7B). However, if the adjacent pattern areas share each other with the crystals on the scribe line 2, the rotation component generated by the irradiation rotation will be " and Fig. 2B shows the case where the irradiation rotation occurs when the pattern is formed = own configuration example Illustrating. As shown in FIG. 2A, in the case where there is a total of 1 :::, 3b on the scribe line 2, even if the underlying pattern is produced at the time of pattern formation, the wafer marks 3a and 3b are reversed. The direction is off. Total: The position of the center of gravity of the shot = circle marks 3a, 3b is unchanged. Therefore, even if the production and turnover are reversed, the offending component of the offending party is also cancelled. This is also the case when the method of dividing the wafer mark is changed as shown in FIG. 2B. Therefore, when the alignment is performed according to the common wafer marks 3a and 3b as described above, even if the underlying pattern is irradiated and rotated during pattern formation, the rotation component is canceled, so the connection pattern of the transfer pattern between the M complementary divided regions is fine.乂 30% of the effect of rotation deviation. That is, even if the h pattern is split by complementary division, a good pattern connection accuracy between complementarities can be obtained, and the advantage of achieving high-precision quadrant complementary exposure can be obtained. Take this as well; fully correspond to, for example, the complementary exposure of semiconductors in the 5G nm generation. In the case where the wafer marks 3a and 3b are shared on the scribe line 2, the number of wafer marks can be reduced by using the number of wafer marks': book line 2. In general, 'the area used for the scribe line 2 on the wafer is reduced, and the area can be fully patterned', so the number of semiconductor devices available from the wafer 1 will not be 87369 14 200416820, which will reduce J, and as a result, semiconductor devices can be avoided. The deterioration of the yield rate. Furthermore, the above-mentioned implementation mode is described as applying the present invention to UEPL technology. In the case, it is an example. However, it is not necessary to repeat it. The present invention is not limited to this. The processing technology can be applied to almost all the same. Also, similarly, the complementary division is not limited to the four-division complementary exposure described in this implementation. As described above, the industrial application possibility. According to the exposure device, alignment method, and semiconductor device manufacturing method of the present invention, the alignment marks on the scribe line are shared with each other by adjacent original mesh areas, so they are divided by complementation. In the case of forming a pattern, even if the irradiated rotation of the underlying pattern occurs, it is possible to avoid the bad image caused by the irradiated rotation so as to maintain the connection accuracy between the complementary divided regions. In addition, by reducing the number of wafer marks, it is possible to reduce the size of the scribe line as a mark arrangement area. For these reasons, if the present invention is applied to the case where a pattern is formed by complementary division, a highly accurate complementary connection accuracy can be achieved, and at the same time, deterioration of the yield of the semiconductor device can be suppressed as much as possible. [Brief description of the drawings] FIGS. 1A to 1C are explanatory diagrams showing an example of the arrangement of alignment marks to which the present invention is applied. FIG. 1A is a schematic diagram of an example of a wafer mark on a scribe line. Schematic diagram of examples of marks and mask marks. Fig. 2A and Fig. 2B are explanatory diagrams showing a configuration example of a case where irradiation rotation occurs when the pattern of the alignment mark of the present invention is applied. Fig. M is a schematic diagram of one example, and Fig. 2B is a schematic diagram of another example. ”” FIG. 3A and FIG. 3B are illustrations showing a specific example of a four-part complementary reticle 87369 15 200416820 FIG. 4A to FIG. 4D are examples of the transfer sequence in the case of pattern transfer using a four-part complementary reticle Illustrating. Θ 5A is an explanatory diagram showing an example of a two-axis SLA optical system. FIG. 5A is a schematic configuration diagram, FIG. 5B is a schematic diagram of an example of a three-axis arrangement, and FIG. 5C is a schematic diagram of an example of detecting an alignment mark. 6A and 6B are explanatory diagrams showing an example of the arrangement of a conventional alignment mark. 7A and 7B are explanatory diagrams showing an example of the arrangement of the underlying patterns. Figure 8 is a state diagram of the correct arrangement of the underlying patterns. [Illustration of Symbols in the Drawings] 2 3, 3a, 3b, 31, 3 la, 3 lb 4, 40 5a v 5b 10 11 12 21 22 23 24 32 Figure 7B shows that the underlined pattern is used to generate a wafer mark and divide it into four parts. Complementary reticle mask mark original pattern opening beam structure light source lens objective lens CCD camera boundary line 87369

Claims (1)

200416820 拾、申請專利範圍： 1· 一種曝光裝置，其特徵為使用具有互補性地分割原圖案 之圖案之曝光用光罩，一面使該曝光用光罩與為被曝光 體之晶圓之相對位置移動，一面進行複數次曝光，於前 述晶圓上為了配置前述圖案之各區域規則地排列而進行 圖案轉印者；且 τ 於前述晶圓上位在配置規則地排列之前述圖案之各區 域2此之間之劃線區域，配置用以進行前述曝光用二 與前述晶圓之定位之對準標記，同時以配置鄰接之前述 圖案之各區域彼此共有前述劃線區域之對準標記。 士申。月專利範圍第1項之曝光裝置，其中前述對準標記 成對之標記。 ’'200416820 Patent application scope: 1. An exposure device characterized by using an exposure mask with a pattern that complementaryly divides the original pattern, while making the relative position of the exposure mask and the wafer to be exposed Move, perform multiple exposures, and perform pattern transfer on the wafer in order to arrange the regions of the pattern regularly; and τ is located on the wafer in the regions of the pattern arranged regularly. 2 The scribe lines between the two are arranged with alignment marks for positioning the second exposure wafer and the wafer, and the regions of the adjacent patterns are arranged to share the alignment marks of the scribe areas with each other. Shi Shen. The exposure device according to the first aspect of the patent, wherein the aforementioned alignment marks are marked in pairs. ’' 4. 5. 6. 申α專利範圍第1項之曝光裝置，其中前述對準標記為 對應使用於對準之三軸光學系統中之1軸標記/ 如申請專利範圍第丨項之曝光裝置，其中前述對準標記為 使用SLA光學系統所進行之晶圓標記。 ^申請專利範圍第i項之曝光裝置，其中前述對準標記係 分開配置於前述圖案區域㈣之端緣附近。 如申請專利範圍第1項之曝光裝置 圖規光罩。 其中前述曝光光罩為 7. 如申請專利範圍第1項之曝光裝置 使用帶電粒子束作為曝光束之光罩 其中前述曝光光罩係 8. 一、寸準方法，其特徵為使用具有互補性地分割原圖 之圖案之曝光用光罩，一使 早 如便a曝先用光罩與為被曝 87369 200416820 體之晶圓之相對位置移動，一面進行複數次曝光，於前 述晶圓上為了配置前述圖案之各區域規則地排列而進行 圖案轉印時，用作前述曝光用光罩與前述晶圓之定位者 ，•且 於$述aB圓上位在配置規則地排列之前述圖案之各區 域彼此間之劃線區域，配置用以進行前述曝光用光罩與 前述晶圓之定位之對準標記，同時以配置鄰接之前述圖 案之各區域彼此共有位於前述劃線區域之對準標記； 分別光學檢出配置於前述劃線區域之對準標記及配置 於刖述曝光用光罩之對準標記，以該檢出結果為基礎， 進行前述曝光用光罩與前述晶圓之相對定位。 9.如申請專利範圍第8g夕料、、隹+ a # 罘M之對準方法，其中前述對準標記為 成對之標記。 ίο.如中請專利範圍第8項之對準方法，其中前述對準標記為 啩應使用於對準之二軸光學系統中之1軸之晶圓標記。 U.如申請專利範圍第8項之對準方法，其中前述定位係使用 SLA光學系統而進行。 12·如申請專利範圍第8項之對準方法，其中前述對準標記係 分開配置於前述各圖案區域相對之端緣附近。 申。月專利&圍第8項之對準方法，其中使晶圓或光罩移 動，以便對準前述各對準標記之重心位置。 14^申請專利範_項之對準方法，其中前述曝光用光罩 為圖規光罩。 15.如中請專利範圍第8項之曝光裝置，其中前述曝光用光罩 87369 200416820 係使用帶電粒子束作為曝光束之光罩。 Μ· -種半導體裝置之製造方&，其特徵為經過微影工序而 製造半導體裝置該冑影工序係使用具有互補性地分 割原圖案之圖案之曝光用光罩，一面使該曝光用光罩與 為被曝光體之晶圓之相對位置移動一面進行複數次曝 光’於前述晶圓上為了配置前述圖案之各區域規則地排 列而進行前述圖案轉印者；且 於則述微影工序進行前述曝光用光罩與前述晶圓之定 位之際’將為了該定位之對準標記配置於前述晶圓上位 在配置規則地排列之前述圖案之各區域彼此之間之割線 區域，同時以鄰接之原圖案區域彼此共有位於前述割線 區域之對準標記。 17.如中請專利範圍第16項之半導體裝置之製造方法，其中 前述對準標記為成對之標記。 1S•如中請專利範圍第17項之半導體裝置之製造方法，皇中 對於前述圖案區域中之一 ’、 之圖案形成日$，對於前述成 對之標記中之一方淮；^千岡奋…L 丁圖案形成，對於前述圖案區域中 之另一方之圖案區域1、$ ^圖案形成4，對於前述成對之標 記中之另一方進行圖案形成。 19.如申請專利範圍第16項 貝之+導體裝置之製造方法，直中 使晶圓或光罩移動，以你 、 以便對準前述各對準標記之重心位 置’進行前述微影工序。 20·如申請專利範圍第16 、，、 干冷肢I置之製造方法，1中 $述曝光用光罩係使用 "使用可電粒子束作為曝光束之光罩。 873694. 5. 6. The exposure device claimed in item 1 of the α patent range, wherein the aforementioned alignment mark is a 1-axis mark corresponding to the three-axis optical system used for alignment The aforementioned alignment mark is a wafer mark using an SLA optical system. ^ The exposure device according to item i of the patent application, wherein the aforementioned alignment mark is separately disposed near the edge of the aforementioned pattern area ㈣. Such as the patent application scope of the exposure device plan plan photomask. Wherein, the aforementioned exposure mask is 7. As the exposure device of the first patent application scope, the charged particle beam is used as the mask of the exposure beam, wherein the aforementioned exposure mask is 8. I. Inch method, which is characterized by the use of complementary The mask used for the exposure of the pattern that divided the original image. As soon as possible, the relative position of the mask and the wafer exposed to 87369 200416820 is moved, and multiple exposures are performed on the same side. When the regions of the pattern are regularly arranged for pattern transfer, they are used as the positioner of the exposure mask and the wafer, and they are located on the circle aB above the regions where the patterns are regularly arranged. The scribe line area is provided with alignment marks for positioning the exposure mask and the wafer, and the adjacent areas of the pattern are arranged to share the alignment marks located in the scribe area with each other. Alignment marks arranged in the scribe area and alignment marks arranged in the exposure mask are described, and the exposure is performed based on the detection result. With the relative positioning of the reticle and wafer. 9. The alignment method according to the 8th range of the patent application, 隹 + a # 罘 M, wherein the aforementioned alignment marks are paired marks. ίο. The alignment method in item 8 of the patent scope, wherein the aforementioned alignment mark is a 1-axis wafer mark that should be used in the aligned 2-axis optical system. U. The alignment method according to item 8 of the patent application, wherein the aforementioned positioning is performed using an SLA optical system. 12. The alignment method according to item 8 of the scope of patent application, wherein the aforementioned alignment marks are separately arranged near the opposite edges of the aforementioned pattern areas. Apply. According to the < Month Patent > Alignment Method No. 8, the wafer or the photomask is moved to align the center of gravity of each of the aforementioned alignment marks. 14 ^ A patent registration method, wherein the aforementioned exposure mask is a plan mask. 15. The exposure device according to item 8 of the patent, wherein the aforementioned exposure mask 87369 200416820 is a mask using a charged particle beam as an exposure beam. -A manufacturer of semiconductor devices & characterized in that the semiconductor device is manufactured through a lithography process, and the photolithography process uses an exposure mask having a pattern that complementaryly divides an original pattern, while exposing the exposure light The relative position of the mask and the wafer to be exposed is moved while performing multiple exposures. 'The person who performs the aforementioned pattern transfer in order to arrange the regions of the aforementioned pattern regularly on the wafer; and then performs the lithography process described above. When the exposure mask and the wafer are positioned, the alignment marks for the positioning are arranged on the wafer in a secant region between the regions in which the patterns arranged regularly are arranged, and the adjacent regions are adjacent to each other. The original pattern areas share the alignment marks in the secant areas. 17. The method for manufacturing a semiconductor device according to claim 16, wherein the aforementioned alignment mark is a pair of marks. 1S • If you request the method for manufacturing a semiconductor device in the 17th area of the patent, the emperor's center is for one of the aforementioned pattern areas, and the pattern formation date is $, and one of the aforementioned paired marks is Fanghuai; ^ Qiangang Fen ... In the L pattern formation, the pattern area 1 of the other pattern area 1 and the pattern formation 4 of the other pattern area are patterned, and the other one of the paired mark is patterned. 19. According to the method of manufacturing the patented item No. 16 PZ + conductor device, move the wafer or reticle straight, and perform the lithography process with you to align the center of gravity position of each alignment mark. 20 · As described in the patent application No. 16, the manufacturing method of dry and cold limbs, the use of the photomask for exposure is used in the photomask for the exposure beam. 87369
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