200415688 (1) . 玖、發明說明 · 相關申請案參考 w 本申請案以2002年12月24所提前日本特許申請案 第2 0 0 2 - 3 7 2 3 8 2號爲本並據以請求優先權，其全部內容附 於內文供參考。 【發明所屬之技術領域】 本發明有關於半導體裝置，詳細言之，有關於具有冗 · 長機能的半導體裝置。 【先前技術】 集成記憶體及邏輯電路於一半導體晶片以形成一系統 的所謂的系統LSI (大型積體電路）業已周知。於系統 L S I中，記憶體電路、邏輯電路等複數機能塊（磁心或巨 集）設於半導體晶片。 又，已知有在記憶體裝置或記憶塊等中使用冗長電路 ® 補救缺陷的方法。亦即，除了記憶體陣列，加設冗長記憶 單元，以此冗長記憶單元替換因製程中所發生缺陷而劣化 的記憶單元。 第7圖是槪略顯示具備賦有冗長機能的記憶塊的習知 半導體裝置的圖面。如第7圖所示，於半導體晶片內的記 憶塊MB內設置冗長記憶單元或冗長記憶單元線路RC。 於半導體裝置的動作測試之際，使用由複數保險絲等 構成的程式配線部P對內部電路進行編程。即使於實際使 -4- (2) (2)200415688 用時輸入不良冗長記憶單元或含有冗長記憶單元的線路的 位址，仍藉此內部電路選擇切換至冗長記憶單元RC。 保險絲具有銅等金屬配線’藉由以雷射經由設於保險 絲的開口切斷此金屬配線，對內部電路進行編程。保險絲 的切斷或非切斷的資訊儲存於鎖存器PL。藉由於冗長機 能動作之際，參考此資訊，自不良記憶單元切換存取至冗 長記憶單元。 程式配線部P的保險絲及鎖存器P L固定於記憶塊 MB內，如第7圖所示，其沿記憶塊MB周圍設置。因 此，連接記憶塊MB與邏輯電路等機能電路塊B的配線 L 1須通過保險絲上。不過由於保險絲中的金屬配線自開 口露出，故配線L 1通過保險絲上構成發生短路的原因。 【發明內容】 本發明第1觀點的半導體裝置是具有複數機能塊，前 述各機能塊配設於半導體基板上的半導體裝置，具備：前 述機能塊之一的記憶塊，前述記憶塊具備記錄資訊的複數 記憶單元以及替換至少一個前述記憶單元，並替代該記憶 單元，記錄資訊的冗長記憶單元；前述機能塊之一，藉配 線與則述5己憶塊連接的機能電路塊，前述機能塊之一的程 式配線塊具備以在前述半導體基板上不與前述配線重疊的 方式配設於前述半導體基板上，並且，形成信號路徑俾不 良的前述記憶單元替換成-前述冗長記憶單元的程式配線 部；以及自前述程式配線塊上朝前述記憶塊上伸延，且將 -5- (3) (3)200415688 有關前述程式配線部的前述程式的程式資訊轉送至前述記 憶塊的資料轉送部。 本發明第2觀點的半導體裝置是具有複數機能塊，前 述各機能塊配設於半導體基板上的半導體裝置，具備：分 別爲前述機能塊之一的第1至第η ( η爲2以上整數）記 憶塊；前述第1至第η記憶塊具備記錄資訊之複數記憶單 元以及替換至少一個前述記憶單元，並替代該記憶單元， 記錄資訊的冗長記憶單元；前述機能塊之一，藉配線與前 述弟1至弟η記憶塊連接的機能電路塊；前述機能塊之一 的程式配線塊，前述程式配線塊具備以在前述半導體基板 上不與前述配線重疊的方式配設於前述半導體基板上，並 且’編成信號路徑的程式俾不良的前述記憶單元替換成前 述冗長記憶單元的程式配線部；以及自前述程式配線塊上 朝前述記憶塊上伸延，且將有關前述程式配線部的前述程 式的程式資訊轉送至前述第1記憶塊的資料轉送部；以及 分別自前述第i程式配線塊上朝前述第i + 1記憶塊上伸 延’並分別將前述第i記憶塊的前述程式的程式資訊轉送 至前述第i + 1記憶塊的資料轉送部。 本發明第3觀點的半導體裝置具備配設於第1半導體 基板上的記憶塊，前述記憶塊具備記錄資訊的複數記憶單 元以及替換至少一個前述記憶單元，並替代該記憶單元， 記錄資訊的冗長記憶單元；配設於第2半導體基板上的程 式配線塊，前述程式配線塊具備形成信號路徑俾不良的前 述記憶單元替換成前述冗長記憶單元的程式配線部；以及 -6 - (4) (4)200415688 自前述程式配線塊上朝前述記憶塊上伸延，且將有關前述 程式配線部的前述程式的程式資訊轉送至前述記憶塊的資 料轉送部。 【實施方式】 胃0月之詳細說明 以下參考圖面就本發明實施形態加以說明。且於以下 說明中，以相同符號標示具有大致相同機能及構造的構成 元件’僅在必要情形下進行重複說明。 <胃1實施形態） 第1圖是槪略顯示本發明第1實施形態的半導體裝置 的圖面。此半導體裝置具有記憶塊MB、程式配線塊PB 以及邏輯電路等的機能電路塊B。此各個機能塊各具有特 定機能，以未形成機能塊的區域圍繞周圍的方式設在半導 體晶片（半導體基板）C上。機能電路塊B藉設於半導體 晶片C上的配線L1與記憶塊MB連接。 於記憶塊MB內設置記憶單元陣列MC。記憶單元陣 列MC由圖略複數記憶單元構成。又於記憶塊MB內設置 冗長記憶單元或冗長記憶單元線路RC (以下單稱冗長記 憶單元）。冗長記憶單元RC用來替換動作測試結果判定 不良的記憶單元或記憶單元線路。典型地，不良的記憶單 元以位元線或字線單位替換成冗長記憶單元RC。 記憶塊MB配置成具有根據來自外部的控制信號，將 (5) (5)200415688 資訊寫入預定位址的記憶單元，又從記憶單元讀出資訊的 機能。典型地，具有例如X解碼器XD、Y解碼器YD、 輸出入控制電路I/O等。例如使用DRAM (動態隨機存取 記憶體）、SRAM (靜態隨機存取記憶體）等。 程式配線塊PB以在半導體晶片C上不與配線L 1重 疊的方式設在半導體晶片C上。程式配線塊PB與記憶塊 Μ藉資料轉送部DT連接。資料轉送部DT自程式配線塊 ΡΒ上伸延至記憶塊MB上，具有將程式配線塊ΡΒ所保存 的資訊轉送至記憶塊MB的機能。資料轉送部DT例如由 串聯連接的複數移位暫存器SR1〜4及配線L2構成。 於程式配線塊PB內設置程式配線部P。程式配線部 P編成信號路徑的的內部電路的程式，俾不良記憶單元替 換成冗長記憶單元。亦即，程式配線部P編成程式，俾在 所輸入位址的記憶單元不良情形下，存取替換此記憶單元 的冗長記憶單元RC。具體方法存在有周知的種種方法。 典型地，程式配線部P可由複數保險絲或快閃記憶體等非 揮發性記憶體構成。 於程式配線塊PB內例如設置鎖存器PL 1。鎖存器 PL 1於冗長機能發揮之際，輸入並保持程式配線部P的程 式資訊。程式資訊對應於在使用保險絲作爲程式配線部P 情形下，顯示保險絲的切斷或非切斷的資訊。於此情形 下，鎖存器PL 1例如相對於各保險絲設置，保持所對應保 險絲的資訊。 保持於鎖存器PL 1的程式資訊依序儲存於設在程式配 -8- (6) (6)200415688 線塊PB內的移位暫存器SR1。儲存於移位暫存器SR1的 - 程式資訊對應供至資料轉送部DT的移位暫存器SR1〜4的 ， 時鐘脈波，依序轉送至資料轉送部DT內。如此’將程式 配線塊PB內的程式資訊轉送至記憶塊MB ^於冗長機能 發揮之際，藉由參考儲存於記憶塊MB內的移位暫存器 SR4的程式資訊’自不良記憶單元將存取切換至冗長記憶 單元RC。 根據第1實施形態’於獨立於記憶塊MB外設置的程 式配線塊PB內設置用在冗長機能發揮之際的程式配，線部 P，程式配線塊PB設置成在半導體晶片C的平面上不與 連接記憶塊MB與其他機能電路塊B的配線L1重疊。並 且， 程式配線塊PB的程式資訊藉資料轉送部DT轉送至記憶 塊MB。藉由作成此種構造，可避免配線L 1通過程式配 線部P上方。因此。在使用保險絲作爲程式配線部P情形 下，可排除配線L1及保險絲短路的可能性。 馨 又由於獨立設置程式配線塊PB，故可提高於半導體 晶片C上配置機能塊之際的自由度。 (第2實施形態） 第2圖是槪略顯示本發明第2實施形態的半導體裝置 的圖面。且爲了簡化說明，於顯示第2實施形態以後的實 施形態的圖面中省略記憶塊MB內的記憶單元陣列MC、 冗長記憶單元RC、X解碼器XD、Y解碼器YD、輸出入 -9- (7) (7)200415688 控制電路I/O。 - 如第2圖所示，第2實施形態的半導體裝置設置與記 - 憶塊MB內的資料轉送部DT連接的資料保持部DS。資料 保持部DS具有保持資料轉送部DT內的資料的機能。典 型地，資料保持部DS由鎖存器PL2〜4構成。鎖存器 VL2〜4相對於移位暫存器SR2〜4設置，保持對應的移位暫 存器SR2〜4內的資料。 資料轉送部DT具有設於記憶塊MB內的選擇控制部 φ MUX。典型地，使用多工器作爲選擇控制部MUX。移位 暫存器SR1的輸出信號供至選擇控制部之一輸入端。來 自設於半導體晶片外部的測試器T的輸出信號經由資料路 徑DP2供至另一輸入端。選擇控制部MUX的輸出信號供 至移位暫存器S R2。資料轉送部D T內的最終段的移位暫 存器SR4藉資料路徑DP 1連接於半導體裝置外部的測試 器T。 其次，於以下就上述構造的半導體裝置的動作加以說 馨 明。如第1實施形態所載，於冗長機能發揮之際，程式配 線部P的程式資訊依序轉送至資料轉送部內，儲存於移位 暫存器SR4。 另一方面，於半導體裝置的動作測試之際，有欲進行 儲存於移位暫存器SR4的資料是否正確反映程式配線部P 的程式資訊等的判定的情形發生。於此情形下，時鐘脈波 供至各移位暫存器SR1〜4，藉由程式資訊依序移位，將程 式資訊供至測試器T。並且，於測試器T中進行程式資訊 -10- (8) (8)200415688 的確認。由於如此供給程式資訊至測試器T ’故先輸入的 程式資訊會喪失。因此，於動作測試之前’藉資料保持部 D S保持程式資訊。 又有實際上於程式配線部ρ中並未編成程式，欲進行 冗長機能是否正確發揮的測試的情形發生。因此’藉選擇 控制部MUX將對移位暫存器S R2的輸入切換成來自測試 器Τ的信號，程式配線部Ρ的仿真程式資訊自測試器Τ 輸入移位暫存器S R2。並且，藉測試器Τ進行冗長機能的 動作判定。 根據第2實施形態，半導體裝置具有與記憶塊MB的 資料轉送部D T連接的資料保持部D S。在半導體裝置的 動作測試之前，程式配線部P的程式資訊藉資料保持部 DS保持。因此，即使自資料轉送部DT的最終段的移位 暫存器SR4至測試器T讀出程式資訊，仍可避免程式配 線部P的程式資訊喪失。 又，半導體裝置具備設於記憶塊MB內的選擇控制部 MUX。程式配線塊PB的移位暫存器SR1的輸出信號以及 測試器T的輸出信號供至選擇控制部MUX。因此，藉由 白 測試器T供給程式配線部P的仿真程式資訊，可實際上於 程式配線部P中未編成程式，進行冗長機能的動作確認。 (第3實施形態） 第3圖是槪略顯示本發明第3實施形態的半導體裝置 -11 - (9) (9)200415688 的圖面。於第2實施形態中’在記憶塊MB內設置選擇控 制部MUX，將來自程式配線塊PB的移位暫存器SR1及測 試器T的輸出信號供至選擇控制部MUX。相對於此，於 第3實施形態中’除了來自鎖存器P L 1的信號外’還將來 自測試器T的信號直接供至程式配線塊PB的移位暫存 SR1。 根據第3實施形態’獲得與第2實施形態相同的效 果。 (第4實施形態） 第4圖是槪略顯示本發明第4實施形態的半導體裝置 的圖面。第4實施形態於半導體晶片C上設置複數記憶 塊。 以下就例如設置3個記憶塊的例子加以說明。 如第 4圖所示，於半導體晶片 C上設置記憶塊 MB1、MB2、MB3。記憶塊MB1具有與第2實施形態中的 記憶塊MB相同的構造。記憶塊MB 1〜MB3藉配線L1與 機能電路塊B連接。 程式配線塊PB與記憶塊MB 1〜MB3如以下串聯連 接。程式配線塊PB的程式資訊例如與第2實施形態相同 的資料轉送部DT 1轉送至記憶塊MB 1。亦即，程式配線 塊PB的移位暫存器SR1的輸出信號以及測試器T的輸出 信號供至記憶塊MB 1的選擇控制部MUX。選擇控制部 MUX的輸出信號供至資料轉送部DT1的移位暫存器 (10) (10)200415688 SR2。 記憶塊Μ B 1〜Μ B 2的移位暫存器S R4的資訊藉與第1 實施形態相同的構造的資料轉送部D T 2分別轉送至記憶 塊ΜΒ2〜ΜΒ3。記憶塊ΜΒ3的最終段的移位暫存器SR4 的輸出信號供至測試器Τ。 其次，就上述構造的半導體裝置的效果說明如下。在 使用第4貫施形態的半導體裝置處理例如具有r 〇 β色素 的影像信號情形下，可分配R色素、G色素、Β色素於記 憶塊MB 1〜MB 3。藉此，可有效率地進行邏輯電路等機能 電路塊及記憶單元的存取。 又可例如使用MB 1〜MB 3於別的用途。於此情形下， 可例如使用一記憶塊於影像資料的緩衝用，使用另一個於 與C P U (中央處理單兀）間的資料供給收受（工作R A Μ (隨機存取記憶體））。藉由如此分配各記憶塊不同的機 能，可提高半導體裝置（系統LS 1 )的動作效率。 根據第4實施形態，除了第2實施形態的構造外，尙 具有串聯連接的複數記憶塊MB 1〜MB3。藉由如此構成， 除了與第2實施形態相同的效果外，尙獲得於記憶塊 MB 1〜MB3具有不同的機能，可提高半導體裝置的動作效 率的效果。 (第5實施形態） 第5圖是槪略顯示本發明第5實施形態的半導體裝置 的圖面。於第1至第4實施形態中，記憶塊MB及程式配 •13- (11) (11)200415688 線塊PB設在一半導體晶片上。相對於此，於第5實施形 態中，記憶塊Μ B及程式配線塊P B設在各自獨立的半導 體晶片上。 如第5圖所示，半導體裝置具有半導體晶片C1及半 導體晶片C2。於半導體晶片C1上設置與第2實施形態的 構造相同的記憶塊MB及機能電路塊Β，這些塊藉配線l 1 連接。記憶塊MB藉資料路徑DP 1及資料路徑DP2與測 試器連接。 於半導體晶片C2上設置與第1實施形態的構造相同 的程式配線塊PB。程式配線塊PB的程式資訊藉與第2實 施形態的構造相同的資料轉送部DT轉送至記憶塊MB。 根據第5實施形態，分別形成程式配線塊PB及記憶 塊於個別半導體晶片C1、C2上。因此，獲得與第1、第 2實施形態相同的效果，以及以下所示效果。 藉由半導體技術的發展，進而達到亦包含機能塊的半 導體裝置的微型化。在使用保險絲作爲程式配線部情形 下，除了記憶塊的保險絲外，各部份均進而微型化，另一 方面，相對於這些部份的微型化，保險絲的微型化有困 難。因此，若記憶塊全體及其他部份設在一半導體晶片 上，記憶塊全體難以微型化。因此，藉由將保險絲以外部 份所構成的記憶塊MB及程式配線塊p β設在別的半導體 晶片上，可不受保險絲製造技術限制，將記憶塊MB微型 化。又藉由使用記憶塊MB作爲泛用品，亦可降低半導體 裝置的製造成本。 -14- (12) (12)200415688 又’容易適用非揮發性記憶體作爲程式配線部P。亦 - 即，記憶體陣列及其控制電路、記憶塊的主要部份、快閃 . 記憶体等非揮發性記憶體的製程不同。因此，藉由適用第 5實施形態，可可不受這些主要部份與非揮發性記憶體間 的製程不同限制，製造個別半導體晶片C i、C2。因此， 適用第5實施形態，於製造成本及微型化方面有效。 (第6實施形態） φ 第6圖是槪略顯示本發明第6實施形態的半導體裝置 的圖面。如第6圖所示，於半導體晶片C上設置晶載內建 機能測試（內建測試：B I S T )電路 B I S T。B I S T電路 BIS T與記憶塊MB的輸出入控制電路I/O以及測試器τ 連接。BIST電路BIST預先儲存記憶塊MB的動作測試所 需的程式，BIST電路BIST根據此程式自動進行記憶塊 MB的動作測試。BIST電路BIST將測試結果輸出至測試 器T。 參 於程式配線塊P中，程式配線部P例如由快閃記憶体 等非揮發性記憶或e (電子）保險絲等電子可程式的程式 元件構成。e保險絲是可藉電子信號寫入與一般保險絲相 同的切斷資訊的元件。 程式配線塊PB除了第1實施形態所示構造外，尙具 有程式配線部控制部（控制電路部）PC。程式配線部控 制部PC響應來自測試器T的信號，於程式配線塊P中編 成程式。 -15- (13) (13)200415688 根據第6實施形態，獲得與第1實施形態相同的效 果。又，第6實施形態於個別半導體晶片C上形成自行測 試機能電路，同時，程式配線部p由電子可程式的程式元 件構成。因此，響應來自測試器T的信號，藉程式配線部 控制部P C，於程式配線塊P中電子式編成程式。並因 此，可有效率地進行半導體裝置的動作測試以及不良記憶 單元與冗長單元間的互換，亦提高便利性。 熟於此技藝人仕當一目瞭然其他優點及變更。因此， 就較廣層面而言，本發明不限於本文所示及所說明的特定 內容及代表性實施例。因此，在不悖離後附申請專利範圍 及其均等範圍所界定的一般性發明槪念的精神及範疇下， 可作種種變更。 【圖式簡單說明】 第1圖是槪略顯示本發明第i實施形態的半導體裝置 的圖面。 第2圖是槪略顯示本發明第2實施形態的半導體裝置 的圖面。 第3圖是槪略顯示本發明第3實施形態的半導體裝置 的圖面。 第4圖是槪略顯示本發明第4實施形態的半導體裝置 的圖面。 第5圖是槪略顯示本發明第5實施形態的半導體裝置 的圖面。 -16- (14) (14)200415688 第6圖是槪略顯示本發明第6實施形態的半導體裝置 的圖面。 - 第7圖是槪略顯示習知半導體裝置的圖面。 【符號說明】 B 機能電路塊 BIST BIST 電路 c、Cl、C2 半導體晶片 _ DPI > DP2 資料路徑 DS 資料保持部 DT 資料轉送部 I/O 輸出入控制電路 LI 、 L2 配線 Μ B、Μ B 1〜Μ B 2 記憶塊 MC 記憶單元 MUX 選擇控制部 _ Ρ 程式配線部 ΡΒ 程式配線塊 PC 程式配線部控制部 PL1〜PL4 鎖存器 RC 冗長記憶單元 SR1〜4 移位暫存器 XD X解碼器 YD Y解碼器 -17-200415688 (1). 发明 Description of the invention · Related application references w This application is based on the Japanese Patent Application No. 2 0 0 2-3 7 2 3 8 2 which was filed in advance on December 24, 2002 and is based on priority Rights, the entire contents of which are attached for reference. [Technical Field to which the Invention belongs] The present invention relates to a semiconductor device, and in particular, to a semiconductor device having redundant and long-lasting functions. [Prior Art] The so-called system LSI (Large-Integrated Circuit) that integrates a memory and a logic circuit on a semiconductor chip to form a system has been known. In the system L S I, a plurality of functional blocks (magnetic core or macro) such as a memory circuit and a logic circuit are provided on a semiconductor chip. It is also known to use a lengthy circuit ® in a memory device or a memory block to remedy a defect. That is, in addition to the memory array, a verbose memory unit is added to replace the memory unit that has been deteriorated due to a defect occurring in the process. Fig. 7 is a diagram schematically showing a conventional semiconductor device having a memory block provided with a redundant function. As shown in Fig. 7, a redundant memory cell or a redundant memory cell line RC is provided in the memory block MB in the semiconductor wafer. For the operation test of the semiconductor device, the internal circuit is programmed using a program wiring section P composed of a plurality of fuses and the like. Even when the actual use of -4- (2) (2) 200415688 is used to input the address of a bad redundant memory unit or a circuit containing a redundant memory unit, the internal circuit is still selected to switch to the redundant memory unit RC. The fuse has a metal wiring such as copper, and the internal circuit is programmed by cutting the metal wiring with a laser through an opening provided in the fuse. Information on whether the fuse is cut or not is stored in the latch PL. When operating due to the verbose function, refer to this information to switch from the bad memory unit to the verbose memory unit. The fuse and latch PL of the program wiring section P are fixed in the memory block MB. As shown in FIG. 7, they are arranged around the memory block MB. Therefore, the wiring L 1 connecting the memory block MB and the functional circuit block B such as a logic circuit must be passed through a fuse. However, since the metal wiring in the fuse is exposed from the opening, the wiring L 1 may cause a short circuit through the fuse. SUMMARY OF THE INVENTION A semiconductor device according to a first aspect of the present invention is a semiconductor device having a plurality of functional blocks. Each of the functional blocks is a semiconductor device disposed on a semiconductor substrate. The semiconductor device includes a memory block that is one of the functional blocks. A plurality of memory units and a redundant memory unit that replaces at least one of the foregoing memory units and replaces the memory unit and records information; one of the foregoing functional blocks, a functional circuit block connected to the memory module by wiring, and one of the foregoing functional blocks The program wiring block includes a program wiring unit that is arranged on the semiconductor substrate so as not to overlap the wiring on the semiconductor substrate, and replaces the memory unit that forms a bad signal path with the redundant memory unit; Extending from the aforementioned program wiring block toward the aforementioned memory block, and transferring the program information of the aforementioned program from (-5-) (3) (3) 200415688 to the aforementioned program wiring section to the data transfer section of the aforementioned memory block. A semiconductor device according to a second aspect of the present invention is a semiconductor device having a plurality of functional blocks. Each of the functional blocks is arranged on a semiconductor substrate. Memory block; the aforementioned first to n memory blocks are provided with a plurality of memory units for recording information, and a tedious memory unit for replacing information by replacing at least one of the aforementioned memory units, and replacing the memory unit; one of the aforementioned functional blocks, by wiring and the aforementioned brother A functional circuit block connected to the memory block 1 to n; a program wiring block that is one of the functional blocks; the program wiring block is provided on the semiconductor substrate so as not to overlap the wiring on the semiconductor substrate; and The program memory that has been programmed into a signal path is replaced by the program memory unit of the redundant memory unit; and the program wiring unit extends from the program memory block to the memory block and transfers program information about the program of the program wiring unit To the data transfer unit of the aforementioned first memory block; and from the aforementioned i-th program wiring block, respectively It is extended to the i + 1th memory block, and program information of the program of the ith memory block is transferred to the data transfer section of the i + 1th memory block. A semiconductor device according to a third aspect of the present invention includes a memory block disposed on a first semiconductor substrate. The memory block includes a plurality of memory cells for recording information, and a long memory that replaces at least one of the memory cells and records the information. A unit; a program wiring block arranged on a second semiconductor substrate, the program wiring block having a program wiring unit in which the memory unit forming the signal path 俾 is replaced by the redundant memory unit; and -6-(4) (4) 200415688 extends from the aforementioned program wiring block toward the aforementioned memory block, and transfers program information about the aforementioned program of the aforementioned program wiring section to the data transfer section of the aforementioned memory block. [Embodiment] Detailed explanation of the stomach month The following describes the embodiment of the present invention with reference to the drawings. In the following description, the constituent elements with substantially the same function and structure are denoted by the same symbols, and repeated descriptions will be made only when necessary. < Embodiment of stomach 1 > Fig. 1 is a diagram schematically showing a semiconductor device according to a first embodiment of the present invention. This semiconductor device includes a functional circuit block B such as a memory block MB, a program wiring block PB, and a logic circuit. Each of the function blocks has a specific function, and is provided on a semiconductor wafer (semiconductor substrate) C so that the area where the function block is not formed surrounds the periphery. The functional circuit block B is connected to the memory block MB via a wiring L1 provided on the semiconductor wafer C. A memory cell array MC is set in the memory block MB. The memory cell array MC is composed of plural memory cells. A redundant memory unit or a redundant memory unit circuit RC is also provided in the memory block MB (hereinafter referred to as a redundant memory unit). The redundant memory unit RC is used to replace a memory unit or a memory unit circuit that is judged to be defective by an action test result. Typically, a bad memory cell is replaced with a verbose memory cell RC in bit line or word line units. The memory block MB is configured to have a function of writing (5) (5) 200415688 information to a predetermined address memory unit and reading information from the memory unit according to a control signal from the outside. Typically, it has, for example, an X decoder XD, a Y decoder YD, and an input / output control circuit I / O. For example, use DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), etc. The pattern wiring block PB is provided on the semiconductor wafer C so as not to overlap the wiring L 1 on the semiconductor wafer C. The program wiring block PB is connected to the memory block M by the data transfer unit DT. The data transfer unit DT is extended from the program wiring block PB to the memory block MB, and has a function of transferring the information stored in the program wiring block PB to the memory block MB. The data transfer unit DT includes, for example, a plurality of shift registers SR1 to SR and wirings L2 connected in series. A pattern wiring section P is provided in the pattern wiring block PB. The program wiring section P compiles the internal circuit program of the signal path, and replaces the bad memory unit with the redundant memory unit. That is, the program wiring section P compiles a program, and accesses the long memory unit RC that replaces the memory unit when the memory unit of the input address is defective. There are various known methods for specific methods. Typically, the program wiring section P may be composed of a non-volatile memory such as a plurality of fuses or a flash memory. For example, a latch PL 1 is provided in the program wiring block PB. The latch PL 1 is used to input and hold the program information of the program wiring section P when the redundant function is performed. The program information corresponds to the information showing whether the fuse is cut or not when a fuse is used as the program wiring section P. In this case, the latch PL1 is provided for each fuse, for example, and holds the corresponding fuse information. The program information held in the latch PL 1 is sequentially stored in the shift register SR1 set in the program register -8- (6) (6) 200415688 line block PB. -The program information stored in the shift register SR1 corresponds to the clock registers of the shift registers SR1 ~ 4 supplied to the data transfer unit DT, and are sequentially transferred to the data transfer unit DT. In this way, 'transfer the program information in the program wiring block PB to the memory block MB ^ When the redundant function is exerted, by referring to the program information of the shift register SR4 stored in the memory block MB', the self-defective memory unit will store Take the switch to the lengthy memory unit RC. According to the first embodiment, the pattern wiring block PB is provided inside the pattern wiring block PB provided independently of the memory block MB, and the wire portion P and the pattern wiring block PB are arranged on the plane of the semiconductor chip C so as not to be used. It overlaps with the wiring L1 connecting the memory block MB and the other functional circuit block B. In addition, the program information of the program wiring block PB is transferred to the memory block MB by the data transfer unit DT. With this structure, it is possible to prevent the wiring L 1 from passing over the pattern wiring portion P. therefore. When a fuse is used as the pattern wiring section P, the possibility of short circuit between the wiring L1 and the fuse can be ruled out. Since the program wiring block PB is independently provided, the degree of freedom in arranging the function block on the semiconductor wafer C can be increased. (Second Embodiment) Fig. 2 is a diagram schematically showing a semiconductor device according to a second embodiment of the present invention. In order to simplify the description, the memory cell array MC, the redundant memory cell RC, the X decoder XD, the Y decoder YD, and the input / output in the memory block MB are omitted from the drawings showing the second and subsequent embodiments. (7) (7) 200415688 Control circuit I / O. -As shown in Fig. 2, the semiconductor device of the second embodiment is provided with a data holding unit DS connected to the data transfer unit DT in the memory block MB. The data holding unit DS has a function of holding data in the data transfer unit DT. Typically, the data holding unit DS is composed of latches PL2 to PL4. The latches VL2 to 4 are set relative to the shift registers SR2 to 4 and hold the data in the corresponding shift registers SR2 to 4. The data transfer unit DT includes a selection control unit φ MUX provided in the memory block MB. Typically, a multiplexer is used as the selection control section MUX. An output signal of the shift register SR1 is supplied to an input terminal of the selection control section. The output signal from the tester T provided outside the semiconductor wafer is supplied to the other input terminal via the data path DP2. The output signal of the selection control section MUX is supplied to the shift register S R2. The final stage shift register SR4 in the data transfer unit D T is connected to the tester T outside the semiconductor device via the data path DP 1. Next, the operation of the semiconductor device having the above-mentioned structure will be explained in the following. As described in the first embodiment, the program information of the program distribution section P is sequentially transferred to the data transfer section and stored in the shift register SR4 when the redundant function is exerted. On the other hand, during the operation test of the semiconductor device, there is a case where it is determined whether or not the data stored in the shift register SR4 correctly reflects the program information of the program wiring section P and the like. In this case, the clock pulse is supplied to each shift register SR1 ~ 4, and the program information is sequentially shifted to supply the program information to the tester T. And confirm the program information -10- (8) (8) 200415688 in the tester T. Since the program information is supplied to the tester T 'in this way, the program information entered first will be lost. Therefore, before the action test, the program information is retained by the data holding section DS. In fact, there is a case where a program is not programmed in the program wiring section ρ, and a test is performed to check whether the redundant function is correctly performed. Therefore, by the selection control section MUX, the input to the shift register S R2 is switched to a signal from the tester T, and the simulation program information of the program wiring section P is input from the tester T into the shift register S R2. Then, the tester T is used to perform a verbose function judgment. According to the second embodiment, the semiconductor device includes a data holding unit DS connected to a data transfer unit D T of the memory block MB. Prior to the operation test of the semiconductor device, the program information of the program wiring section P is held by the data holding section DS. Therefore, even if the program information is read from the shift register SR4 of the final stage of the data transfer unit DT to the tester T, the program information of the program wiring unit P can be avoided. The semiconductor device includes a selection control unit MUX provided in the memory block MB. The output signal of the shift register SR1 of the program wiring block PB and the output signal of the tester T are supplied to the selection control section MUX. Therefore, by providing the simulation program information of the program wiring section P with the white tester T, the program wiring section P is not actually programmed, and the redundant function operation can be confirmed. (Third Embodiment) Fig. 3 is a drawing schematically showing a semiconductor device according to a third embodiment of the present invention-(9) (9) 200415688. In the second embodiment, a selection control unit MUX is provided in the memory block MB, and the output signals from the shift register SR1 and the tester T of the program wiring block PB are supplied to the selection control unit MUX. On the other hand, in the third embodiment, 'in addition to the signal from the latch PL 1', the signal from the tester T is directly supplied to the shift register SR1 of the program wiring block PB. According to the third embodiment, the same effect as that of the second embodiment is obtained. (Fourth Embodiment) Fig. 4 is a diagram schematically showing a semiconductor device according to a fourth embodiment of the present invention. In the fourth embodiment, a plurality of memory blocks are provided on the semiconductor wafer C. An example of setting three memory blocks will be described below. As shown in FIG. 4, memory blocks MB1, MB2, and MB3 are provided on the semiconductor wafer C. The memory block MB1 has the same structure as the memory block MB in the second embodiment. The memory blocks MB 1 to MB3 are connected to the functional circuit block B through the wiring L1. The program wiring block PB and the memory blocks MB 1 to MB3 are connected in series as follows. The program information of the program wiring block PB is transferred to the memory block MB1, for example, by the data transfer unit DT1 of the second embodiment. That is, the output signal of the shift register SR1 of the program wiring block PB and the output signal of the tester T are supplied to the selection control section MUX of the memory block MB1. The output signal of the selection control unit MUX is supplied to the shift register of the data transfer unit DT1 (10) (10) 200415688 SR2. The information in the shift registers S R4 of the memory blocks MB 1 to MB 2 is transferred to the memory blocks MB2 to MB3 by the data transfer unit D T 2 having the same structure as the first embodiment. The output signal of the shift register SR4 in the final stage of the memory block MB3 is supplied to the tester T. Next, effects of the semiconductor device having the above-described structure will be described below. When the semiconductor device of the fourth embodiment is used to process an image signal having, for example, a r 0 β pigment, an R pigment, a G pigment, and a B pigment can be assigned to the memory blocks MB 1 to MB 3. This allows efficient access to functional circuit blocks such as logic circuits and memory cells. MB 1 to MB 3 can also be used for other applications. In this case, for example, one memory block can be used for buffering the image data, and the other is used for data receiving and receiving between the CPU and the CPU (Central Processing Unit) (job RAM). By allocating different functions to each memory block in this way, the operating efficiency of the semiconductor device (system LS 1) can be improved. According to the fourth embodiment, in addition to the structure of the second embodiment, 尙 has a plurality of memory blocks MB 1 to MB 3 connected in series. With this configuration, the effects obtained from the memory blocks MB 1 to MB 3 are different from those of the second embodiment, and the effect of improving the operating efficiency of the semiconductor device is obtained. (Fifth Embodiment) Fig. 5 is a diagram schematically showing a semiconductor device according to a fifth embodiment of the present invention. In the first to fourth embodiments, the memory block MB and programming are provided. 13- (11) (11) 200415688 The wire block PB is provided on a semiconductor wafer. On the other hand, in the fifth embodiment, the memory block MB and the program wiring block P B are provided on separate semiconductor chips. As shown in Fig. 5, the semiconductor device includes a semiconductor wafer C1 and a semiconductor wafer C2. The semiconductor wafer C1 is provided with a memory block MB and a functional circuit block B having the same structure as those of the second embodiment, and these blocks are connected by wiring l 1. Memory block MB is connected to tester via data path DP1 and data path DP2. A pattern wiring block PB having the same structure as that of the first embodiment is provided on the semiconductor wafer C2. The program information of the program wiring block PB is transferred to the memory block MB by the data transfer unit DT having the same structure as that of the second embodiment. According to the fifth embodiment, the program wiring block PB and the memory block are formed on the individual semiconductor wafers C1 and C2, respectively. Therefore, the same effects as those of the first and second embodiments and the effects shown below are obtained. With the development of semiconductor technology, miniaturization of semiconductor devices that also include functional blocks has been achieved. In the case of using a fuse as the program wiring section, in addition to the fuse of the memory block, each part is further miniaturized. On the other hand, compared with the miniaturization of these parts, it is difficult to miniaturize the fuse. Therefore, if the entire memory block and other parts are provided on a semiconductor wafer, it is difficult to miniaturize the entire memory block. Therefore, by arranging a memory block MB and a program wiring block p β formed by an external part of the fuse on another semiconductor chip, the memory block MB can be miniaturized without being limited by the fuse manufacturing technology. In addition, by using the memory block MB as a universal product, the manufacturing cost of the semiconductor device can also be reduced. -14- (12) (12) 200415688 It is also easy to apply non-volatile memory as the program wiring section P. That is, the process of the non-volatile memory such as the memory array and its control circuit, the main part of the memory block, and the flash memory is different. Therefore, by applying the fifth embodiment, it is possible to manufacture individual semiconductor wafers C i and C2 without being restricted by the different processes between these main parts and the non-volatile memory. Therefore, applying the fifth embodiment is effective in terms of manufacturing cost and miniaturization. (Sixth Embodiment) Fig. 6 is a diagram showing a semiconductor device according to a sixth embodiment of the present invention. As shown in FIG. 6, a chip built-in function test (built-in test: B I S T) circuit B I S T is set on the semiconductor wafer C. B I S T circuit BIS T is connected to the input / output control circuit I / O of the memory block MB and the tester τ. The BIST circuit BIST stores a program required for the operation test of the memory block MB in advance, and the BIST circuit BIST automatically performs the operation test of the memory block MB according to this program. The BIST circuit BIST outputs the test result to the tester T. In the program wiring block P, the program wiring section P is composed of, for example, a non-volatile memory such as a flash memory or an electronic programmable program element such as an e (electronic) fuse. An e-fuse is a component that can write the same cutoff information as a general fuse by an electronic signal. In addition to the structure shown in the first embodiment, the pattern wiring block PB includes a pattern wiring section control section (control circuit section) PC. In response to the signal from the tester T, the program wiring section control section PC compiles a program in the program wiring block P. -15- (13) (13) 200415688 According to the sixth embodiment, the same effect as that of the first embodiment can be obtained. In the sixth embodiment, a self-testing function circuit is formed on an individual semiconductor wafer C, and at the same time, the program wiring section p is composed of an electronically programmable program element. Therefore, in response to a signal from the tester T, the program wiring section control section PC is used to program the program electronically in the program wiring block P. Therefore, the operation test of the semiconductor device and the interchange between the defective memory unit and the redundant unit can be performed efficiently, and convenience is also improved. Those skilled in this art should know other advantages and changes at a glance. Therefore, in a broader aspect, the invention is not limited to the specific content and representative embodiments shown and described herein. Therefore, various changes can be made without departing from the spirit and scope of the general invention concept as defined by the scope of the attached patent and its equivalent scope. [Brief Description of the Drawings] Fig. 1 is a diagram schematically showing a semiconductor device according to an i-th embodiment of the present invention. Fig. 2 is a diagram schematically showing a semiconductor device according to a second embodiment of the present invention. Fig. 3 is a diagram schematically showing a semiconductor device according to a third embodiment of the present invention. Fig. 4 is a diagram schematically showing a semiconductor device according to a fourth embodiment of the present invention. Fig. 5 is a diagram schematically showing a semiconductor device according to a fifth embodiment of the present invention. -16- (14) (14) 200415688 Fig. 6 is a diagram schematically showing a semiconductor device according to a sixth embodiment of the present invention. -FIG. 7 is a diagram showing a conventional semiconductor device. [Symbol description] B functional circuit block BIST BIST circuit c, Cl, C2 semiconductor chip_ DPI & DP2 data path DS data holding part DT data transfer part I / O input / output control circuit LI, L2 wiring Μ B, Μ B 1 ~ M B 2 Memory block MC Memory unit MUX selection control unit _ P Program wiring unit PB Program wiring block PC Program wiring unit control PL1 ~ PL4 Latch RC Redundant memory unit SR1 ~ 4 Shift register XD X decoder YD Y decoder-17-