JP2005267794A - Nonvolatile semiconductor memory and semiconductor system lsi provided with same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a core constitution of a semiconductor memory having a nonvolatile memory cell manufactured by a logic circuit manufacturing process. <P>SOLUTION: After write data is set to a shift register 4 in series from a serial output data terminal SDIN, the data are written into (n) pieces bit cells 2 including nonvolatile memory cells as data Q <n:0>. In reading data, a control circuit 5 receives the pulse signal RD of one shot and reads (n) bits data RDEN <n:0> from the bit cells 2. These data are latched by a latch circuit 3, and output to the outside via a parallel output data terminal DOUT <n:0>. Read data LATX <n:0> of the latch circuit 3 is transferred to the shift register 4. Checking of read operation is performed by reading data transferred to the shift register 4 from a serial output data terminal SDOUT. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a nonvolatile semiconductor memory device, and more particularly to a configuration of a nonvolatile semiconductor memory device having a nonvolatile memory manufactured by a logic circuit manufacturing process, and a configuration of a semiconductor system LSI including such a nonvolatile semiconductor memory device. .

  In recent years, non-volatile memories have been used in various semiconductor systems. If this non-volatile memory and logic LSI can be mixedly mounted on the same semiconductor substrate, manufacturing process costs can be reduced and the size can be reduced. Therefore, there is an increasing demand for mounting a non-volatile memory in the leading-edge logic circuit manufacturing process.

As a means for solving the above-described problems, a nonvolatile memory that can be easily manufactured by a logic circuit manufacturing process has been conventionally proposed (for example, see Patent Document 1). In addition, a redundancy technique in a semiconductor system LSI including the nonvolatile memory has been proposed (see, for example, Non-Patent Document 1).
JP-A-6-53521 M. Yamaoka et al. "A System LSI Memory Redundancy Technique Using an ie-Flash (Inverse-Gate-Electrode Flash) Programming Circuit" IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 37. NO. 5, MAY 2002 pp. 599-604

  However, regarding the nonvolatile memory that can be manufactured by the above-described logic circuit manufacturing process, the configuration of the memory cell and the device structure are disclosed in the above-mentioned patent documents and the like, but the core of the semiconductor memory device having the nonvolatile memory cell is disclosed. Conventionally, there is no disclosure regarding the configuration of the semiconductor system LSI and the configuration of a semiconductor system LSI in which such a nonvolatile semiconductor memory device is applied to an application.

  The present invention has been made from such a situation. In particular, in a semiconductor device having an analog trimming function and a memory redundancy function, a fuse element is frequently used to realize the function. Focusing on the fact that the formation of fuses has become more difficult with miniaturization, and the development of alternative technologies is urgently needed, and a semiconductor memory device having the nonvolatile memory cell as such an alternative technology of fuses Will be used.

  That is, an object of the present invention is to provide a configuration of a semiconductor memory device having a non-volatile memory that can be manufactured by a logic circuit manufacturing process, and a semiconductor including such a non-volatile semiconductor memory device. It is to propose a system LSI.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to a first aspect of the present invention includes a serial input data terminal, a serial output data terminal, a parallel output data terminal of n (n is an integer of 2 or more) bits, n nonvolatile memory cells, writing means for writing write data from the outside to the n nonvolatile memory cells via the serial input data terminal, and read data from the n nonvolatile memory cells It is characterized by comprising reading means for reading out via a serial output data terminal and a parallel output data terminal, and control means for controlling the writing means and reading means.

  According to a second aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the control unit receives a one-shot pulse signal, and reads from the nonvolatile memory cell based on the pulse signal. The reading means is controlled to read data to the outside.

  According to a third aspect of the present invention, in the nonvolatile semiconductor memory device according to the first or second aspect, the reading unit includes n latch circuits, and the n-th non-volatile memory cells receive data during a data read period. The read data is latched in the n latch circuits, and the latched n read data are always output to the outside through parallel output data terminals.

  According to a fourth aspect of the present invention, in the nonvolatile semiconductor memory device according to the third aspect, the read means includes n read data latched in the n latch circuits during the data read period. A second output signal that is in a Hi-Z state is output during a period other than the data reading period.

  According to a fifth aspect of the present invention, in the nonvolatile semiconductor memory device according to the fourth aspect, the reading unit includes a shift register including n flip-flop circuits to which a common clock signal is input. The n flip-flop circuits receive the second output signal from the n latch circuits and the output signal from the preceding flip-flop circuit, and each flip-flop circuit receives the output signal during the data read period. The second output signal is latched, and the second output signal latched during the data read period other than the data read period is output to the flip-flop circuit of the next stage based on the clock signal, and the flip-flop of the final stage is output. The second output signal is output from the circuit via the serial output data terminal.

  According to a sixth aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the writing unit includes a shift register including n flip-flop circuits to which a common clock signal is input. Of the n flip-flop circuits, the first flip-flop circuit receives write data via the serial input data terminal, and each of the flip-flop circuits excluding the first flip-flop circuit is a previous flip-flop based on the clock signal. A write signal from the n-type flip-flop circuit is received, and a write signal from the n number of flip-flop circuits is input to the n number of nonvolatile memory cells.

  According to a seventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the sixth aspect, the shift register included in the writing unit is also used as the shift register included in the nonvolatile semiconductor memory device according to the fifth aspect. It is characterized by that.

  According to an eighth aspect of the present invention, the nonvolatile semiconductor memory device according to the first aspect further comprises test mode setting means for receiving a test mode serial input data and a test mode enable signal and generating a plurality of types of test mode signals. It is characterized by that.

  According to a ninth aspect of the present invention, in the nonvolatile semiconductor memory device according to the eighth aspect, the test mode setting means includes a shift register in which a plurality of flip-flop circuits to which a common clock signal is input are connected in series. And the same number of logic operation circuits as the number of the flip-flop circuits, the test mode serial input data is sequentially set in each of the flip-flop circuits, and each of the logic operation circuits has the corresponding flip-flop. The output signal of the logic circuit and the test mode enable signal are inputted, and the combination of the outputs of the logic operation circuits becomes the test mode signal.

  According to a tenth aspect of the present invention, in the nonvolatile semiconductor memory device according to the ninth aspect, a decode circuit for decoding a test mode signal from the test mode setting means is provided.

  According to an eleventh aspect of the present invention, in the nonvolatile semiconductor memory device according to the first aspect, the n non-volatile memory cells are formed by a logic circuit manufacturing process.

  According to a twelfth aspect of the present invention, in the nonvolatile semiconductor memory device according to the eleventh aspect, two types of logic circuit manufacturing processes in which the n non-volatile memory cells form two types of gate oxide films. Among them, it is formed by a logic circuit manufacturing process for forming a thick gate oxide film.

  According to a thirteenth aspect of the present invention, in the nonvolatile semiconductor memory device according to the eleventh aspect, all the transistors constituting the n non-volatile memory cells, the write unit, the read unit, and the control unit are The gate oxide film is formed with the same film thickness.

  A semiconductor system LSI according to a fourteenth aspect includes the nonvolatile semiconductor memory device according to the first aspect and a functional block having a parallel input data terminal of a plurality of bits, and a parallel output of the nonvolatile semiconductor memory device The data terminal is connected to a parallel input data terminal of the functional block.

  According to a fifteenth aspect of the present invention, in the semiconductor system LSI according to the fourteenth aspect, a plurality of the nonvolatile semiconductor memory devices are provided, and the first nonvolatile semiconductor memory among the plurality of nonvolatile semiconductor memory devices. Write data is input to the device from the outside via the serial input data terminal, and the nonvolatile semiconductor memory device except the first stage has a serial output data terminal of the nonvolatile semiconductor memory device of the preceding stage. The nonvolatile semiconductor memory device in the last stage is connected to the serial output data terminal, and read data is externally output from its serial output data terminal.

  A semiconductor system LSI according to a sixteenth aspect of the invention includes the nonvolatile semiconductor memory device according to the eighth aspect, and a functional block having a plurality of bits of parallel input data terminals, and the parallel output of the nonvolatile semiconductor memory device The data terminal is connected to a parallel input data terminal of the functional block.

  According to a seventeenth aspect of the present invention, in the semiconductor system LSI according to the sixteenth aspect, the nonvolatile semiconductor memory device has the test mode setting as write data input to the serial input data terminal as serial input data for test mode. It is input to the means.

  According to an eighteenth aspect of the present invention, in the semiconductor system LSI according to the sixteenth aspect, a plurality of the nonvolatile semiconductor memory devices are provided, and the first nonvolatile semiconductor memory device among the plurality of nonvolatile semiconductor memory devices. Write data is input to the device from the outside via the serial input data terminal, and the nonvolatile semiconductor memory device except the first stage has a serial output data terminal of the nonvolatile semiconductor memory device of the preceding stage. The nonvolatile semiconductor memory device in the final stage is connected to the serial output data terminal, and the read data is externally output from the serial output data terminal, and the test mode setting means of the plurality of nonvolatile semiconductor memory devices includes: Each of the test mode serial input data and the test mode enable signal is directly input. And butterflies.

  According to a nineteenth aspect of the present invention, in the semiconductor system LSI according to any one of the fourteenth to eighteenth aspects, the functional block has a redundant function.

  According to a twentieth aspect of the present invention, in the semiconductor system LSI according to any one of the fourteenth to eighteenth aspects, the functional block has an analog trimming function.

  According to a twenty-first aspect of the present invention, in the semiconductor system LSI according to any one of the fourteenth to nineteenth aspects, the function block is initialized during a power-on sequence of the semiconductor system LSI. A one-shot reset pulse signal is input to the non-volatile semiconductor memory device, and based on the reset pulse signal, the reading means reads from the n non-volatile memory cells. The readout data is read out to the outside.

  According to a twenty-second aspect of the present invention, in the semiconductor system LSI according to the fifteenth or eighteenth aspect, the number of the plurality of nonvolatile semiconductor memory devices is determined according to the total number of parallel input data terminals of the functional block. It is characterized by that.

  According to a twenty-third aspect of the present invention, in the semiconductor system LSI according to the twenty-second aspect, the plurality of nonvolatile semiconductor memory devices all have the same number of parallel input data terminals and the same configuration. It is characterized by being.

  As described above, in the invention described in claims 1 to 23, the read data from the n non-volatile memory cells is read out to the outside via the parallel output data terminal by the read means, and has a function having a redundancy function, for example. Since it is input to the block, n non-volatile memory cells can be used as an alternative technique to the conventional fuse element. Moreover, writing data to n nonvolatile memory cells and checking the written data do not require a very high operating speed. However, write data is stored in n nonvolatile memories via one serial input data terminal. On the other hand, the read data from the n non-volatile memory cells is read out to the outside through one serial output data terminal by the read means while being written into the cell. Therefore, the n-bit parallel input terminal and parallel output terminal for these write data and read data are not necessary, and the number of necessary terminals can be effectively reduced.

  In addition, since a read operation is performed with a one-shot pulse signal, current consumption during reading is reduced, and stress is not applied to the nonvolatile memory cells except during reading, so stress on the nonvolatile memory cells is suppressed. Thus, the reliability is improved.

  In addition, since write data is set and read data is checked using a shift register, simultaneous writing to the nonvolatile memory cells can be performed simultaneously, and there is no need for a decoding signal terminal or a decoding circuit, reducing the number of terminals. The size can be reduced.

  In addition, by providing the latch circuit and the shift register, it is possible to check the read data without causing data destruction.

  As described above, in a system LSI having a functional block having a redundancy function, an analog trimming function, and the like, a nonvolatile semiconductor memory device that can be replaced as a fuse element can be provided in the logic circuit manufacturing process, thereby reducing the manufacturing process cost. be able to. Further, since a trimming process and a trimmer device are not required, the test cost is reduced. Further, conventionally, there has been a layout restriction of the wiring layer above the fuse element, but this restriction is also eliminated since it is replaced by a nonvolatile semiconductor memory device.

  As described above, according to the invention described in claims 1 to 23, as a non-volatile semiconductor memory device having non-volatile memory cells that can be manufactured by a logic circuit manufacturing process, write data and read data together with parallel output data terminals. Since the serial input data terminal and the serial output data terminal are provided for checking, the number of terminals can be reduced.

  In addition, such a nonvolatile semiconductor memory device is useful as an alternative technique for a fuse element, for example, in a semiconductor system LSI including a functional block having a redundancy function, an analog trimming function, and the like.

  The nonvolatile semiconductor memory device according to each embodiment of the present invention will be described below with reference to FIGS.

(Embodiment 1)
FIG. 1 shows a block diagram of a nonvolatile semiconductor memory device according to Embodiment 1 of the present invention.

  In FIG. 1, reference numeral 1 denotes an entire nonvolatile semiconductor memory device, 2 a bit cell including a nonvolatile memory cell, 3 a latch circuit, 4 a shift register, 5 a control circuit (control means), and 6 a bit cell 2. A control signal for controlling, 7 is a control signal for controlling the latch circuit 3, and 8 is a control signal for controlling the shift register 4. SCLK is a clock signal, WT is a write operation designation signal, RD is a read operation designation signal (one-shot pulse signal), SDIN is a serial input data signal input to one serial input data terminal, and SDOUT is one serial. A serial output data signal output from the output data terminal, DOUT <n: 0>, is a parallel output data signal output from the (n + 1) -bit parallel output data terminal.

  The bit cell 2 outputs the read data RDEN <n: 0> based on the control signal 6, and the latch circuit (read means) 3 latches the read data RDEN <n: 0> based on the control signal 7, Two output signals LATX <n: 0> and DOUT <n: 0> are output, and the shift register (reading means) 4 outputs the serial input data signal SDIN and the output signal LATX <n: 0> from the latch circuit 3. As an input, write data Q <n: 0> to the bit cell 2 including the nonvolatile memory cell is output, and a serial output data signal SDOUT is output based on the control signal 8, and the control circuit 5 receives the clock signal SCLK and the write Control signals 6, 7, and 8 are output with the operation designation signal WT and the read operation designation signal RD as inputs.

  FIG. 2 shows a circuit example of an arbitrary n-th bit of the bit cell 2 shown in FIG. In the figure, 11 is a PMOS transistor, 12 and 14 are NMOS transistors, and 13 is a non-volatile memory cell which is composed of PMOS transistors and NMOS transistors and has a common floating gate. 15 is an OR circuit that functions as an amplifier, and 16 is an AND circuit. Further, Vdd is a power source, Vss is ground, SL is a source line set to a predetermined voltage level according to the operation mode (write operation / read operation) of the nonvolatile semiconductor memory device, IRDX, IE, ICG, and IWT are shown in FIG. 1 is a control signal generated in accordance with the operation mode in the control circuit 5, RDEN <n> is an output signal of the bit cell 2, and Q <n> is an output signal of the shift register 4 in FIG. 1.

  In the bit cell 2 of FIG. 2, between the power supply Vdd and the source line SL, a PMOS transistor 11 having a signal IRDX as a gate input, an NMOS transistor 12 having a signal IE as a gate input, and a signal ICG as a control gate. Nonvolatile memory cells 13 are arranged. An NMOS transistor 14 is disposed between the drain N1 of the PMOS transistor 11 and the ground Vss, and an AND circuit that receives the signal IWT and the output signal Q <n> of the shift register 4 as inputs to the gate of the NMOS transistor 14. 16 output signals WD <n> are input, and the signal IRDX and the signal N1 (the drain potential of the NMOS transistor 12) are input to the gate of the OR circuit 15 to output read data RDEN <n> from the bit cell 2. It is the structure to do.

  In the above configuration, in the bit cell configuration shown in FIG. 5 of Non-Patent Document 1, a two-stage inverter circuit functioning as an amplifier is configured by an OR circuit 15, and an AND circuit 16 is added. The difference is that the OR circuit 15 is for avoiding a through current generated in the inverter circuit due to the gate node N1 floating in a period other than the read operation period (the signal IRDX is “1”). The AND circuit 16 is added to make it easy to understand the circuit operation when the write data to the nonvolatile memory cell 13 is “0” and “1”.

  FIG. 3 shows an example of a circuit configuration of arbitrary 2 bits (the nth bit and the (n−1) th bit) in the block excluding the control circuit 5 in the nonvolatile semiconductor memory device shown in FIG.

  In the figure, reference numerals 21, 22, 26 and 27 denote CMOS switch circuits composed of PMOS transistors and NMOS transistors, and reference numerals 23, 24, 25, 28, 29, 30 and 31 denote inverter circuits. In the latch circuit 3, read data RDEN from the bit cell 2 is input to the CMOS switch circuit 21, an output thereof is input to the inverter circuit 23, and an output of the inverter circuit 23 is input to the CMOS switch circuit 22, and an inverter Input to the circuits 24 and 25. The CMOS switch circuit 22 outputs the latched read data LATX, and the inverter circuit 25 outputs the output signal DOUT to the outside. Here, since the output of the inverter circuit 24 is connected to the gate of the inverter circuit 23 to form a latch circuit, the driving capability thereof is set lower than that of the inverter circuit 23. The signal IRD is input to the gates of the NMOS transistors of the CMOS switch circuits 21 and 22, and the inverted signal IRDX of the signal IRD is input to the gates of the PMOS transistors.

  In FIG. 3, the shift register 4 has n + 1 flip-flop circuits 4 <n> to 4 (0) having the same configuration. The internal configuration of one flip-flop circuit 4 <n> will be described as an example. The output Q of the preceding flip-flop circuit is input to the CMOS switch circuit 26, and the output is input to the inverter circuit 29. The output of the inverter circuit 29 is input to the CMOS switch circuit 27 and the inverter circuit 28, the output of the CMOS switch circuit 27 is input to the inverter circuit 31, the output of the inverter circuit 31 is input to the inverter circuit 30, and the bit cell 2 And input to the flip-flop circuit in the next stage. Here, since the output of the inverter circuits 28 and 30 is connected to the gates of the inverter circuits 29 and 30 to form a latch circuit, the drive capability is set lower than the drive capability of the inverter circuits 29 and 30. . The clock signal ISCK generated by the control circuit 5 is input to both gates of the PMOS transistor of the CMOS switch circuit 26 and the NMOS transistor of the CMOS switch circuit 27, and the NMOS transistor of the CMOS switch circuit 26 and the PMOS of the CMOS switch circuit 27. An inverted signal ISCKX of the clock signal ISCK is input to both gates of the transistor.

  A write operation and a read operation in the nonvolatile semiconductor memory device configured as described above will be described below with reference to timing charts.

  FIG. 4 shows, as an example, a timing chart in the case where data “01010101” is written in each bit cell <7: 0> in a semiconductor memory device having 8-bit nonvolatile memory cells.

  In the figure, SDIN is serial input data, SCLK is a clock signal, ISCK is an internal clock signal generated internally by the control circuit 5 based on the clock signal SCLK, and Q <n> is an (n + 1) bit in the shift register 4. The output data signal of the eye, WT is a write operation designation signal, IWT is an internal write operation designation signal generated internally based on the write operation designation signal WT, IE is a control signal for the NMOS transistor 12, and ICG is a nonvolatile memory cell 13 The control gate signal WD <7: 0> is an output of the AND circuit 16 having the internal write operation designation signal IWT and the output signal (write data) Q <7: 0> of the shift register 4 as inputs. , Input to the NMOS transistor 14.

  An internal clock signal ISCK is generated based on the clock signal SCLK, and serial input data SDIN is input to the internal clock signal ISCK at a timing that can secure a setup time and a hold time. At this time, it is assumed that the outputs Q <7: 0> of the flip-flop circuits are all in the “0” state. In the shift register (writing means) 4, first, the serial input data SDIN (“1”) of the first bit is latched by the internal clock signal ISCK, and the output Q <7> of the first flip-flop circuit starts from “0”. “1”. Next, when the second bit serial input data SDIN (“0”) is latched by the internal clock signal ISCK, the output signal Q <7> of the shift register is changed from “1” to “0” and the second stage The output Q <6> of the flip-flop circuit is changed from “0” to “1” by shifting “1” of the output signal Q <7> by the internal clock signal ISCK. Similarly, the serial input data SDIN is latched by the clock signal SCLK, and “01010101” is latched in the shift register 4 after the eight clock signals SCLK, and the setting of the write data is completed.

  Thereafter, by setting the write operation designation signal WT to “1”, the internal write operation designation signal IWT and the other control signals IE and ICG become “1”, and the gate signal WD <of the NMOS transistor 14 of the 8-bit bit cell 2 < 7: 0> becomes “01010101”. Here, in the bit cell 2 in which “1” data is written, that is, the gate signal WD of the NMOS transistor 14 is “1”, the NMOS transistors 12 and 14 and the nonvolatile memory cell 13 are turned on, and the source line SL, the ground VSS, By trapping hot electrons generated by applying a high voltage during this period and flowing current in the floating gate of the nonvolatile memory cell 13, the threshold value of the NMOS transistor constituting the nonvolatile memory cell 13 is increased.

  On the other hand, in the bit cell 2 in which “0” data is written, that is, the gate signal WD of the NMOS transistor 14 is “0”, the NMOS transistor 12 and the nonvolatile memory cell 13 are turned on, but the NMOS transistor 14 is turned off. Therefore, even if a high voltage is applied between the source line SL and the ground VSS, no current flows, so that the threshold value of the NMOS transistor constituting the nonvolatile memory cell 13 does not change. In this manner, data “0” and “1” are written by changing the threshold value of the nonvolatile memory cell 13.

  FIG. 5 shows a timing chart for reading the write data “01010101” shown in FIG.

  In the figure, RD is a one-shot pulse read operation designation signal, IRD is an internal read operation designation signal generated internally based on the read operation designation signal RD, IRDX is an inverted signal of the internal read operation designation signal IRD, IE Is a control signal of the NMOS transistor 12, ICG is a control gate signal of the nonvolatile memory cell 13, RDEN <7: 0> is an output signal of the bit cell 2, and LATX <7: 0> is a second output from the latch circuit 3. The output signal DOUT <7: 0> is an output signal from the latch circuit 3 and is 8-bit parallel output data output externally. Further, SCLK is a clock signal, ISCK is an internal clock signal generated internally based on the clock signal SCLK, and SDOUT is serial output data output based on the clock signal from the first stage flip-flop circuit constituting the shift register 4. .

  In FIG. 5, when the read operation designation signal RD is changed from “0” to “1”, the internal read operation designation signal IRD is changed from “0” to “1”. Similarly, the control signal IE and the control gate signal ICG are also “0”. From “1” to “1”, and the inverted internal read operation designating signal IRDX is changed from “1” to “0”. That is, in FIG. 2, the PMOS transistor 11 and the NMOS transistor 12 arranged between the power supply Vdd and the source line SL are turned on.

  Here, in the memory cell 2 in which “0” data is written, since electrons are not trapped in the floating gate, the threshold value of the NMOS transistor constituting the nonvolatile memory cell 13 is low, and the power supply Vdd and the source line SL are low. A current flows between them. Since the inverted internal read operation designating signal IRDX is “1” except during the read cycle period, “1” is input to one input of the OR circuit 15, so that the output of the OR circuit 15 is in the “1” state. In the cycle of reading “0” data, when the node signal N1 becomes lower than the threshold value of the OR circuit 15, the read data RDEN changes from “1” to “0”. On the other hand, in the memory cell 2 in which “1” data is written, electrons are trapped in the floating gate and the threshold value of the NMOS transistor is high, so that no current flows between the power supply Vdd and the source line SL, and the OR circuit. The read data RDEN which is the output of 15 remains “1”.

  The outputs LATX <7: 0> of the latch circuit 3 are in the Hi-Z state because the CMOS switch circuits 21 and 22 are in the off state except for the read cycle period. Since 22 is turned on, it receives RDEN <7: 0> state (“10101010”) and becomes “01010101”. The serial output data DOUT <7: 0> is in a state where either “0” or “1” is latched because the CMOS switch circuits 21 and 22 are in the off state except during the read cycle period. During the read cycle period, the CMOS switch circuits 21 and 22 are turned on, so that the read data RDEN <7: 0> (“01010101”) is received and becomes “01010101”. At this time, the first bit of data “1” is output as the serial output data SDOUT. Here, when the read operation designating signal RD is changed from “1” to “0” and the read cycle is completed, the inverted internal read operation designating signal IRDX is changed from “0” to “1” and read from the OR circuit 15. The signals RDEN are all “1”, and the parallel output data DOUT always outputs the latched data during the read cycle period.

  As shown in the timing chart of FIG. 5, the read data is checked by inputting the clock signal SCLK from the outside and reading the data latched in the flip-flop circuit constituting the shift register 4 from the serial output data terminal SDOUT. It can be done easily.

  As described above, the latch circuit 3 that latches the read data from the nonvolatile memory cell 13 is provided, and the data read from the memory cell 2 and the data latch are performed by the read operation designation signal RD that is a one-shot pulse signal. Thus, the stress applied to the nonvolatile memory cell 13 is limited only at the time of reading, so that the stress of the nonvolatile memory cell 13 can be suppressed and a highly reliable nonvolatile semiconductor memory device can be realized.

  Also, by providing the shift register 4 composed of a flip-flop circuit and setting the write data serially from the serial input data terminal, the write data can be written simultaneously at the same time. Also for data reading, by providing a shift register 4 composed of a flip-flop circuit and one serial output data terminal, it is possible to easily check data read from the nonvolatile memory cell 13 without increasing the number of output terminals. It can be carried out. Further, since the shift register for the write data and the shift register for the read data are shared by the shift register 4, the circuit can be simplified and the chip size can be reduced accordingly.

  Further, since the output from the latch circuit 3 to the shift register 4 (latch data LATX <7: 0>) is in the Hi-Z state except for the read cycle period, the data write operation of the shift register 4 in the data write period. There is no hindrance. In addition, it is not necessary to separately provide a switching circuit for permitting / prohibiting the input of the latch data LATX <7: 0> from the latch circuit 3 to the shift register 4, and the configuration can be simplified.

  The circuit configurations of the bit cell 2, the latch circuit 3, and the shift register 4 are not limited to the illustrated circuit configurations as long as their functions match the contents described in the claims.

(Embodiment 2)
FIG. 6 is a block diagram of a semiconductor system LSI including the nonvolatile semiconductor memory device shown in FIG.

  In the figure, reference numeral 1 denotes the nonvolatile semiconductor memory device shown in FIG. 1, and 41 (m), 41 (m−1), and 41 (0) are functional blocks having (m + 1) redundant functions and analog trimming functions. It is. The nonvolatile semiconductor memory device 1 receives the clock signal SCLK, the write operation designation signal WT, and the serial input data SDIN. The nonvolatile semiconductor memory device 1 receives the serial output data SDOUT and the (n + 1) -bit parallel output data signal. DOUT <n: 0> is output. A read operation designation signal terminal of the nonvolatile semiconductor memory device receives a one-shot reset pulse signal RST that initializes the internal circuit of the functional block during the power-on reset sequence period of the semiconductor system LSI.

  Here, the nonvolatile semiconductor memory device has a 64-bit parallel output data terminal, and the functional blocks 41 (0), 41 (m−1), and 41 (m) are 8 bits, 16 bits, and 8 bits, respectively. Consider a functional block having a bit parallel input data terminal, in which the parallel input data bits of all the functional blocks are 64 bits. Each of the parallel output data DOUT <63: 0> of the nonvolatile semiconductor memory device 1 is connected to the parallel input data input terminal of the corresponding functional block.

  FIG. 7 shows a timing chart of the semiconductor system LSI including the nonvolatile semiconductor memory device 1. In the figure, Vdd is a power supply, RST is a one-shot reset pulse signal for initializing a functional block during a power-on reset period of the semiconductor system, and DOUT <63: 0> is the nonvolatile semiconductor memory. This is parallel output data output from the device 1.

  As shown in the figure, when the power supply Vdd rises from “0” to “1” during the power-up sequence and then a one-shot reset pulse signal RST is input, data is read from the nonvolatile memory cell 13. Then, the parallel output data DOUT <63: 0> is determined. Here, since the one-shot reset pulse signal RST is input with a sufficient timing margin with respect to the normal use timing of the semiconductor system LSI, the parallel output data DOUT <in the functional block having the redundancy function and the analog trimming function The internal control based on 63: 0> is completed with a sufficient timing margin with respect to the normal use timing of the semiconductor system LSI.

  As described above, in various functional blocks that have conventionally realized a redundancy function and an analog trimming function using a fuse element, a detection node of the fuse element is provided as a parallel input data terminal, and a nonvolatile memory having a parallel output data terminal is provided. Since the fuse element can be replaced by combining with the conductive semiconductor memory device 1, the above-described problems of the fuse element can be solved. Further, from the viewpoint of layout, since the fuse element is not required, the degree of freedom in designing the wiring layer is greatly improved, and the nonvolatile semiconductor memory device 1 is provided on the side of the region such as the power supply wiring like the fuse element. Therefore, it is possible to embed in a region such as a power supply wiring, so that a large area effect can be obtained.

(Embodiment 3)
FIG. 8 shows a third embodiment of a semiconductor system LSI including the nonvolatile semiconductor memory device shown in FIG.

  In the figure, 51 (l), 51 (l-1) and 51 (0) are functional blocks having (l + 1) redundant functions and analog trimming functions, and the total number of parallel input data terminals is as follows. 128 bits. Reference numerals 1A and 1B are two nonvolatile semiconductor memory devices having the same configuration, and the parallel output data terminals have a parallel output data terminal corresponding to the total number of parallel input data terminals (128 bits) of the functional block. The total number is 128 bits, that is, each has 64 bits of parallel output data terminals.

  A clock signal SCLK and a write designation signal WT are connected to the two nonvolatile semiconductor memory devices 1A and 1B, respectively, and a serial input data signal SDIN is input to a serial data input terminal of the nonvolatile semiconductor memory device 1B. The serial data output terminal of the semiconductor memory device 1B is connected to the serial data output terminal of the nonvolatile semiconductor memory device 1A, and the serial output data signal SDOUT is output from the serial data output terminal of the nonvolatile semiconductor memory device 1A. The devices 1A and 1B output 64-bit parallel output data DOUTA <63: 0> and DOUTB <63: 0>, respectively. These parallel output data are respectively output to the parallel input data terminals of the corresponding functional blocks. Connected. In the nonvolatile semiconductor memory devices 1A and 1B, each read operation designation signal terminal has a one-shot reset pulse signal RST that initializes an internal circuit of each functional block during a power-on reset period of the semiconductor system. It is a configuration that is input in common with the block.

  In the semiconductor system LSI, when the number of parallel data input bits required in each functional block is further increased (for example, in the case of 64 → 128 bits), as shown in FIG. 6, one nonvolatile semiconductor memory device 1 Can be accommodated by increasing the number of bits, but the number of functional blocks and the number of bits required in the functional blocks are various in the semiconductor system LSI to be applied. For this reason, in the case of dealing with an increase in the number of bits, it is necessary to prepare the nonvolatile semiconductor memory device 1 having a different number of bits for each semiconductor system LSI, which causes a problem that the design man-hour increases. .

  Therefore, as shown in the present embodiment, when applied to a semiconductor system LSI having a different number of bits, the nonvolatile semiconductor memory devices 1A and 1B having a fixed number of bits are designed in advance, and the nonvolatile semiconductor memory device By adopting a method of arranging a plurality of the steps, an increase in design man-hours can be suppressed. In this case, since the number of bits is fixed, it is assumed that unused bits are generated, but the correspondence between the number of used bits of the nonvolatile semiconductor memory device and the number of parallel input bits of each functional block is clarified. If applied, there is no problem. Further, the number of bits to be fixed may be determined by sufficiently investigating and grasping the trend of the application to be applied.

(Embodiment 4)
FIG. 9 is a block diagram of a nonvolatile semiconductor memory device having a test mode function. In this embodiment, a nonvolatile semiconductor memory device having four types of test modes will be described.

  In FIG. 9, 9 is a test mode setting shift register, and TR <3: 0> is an output of the test mode setting shift register 9, that is, a test mode signal. TEST is a test mode enable signal, TDIN is a test mode setting serial data input signal, and ITCK is a clock signal for controlling the operation of the test mode shift register. In addition, since what is attached | subjected with the code | symbol same as FIG. 1 is the same block, the description is abbreviate | omitted. The test mode setting shift register 9 receives a test mode enable signal TEST, a test mode setting serial data input signal TDIN, and a test mode setting clock signal ITCK, and receives a 4-bit test mode signal TR <3: 0>. Is output.

  FIG. 10 shows an internal circuit of the test mode setting shift register (test mode setting means) 9 shown in FIG.

  In the figure, reference numeral 71 denotes four flip-flop circuits, which constitute a shift register. Reference numeral 72 denotes a logical operation circuit composed of an AND circuit. The four flip-flop circuits 71 are arranged in series to form the shift register 9. The four flip-flop circuits 71 receive the test mode clock signal ITCK in common, and the first-stage flip-flop circuit 71 performs the test. The mode setting serial data input signal TDIN is input, and the output is input to the flip-flop circuit 71 in the next stage. The AND circuits 72 are provided in a one-to-one correspondence with the flip-flop circuits 61, and the test mode enable signal TEST is commonly input to the gates thereof, and the corresponding flip-flop circuits 71 are connected to the other gates. The output is input.

  FIG. 11 is a timing chart for setting the test mode. In this figure, SDIN is serial input data, TDIN is test mode serial input data, RD is a read operation designation signal, WT is a write operation designation signal, SCLK is a clock signal, ITCK is a clock signal of a test mode setting shift register, TQ <3: 0> is an output of the flip-flop circuit 71 constituting the shift register 9. TEST is a test mode enable signal, and TR <3: 0> is an output of the AND circuit 72.

  When both the read operation designation signal RD and the write operation designation signal WT are “1”, the read operation and the write operation are not performed by the control, and the clock signal ITCK of the test mode shift register 71 is enabled based on the clock signal SCLK. Thus, the test mode serial data TDIN is input at a timing having a setup time and hold time margin with respect to the clock signal ITCK. When “0010” is time-divisionally input as test mode setting serial data TDIN, the output signal TQ <3> of the flip-flop circuit 71 is changed from “0” to “1” in the third clock signal ITCK. The signal Q <3> (“1”) latched in the flip-flop circuit 71 in the first clock signal ITCK is transferred, and the output signal TQ <2> from the flip-flop circuit 71 in the next stage is “0”. The data setting to the shift register 9 is completed from “1” to “1”. Thereafter, by changing the test mode enable signal TEST from “0” to “1”, only the test mode control signal TR <2> is changed from “0” to “1”. The test mode is enabled.

  Thus, by setting the data from the serial data input terminal to the shift register 9 composed of a plurality of flip-flop circuits 71, the test mode can be easily set. In this embodiment, four types of test modes are set by using four flip-flop circuits 71. However, two flip-flop circuits and a decode circuit (not shown) that receives the outputs of the flip-flop circuits as inputs. It is also possible to set the test mode using

  The test mode setting means is not limited to the illustrated circuit configuration as long as it matches the contents described in each claim.

(Embodiment 5)
12 and 13 show an embodiment of a semiconductor system LSI using a nonvolatile semiconductor memory device having a test mode function.

  In the figure, 10 is the nonvolatile semiconductor memory device shown in FIG. 1, TEST is a test mode enable signal, and TDIN is a test mode setting serial data input signal. In FIG. 12, the same reference numerals as those in FIG. 1 are signals and blocks having the same function, and a description thereof will be omitted.

  When only one nonvolatile semiconductor memory device is provided, the test mode setting serial data input signal TDIN is directly applied to the test mode serial input data terminal of the nonvolatile semiconductor memory device 10 as shown in FIG. The serial input data SDIN may be input as test mode serial data as shown in FIG.

(Embodiment 6)
FIG. 14 shows an embodiment of a semiconductor system LSI including a plurality of nonvolatile semiconductor memory devices having a test mode function.

  In the figure, reference numerals 10A and 10B denote two non-volatile semiconductor memory devices having the same configuration, and have 64-bit parallel output data terminals. 14 is obtained by replacing the two nonvolatile semiconductor memory devices 1A and 1B with nonvolatile semiconductor memory devices 10A and 10B having a test mode function in FIG. To do.

  As shown in the fifth embodiment, when one nonvolatile semiconductor memory device is arranged, the test mode can be set even if the serial input data terminal and the test mode serial input data terminal of the nonvolatile semiconductor memory device are connected. However, when a plurality of nonvolatile semiconductor memory devices are arranged, if the serial input data terminals and the test mode serial input data terminals of the nonvolatile semiconductor memory devices 10A and 10B are connected, the chain The serial input chain for write data and the serial input data for test mode are mixed in the serial data chain connected in the same manner. For this reason, there arises a problem that the setting of the test mode in each of the nonvolatile semiconductor memory devices 10A and 10B becomes complicated.

  Therefore, when a plurality of nonvolatile semiconductor memory devices 10A and 10B are arranged as in the present embodiment, test mode serial input data TDIN is directly input to each nonvolatile semiconductor memory device 10A and 10B. In the plurality of nonvolatile semiconductor memory devices 10A and 10B, the test mode can be set simultaneously, and the test mode setting can be prevented from becoming complicated.

  Here, most of the blocks in the nonvolatile semiconductor memory device are formed by thin MOS transistors having the same gate oxide film as the transistors constituting the logic circuit. Since a high voltage is applied to some of the included transistors, the gate oxide film has the same thickness as that of the IO cell manufactured in the logic circuit manufacturing process from the viewpoint of reliability (the gate oxide of the transistors constituting the logic circuit). The film thickness is greater than the film thickness).

  By the way, depending on the application, the required speed and power consumption are different, and therefore, there are various types of processes in the logic circuit manufacturing process in which the gate film thickness and threshold value of the transistor are different in order to meet the needs. When the nonvolatile semiconductor memory device is applied to various applications as described above, the device definition and model parameters are different, so that redesign is required every time the logic circuit manufacturing process changes. As shown in the embodiment of the present invention, when a nonvolatile semiconductor memory device is applied as a substitute for a functional block fuse element having a redundancy function or an analog trimming function, high-speed operation is not required. If the transistor is formed with the same thickness as the IO cell, redesign is not required even if the logic circuit manufacturing process changes. However, if all the MOS transistors are designed in this way, there is a concern that the layout area will increase due to the influence of the design rules. Therefore, considering the specifications required for the application and the number of installed bits, etc. Therefore, it is necessary to appropriately determine which gate film thickness to design.

  As described above, according to the present invention, a nonvolatile semiconductor memory device having nonvolatile memory cells that can be manufactured by a logic circuit manufacturing process can be used as an alternative technology for a fuse element. The present invention is useful when applied to a semiconductor system LSI having a functional block having It can also be applied to uses such as secure ID.

1 is a block diagram showing an overall schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention. It is a circuit diagram which shows the structure of the bit cell with which the non-volatile semiconductor memory device is equipped. 2 is a circuit diagram showing an internal configuration of a latch circuit and a shift register included in the nonvolatile semiconductor memory device. FIG. FIG. 4 is a timing chart showing a write operation of the nonvolatile semiconductor memory device. FIG. 6 is a timing chart showing a read operation and a read data check operation of the nonvolatile semiconductor memory device. It is a block diagram which shows the semiconductor system LSI of Embodiment 2 of this invention. 6 is a timing chart showing a read operation of the semiconductor system LSI. FIG. It is a block diagram which shows the semiconductor system LSI of Embodiment 3 of this invention. It is a block diagram which shows the non-volatile semiconductor memory device of Embodiment 4 of this invention. It is a circuit diagram of the test mode setting means with which the nonvolatile semiconductor memory device is provided. It is a timing chart figure which shows the test mode setting by the test mode setting means. It is a block diagram which shows the semiconductor system LSI of Embodiment 5 of this invention. It is a block diagram which shows the other structural example of the semiconductor system LSI. It is a block diagram which shows the semiconductor system LSI of Embodiment 6 of this invention.

Explanation of symbols

1, 1A, 1B, 10, 10B Nonvolatile semiconductor memory device 2 Bit cell including nonvolatile memory cell 3 Latch circuit (reading means)
4 Shift register
(Writing means and reading means)
5 Control circuit (control means)
9 Test mode setting shift register 11 PMOS transistor 12, 14 NMOS transistor 13 Non-volatile memory cell 15 OR circuit 16, 70 AND circuit (logic operation circuit)
21, 22, 26, 27 MOS switch circuits 23, 24, 28, 29, 30, 31 Inverter circuits 41 (0) to 41 (m)
51 (0) to 51 (l) Function block 71 Flip-flop circuit 72 AND circuit (logic operation circuit)
SDIN Serial input data SDOUT Serial output data DOUT <n: 0> Parallel output data RD 1 shot pulse signal LAT <n: 0> Latch circuit second output signal TR <3: 0> Test mode signal

Claims (23)

A serial input data terminal and a serial output data terminal;
n (n is an integer of 2 or more) bits of parallel output data terminals;
n non-volatile memory cells;
Write means for writing write data from the outside to the n nonvolatile memory cells via the serial input data terminal;
Read means for reading out read data from the n non-volatile memory cells to the outside via the serial output data terminal and the parallel output data terminal;
A non-volatile semiconductor memory device comprising: a control unit that controls the writing unit and the reading unit. The nonvolatile semiconductor memory device according to claim 1,
The control means includes
A non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device receives a one-shot pulse signal and controls the read means to read out read data from the non-volatile memory cell based on the pulse signal. The nonvolatile semiconductor memory device according to claim 1 or 2,
The reading means includes
n latch circuits, and in the data read period, the read data from the n nonvolatile memory cells are latched in the n latch circuits, and the latched n read data are passed through the parallel output data terminal. A non-volatile semiconductor memory device characterized by being constantly output to the outside. The nonvolatile semiconductor memory device according to claim 3,
The reading means includes
The nonvolatile memory is characterized in that n read data latched in the n latch circuits is contained during the data read period, and a second output signal that is in a Hi-Z state is output during the period other than the data read period. Semiconductor memory device. The nonvolatile semiconductor memory device according to claim 4,
The reading means includes
Including a shift register composed of n flip-flop circuits to which a common clock signal is input;
The n flip-flop circuits receive the second output signal from the n latch circuits and the output signal from the previous flip-flop circuit,
Each of the flip-flop circuits latches the second output signal during the data read period, and the second output signal latched during the data read period other than the data read period is based on the clock signal. Output to flip-flop circuit,
The nonvolatile semiconductor memory device, wherein the second output signal is output from the flip-flop circuit at the final stage via the serial output data terminal. The nonvolatile semiconductor memory device according to claim 1,
The writing means includes
Including a shift register composed of n flip-flop circuits to which a common clock signal is input;
The first flip-flop circuit among the n flip-flop circuits receives write data via the serial input data terminal,
Each of the flip-flop circuits excluding the first stage receives write data from the previous flip-flop circuit based on the clock signal,
The nonvolatile semiconductor memory device, wherein a write signal of the n flip-flop circuits is input to the n nonvolatile memory cells. The nonvolatile semiconductor memory device according to claim 6,
6. The nonvolatile semiconductor memory device, wherein the shift register included in the writing unit is also used as the shift register included in the nonvolatile semiconductor memory device according to claim 5. The nonvolatile semiconductor memory device according to claim 1,
A non-volatile semiconductor memory device comprising test mode setting means for receiving a test mode serial input data and a test mode enable signal and generating a plurality of types of test mode signals. 9. The nonvolatile semiconductor memory device according to claim 8, wherein
The test mode setting means includes
A shift register in which a plurality of flip-flop circuits to which a common clock signal is input are connected in series;
The same number of logic operation circuits as the number of flip-flop circuits,
The test mode serial input data is sequentially set in each flip-flop circuit, and the output signal of the corresponding flip-flop circuit and the test mode enable signal are input to each logic operation circuit,
A combination of outputs of the logic operation circuits becomes a test mode signal. The nonvolatile semiconductor memory device according to claim 9, wherein
A non-volatile semiconductor memory device comprising: a decode circuit for decoding a test mode signal from the test mode setting means. The nonvolatile semiconductor memory device according to claim 1,
The n non-volatile memory cells are formed by a logic circuit manufacturing process. The nonvolatile semiconductor memory device according to claim 11,
The n non-volatile memory cells are
Nonvolatile semiconductor memory characterized by being formed by a logic circuit manufacturing process for forming a thick gate oxide film, out of two types of logic circuit manufacturing processes for forming two types of gate oxide films. apparatus. The nonvolatile semiconductor memory device according to claim 11,
All the transistors constituting the n non-volatile memory cells, the writing unit, the reading unit, and the control unit are formed with the same gate oxide film thickness. A nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 1,
A functional block having a multi-bit parallel input data terminal,
A semiconductor system LSI, wherein a parallel output data terminal of the nonvolatile semiconductor memory device is connected to a parallel input data terminal of the functional block. The semiconductor system LSI according to claim 14, wherein
A plurality of the nonvolatile semiconductor memory devices are provided,
Of the plurality of nonvolatile semiconductor memory devices, the first stage nonvolatile semiconductor memory device is supplied with write data from the outside via the serial input data terminal,
The nonvolatile semiconductor memory device excluding the first stage is arranged in a chain with its serial input data terminal connected to the serial output data terminal of the previous stage nonvolatile semiconductor memory device,
A semiconductor system LSI characterized in that read data is externally output from the serial output data terminal of the final stage nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device according to claim 8,
A functional block having a multi-bit parallel input data terminal,
A semiconductor system LSI, wherein a parallel output data terminal of the nonvolatile semiconductor memory device is connected to a parallel input data terminal of the functional block. The semiconductor system LSI according to claim 16, wherein
The nonvolatile semiconductor memory device is
Write data input to the serial input data terminal is input to the test mode setting means as test mode serial input data. The semiconductor system LSI according to claim 16, wherein
A plurality of the nonvolatile semiconductor memory devices are provided,
Of the plurality of nonvolatile semiconductor memory devices, the first stage nonvolatile semiconductor memory device receives write data from the outside via the serial input data terminal,
The nonvolatile semiconductor memory device excluding the first stage is arranged in a chain with its serial input data terminal connected to the serial output data terminal of the previous stage nonvolatile semiconductor memory device,
The nonvolatile semiconductor memory device at the final stage outputs read data externally from its serial output data terminal,
The semiconductor system LSI, wherein the test mode serial input data and the test mode enable signal are directly inputted to the test mode setting means of the plurality of nonvolatile semiconductor memory devices, respectively. In the semiconductor system LSI according to any one of claims 14 to 18,
The functional block has a redundant function. A semiconductor system LSI, wherein: In the semiconductor system LSI according to any one of claims 14 to 18,
The functional block has an analog trimming function. A semiconductor system LSI, wherein: In the semiconductor system LSI according to any one of claims 14 to 19,
The functional block receives a one-shot reset pulse signal for initializing the functional block during the power-on sequence of the semiconductor system LSI,
The reset pulse signal is input to the nonvolatile semiconductor memory device, and based on the reset pulse signal, the reading unit reads out read data from the n nonvolatile memory cells to the outside. Semiconductor system LSI. In the semiconductor system LSI according to claim 15 or 18,
The number of the plurality of nonvolatile semiconductor memory devices is determined according to the total number of parallel input data terminals of the functional block. The semiconductor system LSI according to claim 22, wherein
The plurality of nonvolatile semiconductor memory devices are all the same configuration nonvolatile semiconductor memory device having the same number of parallel input data terminals.

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