TW200414468A - Flip-chip package structure - Google Patents

Abstract

The present invention provides a kind of flip-chip package structure that contains at least the followings: a packaging substrate with an internal circuit, in which plural first contacts arranged with a constant gap are formed on one surface of the packaging substrate, and a trace line region is located at the region excluding the first contact on the surface; an IC chip assembled on the surface of the packaging substrate stated above, in which the IC chip is electrically connected to the packaging substrate through the use of plural conduction bumps arranged between the IC chip and the first contact with a constant gap; the filler material, which is formed between the packaging substrate and the IC chip so as to fill in between the conduction bumps; and an electric protection apparatus having a protrusion portion and an edge extension portion, in which the protrusion portion covers the IC chip and the edge extension portion extends to the surface of the packaging substrate to cover the trace line region. In addition, a bonding material is used to connect the edge extension portion and the packaging substrate, so as to fix the electric protection apparatus on the packaging substrate where the gap height between the edge extension portion and the packaging substrate surface is not larger than 40 mils.

Description

200414468

[Technical field to which the invention belongs] The present invention relates to a semiconductor device and a flip-chip package structure. Related to a kind of [Previous Technology] Please refer to the figure 系 to show a traditional cover. The so-called flip chip package is on the active surface of the 1C chip 180 or ^ ° 冓 7 0 0. Board (SUbstrate) 7 0 2 —Contacts 71 on the surface = After the package base, the 1C chip 180 is bonded with the active surface facing downwards = 790 702, and the IC chip 18 and the chip The chip packaging base = = a filling 7 7 0 and filled with a ball 1 (bal 1 Placement) between the conductive bumps 79 0 and other methods on the chip-on-chip packaging substrate ^ 'for example ^. Surface connection The technique of forming a solder ball 73 2 as a pin on the point 73 0, and the packaging structure. Compared with the conventional step of forming a flip chip, the area of the mounting structure must be adjusted to the above soldering. The layout of the lines (丨 ay —) ^ and > Bi Xifeng is larger than the area of the IC chip; in the flip-chip package structure, the contact range of the IC chip and the mounting substrate is only distributed in the IC chip itself ^: It can help reduce the area of the package structure or package base, especially the number of pins is less than 2000. The area of the chip can be reduced to 1 or 2 times the IC chip area. The following is the chip size package (chip size package). -scale package; CSP). And at the center = central process unit (CPU), graphics chip, crystal Set (Chipset), or other systems to a single wafer (system 〇n a chip; S〇C) and the 6 meter package structure I c of the wafer, because of its multiple functions and high operating

0702-8850TWf (nl); 91P58; Dwwang.ptd Page 5 200414468 V. Description of the invention (2) " ~ '-the operating frequency, the number of pins will usually exceed 300 or even 1000, its package The substrate routing is complicated, and the package structure or the area of the package substrate is difficult to reach the level of the chip size package described above; however, compared to the conventional wi re bonding package, the flip chip package structure In this case, the short path between the IC chip and the package substrate helps reduce the interference and delay when electronic signals are transmitted between the IC chip and the package substrate. Therefore, the application of flip-chip packaging structures for non-chip-size packages is also becoming more and more popular. ","; The name of the "I have to pass the market for electronic products to be light, thin, short, small and small $-In addition to the 1 C chip design work must be done, in a limited area of the semiconductor, base, put more In addition to many electronic components; in the design of the circuit board, not only in the application of the above-mentioned flip-chip packaging structure, the delta of the flip-chip packaging substrate must also be placed in a limited area with higher-density internal wiring. Therefore, when there is no extra space in the transmission line (transmission 1 ine), VSS or VDD can be added for shielding. As a result, the electrical signal change of a trace line (signal⑽) will occur between adjacent wires. The crosstalk effect (crosstaik ef feet) occurs due to the inductive inductance (mutual induCtance) and the inductive capacitance (mutual capacit〇r), which will not only affect the signal quality of the circuit and system stability, but also affect the special ten peaks K of the transmission line. The character impedance of the 7th Xuan side ice sun changed. In the design of the transmission line of the I substrate or other types of circuit boards, the most impediment is the lmpedance match. The basic wooden structure of the transmission Qinshan is an output terminal that transmits a signal to a signal via a wire. A load _? ^ ^ The $ line is connected to the output end by the load end to form a ^, k is not in the transmission line, the output impedance of the signal is ZG, load

200414468

V. Description of the invention (3) The impedance is ZL, the characteristic impedance of the transmission line is Z0, and ZG = Z〇 = ZL is the impedance matching. As far as the load side is concerned, when Z0 = ZL, all the transmission lines ^ stomach energy and signals will be completely transmitted to the load side; if the transmission line, the characteristic impedance changes due to the influence of the crosstalk effect, resulting in resistance ^ If they do not match (impedance mismatch), part of the energy and signal will be reflected (re fleet ion) back to the above output. The above-mentioned signal reflection b phenomenon will cause the signal to overshoot, undershoot, 'and ringback, and affect the signal's unity (mon〇t〇icity)' will not only affect the circuit signal Quality and system stability will cause damage to electronic components. If the characteristic impedance value of the above-mentioned transmission line can be controlled and then adjusted as needed, the difficulty in circuit design can be greatly reduced. In addition, in the flip-chip package structure 700 of FIG. 7A, the 1C wafer 180 is in a bare die state, which may easily cause mechanical damage such as chip cracking in a subsequent processing process. The flip-chip package structure is electromagnetically protected to prevent the flip-chip package structure from external radio frequency interference (RFI) or electromagnetic interference (EMI). The flip-chip package structure is disclosed in US Patent No. 5 No. 3,3,0,5,9, the patent is a method of forming a metal thin film by sputtering on the surface of the exposed chip c and the primer (under fi 1 1), and making the above metal; 4 film connected to A ground pad (groundpad) on the packaging substrate is in a grounded state to target the package structure, especially the chip, to provide electromagnetic protection; and US Patent No. 5, 3, 7, 4, 04 patent system Has formed a bottom

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i 200414468 V. Description of the invention (4) The flip-chip packaging structure of the glue is more traditional. It is a traditional sealing process: a metal content of about 70% to 75% and a conductive and thermally conductive sealing compound (㈣ 丨 heart called compound ) Is formed after the underfiii step has been performed, and

If the package substrate with a ground pad is located on the periphery of the chip, the sealing compound covers the 1C chip and the ground pad, and a plurality of heat sink fins (fins) are formed on the upper surface of the sealing compound. The function of electromagnetic protection and heat dissipation. Called No. 1 A ~ 1 C, it is shown in US Patent No. 5, g 7 7, 6 2 6 and Japanese Patent Publication No. P2 0 0 0-775 75A. One of the heat dissipating device 32 is a top view (FIG. 1A), a cross-sectional view (FIG. 1), and an application of a flip chip package structure (FIG. 1C). In FIG. Part 32a, a protruding part 32b, a supporting part 32 () located at the protruding part 32b, and four supporting parts 32d located at the flat part 32a; and a cross-sectional view of the heat sink 32 along the line ^ is shown in the first Figure 1 B. In Figure 1 C, on the packaging substrate 20, the IC chip 22 is assembled on a surface of the packaging substrate 20 in the form of a flip-chip package; and then the primer-filling step is performed to remove the substrate. The glue 2 4 a fills the gap between the conductive bumps 26 a between the IC chip 2 and the 2 package substrate 20; The support 32 is assembled on the package substrate 20, in which the support portion 3 2 c located at the protruding portion 32 b is connected to the IC chip 2 2, and the four support portions 3 2 d located at the flat portion 3 2 a make the heat dissipation device 32 and The packaging substrate 20 forms an electric company; and then the heat dissipation device 32 is covered with the sealing compound 30 and the protrusions 32b are exposed. The heat dissipation device 32 is the exposure of the protrusions 32b and the support portions 32 and 10. The chip 2 2 The IC chip 2 2 is provided with a heat dissipation function; and the support part 32 is electrically connected to the package substrate 20 and the support part 3 2 c is connected to the 1C chip 22.

200414468 V. Description of the invention (5) ^-The function of providing electromagnetic protection to IC chip 2 2 in turn. In addition, please refer to the second figure, which shows the semiconductor chip-size package (cSP) disclosed in the Republic of China Patent Bulletin No. 4 1 0445 and U.S. Patent No. 6, 2 55, 丨 40. The structure has a heat sink, 3-12 is covered on the a semiconductor 311 which has been combined with the substrate 3ι ^ in the form of a flip-chip package, and its edge is connected to the semiconductor wafer 311 and the substrate 3 1 3. The gap between the solder balls 3 丨 6 and the outwardly extending glue filling sound t ^ ^ ^ # 312 ^ # ^ € ^^ ^ Two = sex two, connection; and the heat sink 312 can still be connected to the substrate 313: ,,, ° to strengthen the function of providing electromagnetic protection to the semiconductor wafer 3 1 1 In the previous techniques, only the flip chip package was electromagnetically protected to avoid external electromagnetic interference from the outside world. ^ 1 rejection of radio frequency interference or: control of the characteristics of the transmission line; the technical content is given to the methods and techniques of π · LL, A Day wish, and the technical level of n in the flip-chip packaging structure cannot be caused The increase in the shape of the special line density of the transmission line. Resistance to changes and crosstalk between wires

In addition, please refer to the semi-conducting permits / sheets disclosed in No. 3a ~ 3B No. 50 8778 (Paper 3A of the Republic of China Patent Publication) and the cross-sectional view of the semiconductor wafer 4a-day and ten-sheet structure & The top view of the heat sink is Chu Pigang, the semi-conductor diagram (Picture 3B) shown in Figure 3A, and the board is electrically connected to the body chip package structure 2. The system includes: a semiconductor wafer 42 on a base substrate 41 ; And set in semiconducting

0702-8850TWf (nl); 91P58; Dwwang.ptd V. Description of the invention (6) The sheet 45 has a first heat-dissipating part, and the heat part 45b is respectively from the first K. In the Republic of China patent package structure 2 the relevant bulk structure is disclosed. The transmission line provides cross-talk phenomenon between the conductors at the current technological level of the substrate and changes in the internal circuit density of the substrate and the cross-talk between the conductors. The heat sink 45 on the wafer 42 includes heat dissipation 45a and a pair of second The heat radiating portion 45b is underheated in the second month.卩 4 5 a is curved on opposite sides. The gas bulletin No. 5 08 778 is only in the technical content of the semiconductor wafer hot sheet 45, and the method and technical content of the flip chip sealing and shielding to control the characteristic impedance of the transmission line are equally well; therefore, it cannot be considered In the crystal package structure: the characteristic impedance of the transfer line caused by the increase is like the net case. [Summary of the Invention] In view of this, the main purpose of this private structure with an electrical protection spoon is to provide a characteristic of the transmission line in the flip-chip package junction structure to block the green 2 to control and adjust the flip-chip package to reduce the difficulty in circuit design. ^ Second, it can increase the flexibility of circuit design. Another object of the present invention is to provide an electrical protection device, which can control two kinds of next-day dressing structures, which have first-line characteristic impedance changes. Transmission quality and system stability in the structure. … Circuit signal products in a crystal package structure Another object of the present invention is an electrical protection package i, which can be controlled and adjusted; :: 3-pack structure with characteristic impedance change of the transmission line, ° = at the crystal package The signal quality and system stability of the transmission path in the structure can be protected more than the electrical power in the flip-chip packaging structure; moreover, the flip-chip packaging structure can be protected; V. Description of the invention (7) The hibiscus is not abnormal. The circuit signal is damaged, which improves the reliability and service life of the structure. I know that the flip chip technology of the present invention is to provide a flip chip packaging structure, which starts from the beginning. In addition, in addition to controlling and adjusting the above-mentioned cover #shape to protect the above-mentioned cover 2Γ, the above-mentioned electrical protection device is mechanically broken; The heart piece of the clothing structure is knotted in the subsequent processing process: up to the above: "The present invention provides-a kind of covering the above sealing substrate: table = base: reverse, with-internal wiring, contacts;-丨^ Surface, there are several ICs ah & f arranged at a certain gap, assembled on the surface of the package substrate, the first contact of the chip and the package substrate • ma ^ ¥ Electric bump and The package substrate is formed electrically, t, 21% between the sealed substrate and the 1C wafer. The filler is further filled in the β channel + interstitial space between the ¥ electric bumps; and the output = ΐ — a protruding portion and an edge extension, where L = complex crystal, and the above edge extension extends to the upper fan 1, ": ί Surface '11 is connected to the above edge extension by a bonding substance ϊ ΐ: The electrical protection device is fixed on the surface, and the height of the gap between the edge extension and the surface of the package substrate is not more than 40 mil. [Embodiment] For the above and other purposes, features, and advantages of the present invention, the f-junction has a structure that can not crystallize the first above-mentioned upper connection, and an electrical package. The above is more clear with the above

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P.11 0702-8850TWf (nl); 91P58; Dwwang.ptd 200414468 V. Description of the invention (8) Comparative example, combined with the tenfold manifestation, three preferred embodiments and attached drawings are given below for detailed description. It is as follows: 1. An example: Figure 4A of the Oral Examination Examination, which shows the present-structure 4 0 0. Its towel, this hair? /-The flip-chip package 402 of the embodiment is a package having a package substrate used for internal circuits: board Kir;? Applications are limited to those skilled in the art using the above form, in: 1: package form Any packaging structure, which is beyond the spirit and scope of the present invention, can be used as a flip-chip package substrate of the first embodiment of the present invention. The protection device 440 may have a single-crystal package structure 400 which has an electrical property; a linear impedance change, wherein a contact 41 is arranged on a surface of the package substrate 4.2 at a certain gap. The above-mentioned surface is formed by a plurality of conductive bumps 4 9 0 and a package substrate 40 2 which are arranged with a certain gap between the contact 410 and the contact 410. The shape of the filler 4 7 0 is formed in the package. Between the substrate 4 0 2 and the c crystal 180, and the filler 47 0 is filled between the gap of the conductive bump 49 0 and the electrical protection device 44 0, the upper view of which is shown in Figure 4β, ^ f A protruding portion 446 and an edge extending portion 444, wherein the protruding portion 446 covers the 1C chip 180, and the edge extending portion 444 extends to the above-mentioned surface of the package substrate 4 ′, so that the electrical protection device 4 4 ′ may be effective. Control and adjust the characteristic impedance change of the transmission line in the flip-chip = I structure 4 0, and connect the edge extension 444 to the above surface of the package substrate 4 2 with a bonding substance 422. 200414468 V. Description of the invention (9) Electricity The protective device 440 is fixed on the package substrate 40. In addition, there is a 1C chip 18 for heat dissipation. The imaginary protrusion Qiu “and ca n’t use the bonding material 422 and 1 t μ in addition to 1 t μ” to produce σM46, which can make the electrical protection device 440 more capable of helping the 1C chip 180 to dissipate heat outside the head. More 1 The material of the better Lt bio-protection device "° is a conductive material. -Anti-: Strong :: Secondary electrical protection. The surface layer of the vibration protection can also have an etched coating; and in consideration of help & "⑽" = ";" 422 is preferably-a thermally conductive substance such as-metallic silver; and a mixture with a resin. 1 knife and the package substrate 4 0 2 on the surface and the contact 4 1 f) has a trace llne region in the A μr field system, and the area extension 444 of the lead 2 4 is covered; the lead F toilet, Zhenling, and spring area are Yuanyan helmet door makeup shovel +, Japanese friends. The gap between the human edge extension 444 may be two = gap-like sadness or a gap of not more than 40 mil, and In the embodiment of the present invention, the above-mentioned lead region is in a state of a marginal gap. The gap between the Wuliang Dagger /, the edge, and the water extension 444 is infinite. On the other surface of the package substrate 402, there are a plurality of external contacts: 43 0 ', and the external contacts 43 are respectively joined with a solder ball 432. , Its material = m-based tin-based alloy or tin-based alloy containing no error-like tin balls. The flip-chip package structure 400 is soldered by a solder ball 432 to an external component such as a printed board: (The drawing is shown in the figure), and then the final electricity is completed; The schematic diagram of the relative positional relationship between the laminated circuit and the edge extension 444 in the mounted substrate 4 is shown in the "Figure." Five out of the first layer wiring 451 of the package substrate 402

200414468 V. Description of the invention (10) The upper conductors TT1 ~ TT5, and the five lower conductors TB5 of the sixth-layer wiring 45 6; and the widths of the upper conductors TT1 ~ TT5 and the lower conductors TB1 ~ TB5 are about 4 / / m, the thickness of the wires are about 1 5 // m, and there is a gap of about 4 m between the adjacent wires, and the upper wires ΤΠ ~ ΤΤ5 and the lower wires TB1 ~ TB5 are each about 3 5 thick. // m solder mask 4 6 1 and solder mask 4 6 7 with a thickness of about 3 5 // m. In addition, there is a dielectric layer 4 6 2 having a thickness of about 3 3 // m between the first layer of wiring 451 and the second layer of wiring 452, wherein the thickness of the second layer of wiring 4 5 2 is about 21 // m; A dielectric layer 463 having a thickness of about 70 // m is formed between the second layer wiring 452 and the third layer wiring 453, wherein the thickness of the third layer wiring 453 is about 18 // m; the third layer wiring 453 and There is a dielectric layer 464 with a thickness of about 5 0 2 // in between the fourth layer wiring 4 5 4, wherein the thickness of the fourth layer wiring 454 is about 18 // m ′ between the fourth layer wiring 454 and the fifth layer wiring 455 There is a dielectric layer 465 with a thickness of about 70 // ra between them, of which the thickness of the fifth layer line 455 is about 21 // m; between the fifth layer line 45 5 and the sixth layer line 45 6 there is a thickness of 33 // m of dielectric layer 466. Among them, the second layer line 4 5 2, the third layer line 45 3, the fourth layer line 4 5 4 ′ and the fifth layer line 4 5 5 are copper layers; the second layer line 45 2 and the third layer line 453 is the VSS layer, that is, the ground layer; and the fourth layer 454 and the fifth layer 455 are the VDD layer, which is the power layer. In the first embodiment of the present invention, the electrical protection device The edge extension 444 of 4 4 0 and the solder mask layer 461 of the package substrate 40 are in a state of no gap, and the electrical protection device 440 is not connected to the second layer circuit 4 5 2, the third layer circuit 453, or other The grounding element is electrically connected and is in an ungrounded state; and the semiconductor package structure of the first embodiment of the present invention obtained by an electrical simulation method

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V. Description of the Invention The characteristic impedance control (mutual inductance) value of the transmission line (1-4) is recorded in Table 1. The range and the induced inductance between the wires Second embodiment: Oral tea tea test 5 Picture 'shows this Li The chip-on-chip package structure 50 of the second embodiment of the beating and beating is not included. Among them, the package substrate of the present invention, which is the same as that of the conventional embodiment, is used as the package substrate. It is a flip-chip package substrate with a BGA form having an internal circuit of & & poor α horse, and a layered circuit, but does not mean that the application of the invention is limited to the use of the above-mentioned package substrate. As long as the packaging structure is in the form of a frosty package, 4α1 + text, and daily packaging, any = ϊίΐ 'without departing from the spirit and scope of the present invention a, when you can do something ^ 更 ㈣ 润 = 4 use other A flip-chip package substrate. The structure of the day-to-day cover I 5000 has an electrical protection 4I and 5 4 0, which can effectively approve the Ueda Corporation to recognize this α & system to adjust the flip chip The characteristic impedance change of the transmission line in the package structure 5 0 〇 ^, Bajia on the sealing substrate 5 02, one surface of which is two T r (μ 彳 Q η〆f)] 5 1 0 and a plurality of contacts 5 2 0; and the IC chip 1 8 0 series Assembled on Feng Mengqi ^ n 9 The above-mentioned two surfaces of -zong μ are arranged in a plurality of gaps to find the wafer 18〇 and the contact 51 590 and the package substrate 5 0 2 to form an electrical company ·] 3 ¥ Electric bump seven people w Zhuanggan ”take the quick shelter, rural entrance, in addition the filler 570 is formed between the coating substrate 502 and the 1C chip 180, and the gap between the conductive bump 590 Door. 1 ^ ^ brother 1) more true filling in the protruding portion 546 and an edge extending adjacent to 544, clothing b4U ^ one

It is said that κ 18 (), and the name # 申 邛 4 ”in the protruding part 54Θ covers the 1C extension part 544 and extends to the above surface of the package substrate 502, so that the electrical protection device 54Q can effectively control and adjust the structure 5 0 The characteristic impedance of the transmission line in 0 changes, the clothing becomes more mechanized, and the edge extension 544 is more

200414468

There are " " " " Contacts 5 4 2 'and are connected by one by eight ^ an two times + α. !! Bonding substance 5 2 2 Connected to contact 542 * Connected to 5 2 0 The sexual protection device 54 is fixed to the seal :: contact resistance protection device 540 and the upper layer of the package substrate 502, and the electrical layer (not shown in the figure) is connected. However, the electrical guarantee shown in the detailed picture in a grounded lightning circuit is not shown. f @ 'It will be omitted to connect another 1C. In the case of an extra and better anti-corrosion package base, it helps the IC and the thermally conductive bad oxygen tree and the field system has a lid; on or with, the above point 5 3 0, well-known In terms of needs, it has a function to help the 1C chip 180 dissipate heat. , 40 can be described as follows: The material of the protective device 540 is a conductive material, or a reinforced plating; while considering the electrical properties: = there is a board 5. 2 grounding in the laminated circuit = 2, the bonding substance 522 is more than It is better that-conductive mine #connected, grounded, grounded, such as the bonding material 5 2 2 '& is a mixture of conductive grease. It is described as an area other than 51 ° between a metal silver powder and a metal plate on the guide table / on, the contact is more than 51 °, and the other d in the external packaging base is === : Between f states. And the above-mentioned external contacts 530 are respectively joined,-two outer =

200414468 V. Description of the invention (13)-The tin-ball 532, which can be a lead-based alloy or a lead-free tin-based alloy, 532 solders the flip-chip package structure 5 0 0 to an external component such as printing :: The above (not shown in the figure) 'to complete the final electronic schematic diagram of the relative positional relationship of the laminated circuit blood = extended portion 544 in the package substrate 502 of the second embodiment of the present invention is the same as in the first generation The relative positional relationship between the laminated circuit and the edge extension 4 in the package substrate 402 is shown. Please refer to the 4C diagram of the present invention for the description of the 4C diagram, which is omitted here. In the second embodiment of the present invention, the gap 544 between the extension 544 of the electrical protection device 54 and the package substrate 502 is in a state without a gap, and the above-mentioned laminated circuit of the device and the package substrate 502 is One of the grounding protections is when the second layer line 452 or the third layer and the line 4 5 3 in the 4C diagram are electrically connected, but in a grounded state; and the present embodiment obtained by the electrical simulation method The characteristic impedance control of the transmission line of the semiconductor package structure of 500 and the induction inductance (mutual inductance) between the wires are recorded in Table 1. The third embodiment: Please refer to FIG. 6A, which shows the second embodiment of the present invention; it is a flip-flop following the second embodiment of the present invention; The difference between the two is that in the third embodiment of the present invention, the contact point 542 is used to replace the second daily coat structure of the present invention # 5 0 0 ^ ^ II ^ £ 540 ^ ,, 542 The degree of change is still between the electrical protection device 54 and the package substrate 502: the electronic game If Page 17 0702-885mf (nl); 91P58; Dwwang.ptd 200414468 V. Description of the invention (14) — Grounding layer (corresponding to the second layer of the line 4452 in Figure 4C), the first embodiment of the present invention is in a state of 1 connection and grounded, which makes the present invention the third embodiment ;: 5i: r " ^ 5 ° 2 ^ ^ ί: crystal seal :: milk gap 548. For other descriptions of the structure of the third embodiment of the present invention, please refer to the related packaging structure 500 after the second embodiment of the present invention. The description is omitted here. In the third embodiment of the flip-chip packaging structure 5QQ, the edge extension 544 of the electrical protection layer 540 and the ^ Γ line area on the surface of the packaging substrate 502 are repeatedly disposed. There is an air gap gap 548 of no more than 40 mi 1 · (1 · 〇16 mm), and the electrical protection device 54 is connected to one of the laminated circuits of the package substrate 50 Layer (corresponding to the second layer line 452 or the third layer line 453 in FIG. 4C) is electrically connected and grounded; and the semiconductor package structure 5 of the third embodiment of the present invention obtained by an electrical simulation method 5 The control range of the characteristic impedance of the transmission line and the value of the induced inductance (mutual inductance) between the conductors are recorded in Table 1. Comparative Example: Refer to Figure 7A, which shows a flip-chip package structure of a comparative example 7 〇 〇 'is a traditional flip-chip package structure 700 without electrical protection. Among them, the package substrate 7 used in the comparative example of the present invention is a BGA form with an internal circuit of a six-layer laminated circuit. The flip-chip package structure 700 according to the comparative example of the present invention includes: a package substrate 7 0 2 ′, one surface of which has a plurality of contacts 71

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Page 18 200414468

And a plurality of contacts 720; and the iC chip 180 is assembled on the surface of the package A, and a plurality of conductive bumps between 71 and 710 are arranged in a slow-gap arrangement to form an electrical connection with the package substrate 702; The filler 770 is formed between the package substrate 702 and the 1C wafer 180. That is, the filler 770 fills the gap between the conductive bumps 79. "Another" on the other surface of the package substrate 7 〇2 is ancient,-contact 73 ° ', and the above external interfaces are respectively bonded with a material: a tin-based alloy containing the wrong or tin-based two without error 』Two flip-chip packaging structure 70 by Siga. Tan Jie :: == on the external component (not shown in the drawing), and then complete the most phase: = n702 The schematic diagram of the relative positional relationship between the laminated circuit and the edge extension surface is shown in the first redundant figure. Recording 丨:; Five upper wires τη wide TT5 in the first layer of the circuit 751 sealing Λ substrate 702, and five lower wires TB1 ~ TB5 in the sixth layer of the circuit 756; ^

The line widths of the lines TT1 to TT5 and the lower conductors TB and TB5 are both Δ Λ) 4η ... V degrees are all about 1 5 // m, and the adjacent guide lines are „recognition ^ ^ and… tTT " TWr two There is a gap of about 40mm between the top and bottom MTHT5 and the lower conductors TB1 to TB5. The solder mask 761 and the solder mask 767 with a thickness of about 35 claws are the first layer of the circuit. 751 and the second layer line 752 < n & complex ^, in the dielectric layer 762, where the second layer line 75 is at the gate of the second layer line 752 and the third layer line 753, and m, In the third electric line 3, where the third layer of the line 7 5 3 =: the thickness of about 7 ° ", the degree of y of the medium 1 ~ 8 is 8 there is a thickness of about 502 between the first layer line and the fourth layer line 754 Electricity

200414468 V. Description of the invention (16) Layer 764, of which the thickness of the fourth line Yu 7 7 ^ wooden arm line 7 54 is about 18 // m line 2 754 ^ green line 75 5 between 22: 2 Layer 2 of the line 75 5: There is a gap between == layer ㈣56 ^ The first layer of the line 75 2, the third layer of the line 753, the fourth ^ 54, and the fifth layer of the line 75 5 are copper The second layer is 75 ^ 2, the first layer is 53 series, it is the vss layer, which is the ground layer (gr_d); and the fourth layer 754 and the fifth layer 75 are the VDD layer, which is the power layer. Alas. The semiconductor package structure of the comparative example obtained by the electrical simulation method is used to record the characteristic impedance control range of the transmission line and the value of the induced inductance (mutual inductance) between the wires in Table 1 below. Mutual inductance of lead TT1 and lead TT2 (nH / mrn) Mutual inductance of lead TT1 and lead Π3 (nH / mrn) Mutual inductance of lead TTII and lead TT4 (nH / mm) Characteristic impedance control (Ω) Comparative example 0.0710 0.0236 0_ 51 First Example 0.0269 0.0146 0.0138 32-51 First example 0.0131 0.03067 〇03⑴6 30-51 Second rich example 0.0599 0.0149 0.00404 47-51 ^ Table 1 The characteristic impedance of each of the examples and comparative examples is controllable. For the range and the electrical simulation results of the mutual inductance between the lead Π and the lead TT2, TT3, and TT4 of each of the examples and comparative examples, please refer to Table 1, which shows the characteristic impedance of the examples and comparative examples. ) Value controllable range and the electrical simulation results of the mutual inductance between the wire TT1 and the wires TT2, TT3, and TT4 of the examples and comparative examples. In the conventional flip-chip package structure 7000 of the comparative example

0702-8850TWf (nl); 91P58; Dwwang.ptd Page 20 200414468 V. Description of the invention (17) 'No. of electrical protection device _, i # Package structure 40 0, electrical protection I, 4 The edge extension 444 of the crystal-covered grounded R R / Bao Jiang Yi 44 〇 is ungrounded, and the edge extension 444 * beautiful in the state of the gap. ¥, the V-line area of the soil plate 402 is infinite, and the electrical simulation results can be made in the range of Μ Ο ^ η: the thickness is in the range of 32 Ω to 51 Ω; and the flip chip package structure 5 0 0 , Electricity, Zhuangyue /: only the yoke example is grounded to the substrate 502: Γ and: 4; the lead region of the edge extension 544 is a gap-free energy layer edge extension 544 and the substrate The electric simulation of 502 is carried out in a nutshell with a characteristic impedance value within a controllable range; the range is from 300 to 5100; and the crystal package structure after the implementation of this example 5 0 〇 ， 中 ， 电 性伴 1 # The edge extension 544 is grounded to the substrate: the 540 portion 544 and the substrate 50 2 of the lead plate 50 2 are: the ground layer, and the edge extends 548, which has a characteristic resistance f _ ^ / 、 There is an air gap of not more than 40 mil. Controlled in the heart ~: The range of electrical simulation results is acceptable, which is: Fruit: Know: The characteristics of the transmission line in the flip-chip packaging structure of the present invention The purpose is to control the above-mentioned flip-chip package to reduce the difficulty in circuit design during the 5th week; to improve the flip-chip package. The AA chip is designed for two purposes. The quality and system stability of the alum number are damaged and the circuit signal is damaged, and the connection is not abnormal. ^ Reliability and service life of the multi-crystal package structure In addition, the flip-chip package of the present invention is constructed with an electrical protective device

200414468 V. Description of the invention (18) The device covers the IC chip and the packaging substrate in the above-mentioned flip-chip packaging structure, and can further protect the IC chip of the above-mentioned flip-chip packaging structure from mechanical damage during subsequent processing. In terms of the electrical simulation results of the mutual inductance between each group of wires TT1 and wires TT2, TT3, and TT4, the electrical protection device of the flip-chip package structure of the three embodiments of the present invention can also effectively reduce the The mutual inductance phenomenon also makes the electrical protection device of the flip-chip package structure of the present invention have the additional advantage of reducing the mutual inductance phenomenon between the wires. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Any person skilled in the art can make some modifications and retouching without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application.

0702-8850TWf (n 1); 91P5 8; Dwwang. Ptd page 22 200414468 Figures briefly explain Figures 1 A to 1 C are a series of top and cross-sectional views used to illustrate US Patent No. 5, 9 7 7, The heat dissipation device disclosed in 6 2 6 and Japanese Patent Publication No. P 2 0 0 0-7 7 5 7 5A and its application in a flip-chip package structure. FIG. 2 is a cross-sectional view illustrating the semiconductor cube-size package structure disclosed in the Republic of China Patent Publication No. 4 10 445 and the US Patent No. 6, 2 55, 140. 3A to 3B are a cross-sectional view and a top view, which are used to illustrate the semiconductor chip package structure disclosed in the Republic of China Patent Publication No. 5 0 8 7 7. 4A to 4C are a cross-sectional view, a top view, and a schematic view, which are used to explain a flip-chip package structure according to the first embodiment of the present invention. Fig. 5 is a sectional view for explaining a flip-chip package structure according to a second embodiment of the present invention. Fig. 6 is a sectional view for explaining a flip-chip package structure according to a third embodiment of the present invention. Figures 7A to 7B are a cross-sectional view and a schematic diagram for explaining a conventional flip-chip package structure as a comparative example. [Symbol description] 2 0 ~ package substrate; 2 2 ~ IC chip; 2 4 a ~ primer; 26 a ~ conductive bumps, 2 8 ~ solder balls; 3 0 ~ sealing gel; 32 ~ heat sink;

0702-8850TWf (nl); 91P58; Dwwang.ptd Page 23 200414468 Brief description of the drawing 3 2 a ~ flat part; 32 b ~ protruding part; 3 2 c ~ support part; 3 2 d ~ support part; 4 1 ~ Substrate; 42 ~ semiconductor wafer; 4 3 ~ bump; 44, 47, 48 ~ filling body; 4 5 ~ heat sink; 45a ~ first heat sink; 45b ~ second heat sink; 4 9 ~ solder ball; 2, 4 0 0, 5 0 0, 5 0 0 ', 7 0 0 ~ flip-chip package structure; 4 0 2, 5 0 2, 7 0 2 ~ package substrate; 11 0, 1 3 0 ~ contacts; 4 3 2 , 5 3 2, 7 3 2 ~ solder balls; 4 7 0, 5 7 0, 7 7 0 ~ fillers; 1 80 ~ IC wafers; 490, 590, 790 ~ conductive bumps; 311 ~ semiconductor wafer, 3 1 2 ~ heat dissipation element; 3 1 3 ~ substrate; 3 1 4 ~ adhesive epoxy resin; 3 1 5、3 1 6 ~ solder ball;

0702-8850TWf (nl); 91P58; Dwwang.ptd Page 24 200414468 Simple and early description of the drawing 3 1 7 ~ filling layer; 3 1 8 ~ void; 3 1 9 ~ void; 4 1 0, 4 3 0 ~ connected Point; 4 2 2, 5 2 2 ~ bonding material; 440, 54 0 ~ electrical protection device; 4 4 4, 5 4 4 ~ edge extension; 446, 546 ~ protruding portion; 4 5 1, 7 5 1 ~ First layer line; 4 5 2, 7 5 2 ~ Second layer line; 4 5 3, 7 5 3 ~ Third layer line; 454, 754 ~ Fourth layer line; 4 5 5, 7 5 5 ~ No. Five-layer circuit; 456, 756 to sixth layer circuit; 4 6 1, 4, 6 7 to solder mask; 46 2, 46 3, 464, 46 5, 46 6 to dielectric layer; 510, 52 0, 5 3 0,542,542 '~ contact; 5 4 8 ~ air gap; 7 1 0, 7 3 0 ~ contact; 761, 767 ~ fresh-proof layer; 7 6 2, 7 6 3, 764, 7 6 5, 7 6 6 ~ Dielectric layer; TB1, TB2, TB3, TB4, TB5 ~ lower conductor; TT1, TT2, TT3, TT4, TT5 ~ upper conductor.

0702-8850TWf (nl); 91P58; Dwwang.ptd Page 25

Claims (1)

200414468 6. Scope of patent application 1. A flip-chip package structure at least includes: a package substrate having an internal circuit, and a surface of the package substrate having a plurality of first contacts arranged at a certain gap, and the surface having A trace line area is located outside the first contacts: An IC chip is assembled on the surface of the package substrate. The 1 C chip is arranged in a plurality of gaps between the IC chip and the IC chip. The conductive bumps between the first contacts and the package substrate form an electrical connection 'a filler is formed between the package substrate and the IC chip', and the filler is further filled in the conductive bumps. Between the gaps; and an electrical protection device having a protrusion and an edge extension, wherein the protrusion covers the IC chip, and the edge extension extends to the surface of the package substrate to cover the The lead area is connected to the edge by a bonding material and extended to be fixed between the sealing surfaces. 2. If the protrusion is applied, 3. If the electrical protection is applied. 4. If the package substrate protection device is applied. The bonding material personal protective device portion and the surface of the package substrate mount the electrical protective device on the substrate, and the gap between the edge extension portion and the package substrate is not more than 40 mi. The flip-chip package structure described in item 1 of patent fe, wherein the j c chip is connected by the bonding substance. : The flip-chip package structure described in item 1 of the patent scope, and the material in the description is selected from aluminum or copper.请 Please ask for the main package of the two as described in item 1 of the patent scope. The human heart has a day-to-day packaging structure. The surface of the § 亥 of the complex Φ contains more than one, and the edge extensions of the jf and the electrical include more:保 Electrically guarantee to connect each of the second contact disks—connected to each other. The wrong connection is fixed on the package substrate: 0702-8850TWf (nl); 91P58; Dwwang.ptd Page 26 200414468 6. Patent application scope 5. The flip-chip package structure described in item 4 of the patent application scope, wherein the package substrate further includes a ground element. 6. The flip-chip package structure according to item 5 of the scope of the patent application, wherein the second contacts are electrically connected to the ground element by an internal circuit of the package substrate. 7. The flip-chip packaging structure according to item 1 of the scope of the patent application, wherein the bonding substance is a conductive substance. 8. The flip-chip packaging structure according to item 2 of the scope of the patent application, wherein the bonding substance is a conductive and thermally conductive substance. 9. The flip-chip package structure according to item 1 of the scope of the patent application, wherein the bonding substance is a mixture of metal silver powder and epoxy resin. 10. The flip-chip package structure according to item 1 of the scope of patent application, wherein the gap between the package substrate and the edge portion of the electrical protection device further includes a state without gap (g a p). 0702-8850TWf (nl); 91P58; Dwwang.ptd Page 27