TW200410611A - Pad-less design of high-density circuit board and its manufacturing method - Google Patents

Abstract

A kind of pad-less design of high-density circuit board and its manufacturing method are revealed in the present invention. The invention includes the following steps: providing a circuit board substrate; forming an external circuit on the circuit board substrate, in which the external circuit contains plural external contacts and the width of external contact is not larger than the line width of the external circuit; forming a solder mask layer for covering the circuit board substrate and the external circuit, in which the solder mask layer is provided with plural solder mask openings to expose external contacts and the diameter of each solder mask opening is not larger than its exposed external contact width; and forming plural conductive bumps on the external contact within the opening range of the solder mask layer for connecting an external device, so as to form high-density circuit board with pad-less design.

Description

200410611 V. Description of the invention (1) The field of manufacture is related to a kind of high-density circuit board without pad design and the second one of its design: don't be related to it- a kind of pads used in the electronics product group The bifurcation degree circuit board and its manufacturing method. . ,,, Α before and after jg = electronic products on the market should be light, thin, short, and board, put in the Zixi band with Γ count, in a limited area semiconductor substrate H. more than 70 electronics; in In the design of the circuit board, special 5 and 4 packages of the above-mentioned IC chips are connected to the flip-chip package substrate, general BGA package: or used to connect semiconductor chip packages, light-emitting components, and even; in another: circuit boards, or Other components of the circuit board, also in a limited area, put higher density circuit traces. autumn

In the design of the road, the design of its external contacts has become an important factor in the density of the road. w 丄 I Please refer to Figure 1, which is based on a conventional flip-chip package substrate. The design of Λ1 " outside, such as the density of the circuit traces, limits it. In FIG. 1, the bonding pad 112 is an external contact of the external circuit η0, and its diameter is 2 to 10 times larger than the width W of the external circuit 110, which generally results in a line pitch between the outer and middle wires 114. Restrictions of the pad 112 prevent short circuits between adjacent lines. The wire spacing between the wires in the external circuit 11 () must be greater than the wire, 14 line width, and pad diameter. (W + RJ half and one half. When designing the circuit pitch greater than 18 ^ ^ ^ 'has not caused much impact; but when designing, for example, a flip-chip package substrate circuit board, the contacts of the jc chip to which it is connected Spacing is often less than

200410611

π ’often because of the limitation of the diameter of the solder pad 112, it is not possible to increase the unit size by reducing the line spacing between the wires 114 in 110 =. In the case of density, you can only increase the flip-chip package substrate! . The area of the wiring board within the product line is 10 ° to accommodate the required wiring, f ..., and finally the size of the finished product is reduced. And in other electrical: ^: Γ, for example, general MA packaging substrate, or used to connect half-body chip package, light emitting element #, connector, passive element, and other :: inside: the circuit of other components Board 'also encountered the same problem. In view of this, the main purpose of the present invention is to provide a non-padding circuit board with south density. When designing the wiring of the circuit, the above-mentioned factors of pad size are eliminated, and the circuit layer of the circuit board can not be increased. Number or surface area ^ In the same-layer circuit, a larger number of circuits can be accommodated to reduce the thickness, surface area, and manufacturing cost of the high-density circuit board described above, and can help reduce the size of the final product. Another object of the present invention is to provide a method for manufacturing a high-density circuit board without a pad design. It does not increase the number of circuit layers or the surface area of the circuit board, and accommodates more circuits in the same layer of circuits. The number of circuits can reduce the thickness, surface area and manufacturing cost of the high-density circuit board, and can help reduce the final product size. In order to achieve the above-mentioned object of the present invention, the present invention provides a solderless pad 5 and a south-density circuit board including a circuit board substrate, and one surface of the circuit board substrate is a dielectric layer; External circuit

ZUU410611 Description of the invention (3) The width of the upper contact of the electrical layer ^ ^ 1 The line includes a plurality of external contacts, and the line width of the external circuit on the dielectric layer i; a solder resist layer, a cover layer Opening, warm second description of the external circuit, the solder mask has a plurality of solder masks not less than the exposed mask.卩 Contacts, the diameter of the above solder mask openings are bumps, respectively, to report the width of each external contact; and a plurality of conductive conductors, for the second fish: the above external contacts within the opening range of 2 solder masks Click on this, outside. The files form an electrical connection. Method, the manufacturing surface of a high-density circuit board including a padless design is-a dielectric axe ::: a circuit board substrate, the above-mentioned circuit board substrate-the expression external circuit package 'plurality = is formed on a dielectric layer An external circuit is not larger than the external contact of the external contact, and the width of the external contact Γ line forms a solder resist layer, covering the above-mentioned external circuit, which is exposed on the external circuit and exposed to the above. The external connection #, θ, there are a plurality of solder mask openings ^ Η ^ bu 卩 contact 'the above-mentioned solder mask openings S, π, it is easy to describe and its ..., characteristics, and advantages can be more The following is a detailed description of the preferred embodiments with the following pi +, and the detailed description is as follows: The drawings of the children's mouth, detailed implementation The following is a flip-chip package substrate as an example. , · Describe the characteristics of the present invention and the general de-packaged substrate, or used to connect the semiconductor

200410611

Components, connectors, and passive component boards are designed for application; Ming :::: The electrical product, low-thickness output, high soul-loss of board or other components is designed and manufactured with low area and low area. 7 sub-degree circuit board with circuit density. First embodiment: Please refer to Figures 2A ~ 2C. 仫 u00 ^ ^. Yf ^ is a cross-sectional view to illustrate the principle; for example, the high-density pad design of a flip-chip package substrate method. In the present invention, a circuit without a solder pad can be designed. Ί The circuit of the circuit board with a high degree of stiffness. Zhai Geng 仏 10 1 degree of ice ridge, and a conductive bump is formed on the external contact.

The block replaces the function of 4ΐτ Λ. L · JJU Babai Lizijia fresh pad in the provincial technology. It is used to connect an external component with a pin or a bump. It includes the following steps: Referring to FIG. 2A, an external circuit 210 is formed on the circuit board substrate 25. The external circuit 21 has a plurality of conductive lines (formed as "111") 214, and the external contact point 212 is usually located at the -end of the conductive line 214 to form an electrical connection with an external component, and is suitable for the first embodiment of the present invention. The external components of the flip-chip package substrate 200々 may be an IC chip, a circuit board, or a passive component. In the first embodiment of the present invention, the external contacts 212 are in a first application comparative example described later. An electrical connection is formed with an IC chip (refer to FIG. 3B); and the external contact 212 of the present invention is characterized in that its width is not greater than the line width of the wire 2 1 4. Therefore, the external line 2 1 0 The distance between the wires 2 j 4 can be reduced to a minimum of about 60m. The material of the external circuit 210 is usually copper, and the formation method can be as follows: a surface of the circuit board substrate 250 and a copper foil (not (Illustrated in the drawing)

200410611

The above-mentioned copper foil is etched again to form the desired external circuit 21; one surface of the substrate of the circuit board 250 is subjected to a suitable masking physical vapor deposition method such as sputtering, and the steel is atomically shaped = Circuit board substrate 25G 'Form external circuit; remove / remove the shape cover Step 2 "B picture'" Cover the circuit board base with solder mask 22 by screen printing or spin coating 70 Material 25 〇 and the external circuit 2 丨 0; and then apply a pre-cure measures to partially harden the solder mask layer 22; and then by way of exposure development, the solder mask 220 forms a solder mask opening 222, The exposed part contact 212 & is then subjected to a baking step, saying that the solder resist layer 22 is completely hardened. The role of the solder resist layer 220 is to protect the wire 214 from being contaminated by solder during subsequent processes and to bridge with other neighboring wires 214. The occurrence of a short circuit also protects the wires 2 14 from electromigration during the storage or use of the flip-chip package substrate 2000, and bridges with other neighboring wires 214 to cause a short circuit. The direct control of the opening 2 2 2 is usually not less than the width of the external contact 21 2 'The width of the external contact 21 2 is 1 to 2 times to 2 times as large, and it is preferable that the external contact 21 2 is fully exposed. Step 3 refers to Figure 2C.' Contact 2 1 2 'The electroless plating method is used to immerse the flip-chip package substrate 2000 in an electroless plating solution containing the components of the conductive bump 230 on the clock (not shown in the figure).

rif02-8994TW (nl); 91P61; Dwwang.ptd page 9 200410611 V. In the description of the invention (6), a conductive bump 23 is formed on the external contact 212 to replace the function of the pad in the conventional technology. The height of the conductive bump 230 is not higher than the solder resist layer 220, so as to facilitate the bonding with the IC chip with the flip-chip bump formed in the subsequent packaging process. The conductive bumps 2 30 can be made of copper, gold-plated nickel, tin-lead alloy, or tin-based alloys that do not contain lead. In addition, if the flip-chip package substrate 2000 is a laminated circuit board with more than two layers of circuits, the circuit board substrate 250 is a laminated circuit substrate with a dielectric layer on one surface, and the external circuit 2 is formed in step 1.丨 〇 Before, a plurality of via holes (via h0ie) (not shown in the drawing) must be formed on the dielectric layer and a material is formed on the via hole by a physical vapor deposition method such as sputtering. It is preferably a metal layer of copper. After the external circuit 21o is formed, the other end of the conductive wire 21 4 may be connected to the laminated circuit in the circuit board substrate 250 to form a circuit. The foregoing is a conventional technique and is not related to the features of the present invention, so it is only briefly described after the steps of the first embodiment of the present invention. If the flip-chip package substrate 2000 is a circuit board with one layer of circuit, the circuit board substrate 250 is a dielectric layer, and the other end of the wire 214 usually becomes another form of external contact (not shown in the figure) ), Usually with different external components ^ 212 to connect different external components, and after completing the above three steps, still includes forming a plurality of openings on the other surface of the circuit board substrate 250 to expose the above external contacts 2 1 2 Another form of external contact that connects different external components. The foregoing is a conventional technique and is not related to the features of the present invention ', so it is only briefly described after the steps of the first embodiment of the present invention.

200410611

Figure Λ 3A of the flip-chip package substrate 300 and ㈣ = are both designed to be the same as the flip-chip package substrate with flip-chip bumps 12 star right Γ = ° δ. A circuit board designed by soldering; and the flip-chip package substrate 200 is a high-density circuit board designed as a flip-chip package substrate without a pad in the first embodiment of the present invention. Comparing the flip-chip package substrate 300 with the flip-chip package substrate 2000: The flip-chip package substrate 200 has a padless external contact 212, and two wires 214 can be allowed to pass between the external contact 212 in FIG. 3b The flip-chip package substrate 300 has solder pads 312 having a diameter larger than the line width of the wires 314. In the μ diagram, the solder pads 312 have the same pitch as the external contacts 212 in FIG. 3B, and can only accommodate one pad. The lead 314 passes; therefore, the flip-chip package substrate 200 can have a smaller number of circuit layers or surface area due to its larger circuit density. It is conducive to the reduction of the volume of the final product of the post-production. In the case of increasing the number of circuit layers or surface area of the circuit board, in the same-layer circuit, the number of circuits is increased to reduce the thickness, surface area and manufacturing cost of the high-density circuit board, and can help the final product size Reduction. " In addition, after the flip-chip package substrate 300 in FIG. 3A is combined with the IC chip 10, the design of the large solder pad 312 is large. After the flip-chip bump 12 is combined, its height decreases and its width increases. , Which increases the risk of short-circuiting due to bridging of adjacent flip-chip bumps 12. Not only in the application of flip-chip packaging substrates, but also in other fields ’, for example, to connect semiconductor chip packages and light-emitting devices.

200410611 V. Description of the invention (8), connector, passive 7L piece, another circuit board, or other, on the circuit board connecting 2 of the above-mentioned external components to be connected, the above-mentioned addition of the adjacent flip-chip bump 12 bridges and It happened like a problem. In particular, the application of the flip-chip package substrate i :::: must be performed in the same process as the flip-chip package substrates 300 and 1 (under chip 11); The increase in the base rubber degree, the thinker in the process of filling the bottom glue in the bottom glue flow / and see the system caused the bottom filling # process time extension with & = reduce the risk of void. In FIG. 3B, the first embodiment of the present invention is a high-density circuit board with a padless design of 200? The external contact 212 and the bump 23 which replaces the function of the fresh pad are combined. What is the height and width of the rear flip-chip bump 12 = to 1: the chip 2 7 The risk of short-circuit of the neighboring flip-chip bump 12 due to bridging ?: In the application of mounting substrates, in other # # Encapsulation chip package, light emitting element; cattle ;; quilt: such as: to connect semiconductor or other components on the circuit board, after m? Pieces, * -circuit board components, also reduces the number of connections to be connected as described above (External ^ ^ ^) As above, the adjacent flip-chip bumps 1 and 2 are bridged and S occurs because of ί Ϊ ::: Ϊ problem. Especially in flip-chip sealing The height and width of the application of the substrate are hardly affected. There is enough space between the mounting substrates 20 0 and 1 (; wafer J 〇) to fill the bottom knee k for the primer to flow, which can reduce the filling. The processing time of the primer can also reduce the wind & that occurs in the cavity of the primer. The above-mentioned southern rush-free circuit board of the present invention is designed without increasing the number of circuit layers or surface area of the circuit board.

200410611

In the case of the same, reducing the above-mentioned high-density electricity can help the final product with additional advantages. In the layered circuit, the thickness of the circuit board and the reduction in surface size are accommodated. In addition, the number of circuits is larger, in order to increase product and manufacturing costs, and can be the first consistent example provided by the industry. Please refer to Section 4A The ~ 4D figure is prepared, and the second embodiment of the invention is a cross-sectional view of the second embodiment, which is used to explain this method. The invention can adopt the design of a fresh pad, the density of the road, and an external element of a conductive conductive block formed on the external contact. The work of 用以 is used to connect-no pins or convex U. The flip-chip package substrate 40 of the second embodiment, step 1 and step 2 and the above-mentioned first embodiment ㈣, so here please refer to the above-mentioned first paragraph of the present invention ―Steps of the Example-Explanation of Panniu Step 2 and 2A ~ 2B. Step by step ^ Please refer to Figures 4A to 4C. In accordance with the above-mentioned padless design, the conductive bump 43 is formed on the external #point 412 in accordance with the 1/2 / two-ore method. Come to the function of the welding pad in the known technology. The above The electric money method also includes the following sub-steps. Please refer to Section 4A ^, Forming-a conductive metal layer 440, which covers = :: 420, P square welding layer openings 422, and external contacts 412. The metal layer can be formed in the following manner: This is a physical vapor deposition method such as a sputtering chain method.

200410611 V. Description of the invention (10) (2) Please refer to FIG. 4B to form a resist layer 460. After covering the metal layer, pattern the resist layer 460 to form a resist layer opening 462 to expose and cover the solder resist. Layer opening 422 and the metal layer 440 on the external contact 412 'then placing the flip-chip package substrate 400 in a plating solution (not shown in the drawing)' and energizing the metal layer 4 40 to conduct the conductive bumps 430 is plated on the external contacts 4 12. (3) Please refer to FIG. 4C to remove the resist layer 460 and the metal layer 440 covering the solder resist layer 420. The height of a conductive bump 430 is higher than the solder mask 420, and the same degree of the conductive bump 43 is preferably higher than the thickness of the solder mask 420 by 20 to 60 vm so as to facilitate the subsequent packaging process. In combination with IC chip without flip-chip bumps. The material of the conductive bump 430 may be copper, gold, tin-lead alloy, or tin-based alloy. : ¾ No 3 milk, please refer to Figure 4D. If the material of the conductive bump 430 is copper or gold, in order to help the magic process of re-soldering after connecting with the IC chip without flip-chip bumps, hot dip plating, spray coating can be used. Attach, electroplating, etc., the metal sound 432 = on the surface. The material of the metal layer 432 is tin-lead gold or tin-based alloy without 3 lead. In addition, the above-mentioned hot dip plating method is to immerse the conductive bump 430 in a tin-lead alloy or lead-free tin-based alloy to form a metal layer 432 on the surface of the conductive bump 430; and spray: Formula 1 is a method in which a molten tin of a tin-lead alloy or a tin-based alloy containing no lead is sprayed on the surface of the conductive bump 430 to form a metal layer 432. The plating method is implemented in the above (2). Eight are incorporated. However, if the material of the conductive bump 43 0 is only steel or gold, you can use .Q702-8994TWF (nl); 91P61; Dwwang.ptd Page 14 200410611 V. Description of the invention (11) A conductive In the manufacturing process of the adhesive, the flip-chip package substrate 400 can be connected to the IC chip without the flip-chip bump without re-soldering. This portion will be described in a second application comparative example described later. In addition, the case of the flip-chip package substrate 400 can also be a laminated circuit board with more than two layers of circuits or a circuit board with one layer of circuits, as described after step 3 of the first embodiment above, here Also omitted. Second application comparative example: Please refer to FIG. 3A and FIGS. 5A to 5C. The flip-chip package substrate 3 0 0 of FIG. 3A is also designed to be combined with an IC chip 1 with flip-chip bumps 2 The flip-chip package substrate 400 shown in Figures 5A to 5C is the same as the flip-chip package substrate designed to be combined with the {c-chip 2o without the flip-chip bumps; 1C chip 1〇 The difference between the 1C chip 20 and the presence or absence of the flip-chip bumps 12 is that they are IC chips with the same design and function. The flip-chip package substrate 300 is a circuit board having a pad design as shown in FIG. 1; and the flip-chip package substrate 400 is a padless design of the flip-chip package substrate according to the second embodiment of the present invention described above. High density circuit board. Compare the flip-chip package substrate 300 with the flip-chip package substrate 400. The flip-chip package substrate 400 has a padless external contact 412 between the 5A to 5 (: external contact 41 2 in the figure) Two wires 414 are allowed to pass through; the flip-chip package substrate 300 has pads 3 1 2 having a diameter larger than the wire 3 14 of the respective wires. In FIG. 3A, the pads 3 12 have the same outer dimensions as those in FIGS. 5A to 5C. The contacts 412 have the same pitch and can only accommodate one wire 3 丨 4 to pass through. Therefore, the flip-chip substrate 400 can have a smaller number of circuit layers due to its larger circuit density.

200410611 V. Description of the invention (12) or surface area is beneficial to the reduction of the volume of the final product of the post-production, which is the cost of the invention "without increasing the number of circuit layers or surface area of the circuit board, in the circuit of the same layer, To accommodate a larger number of circuits in order to reduce the thickness, surface area, and manufacturing cost of the above-mentioned highly inspected circuit board, and to help reduce the size of the final product ". Please refer to FIGS. 5A to 5C. The second embodiment of the present invention is a flip-chip package substrate of a solderless design high-density circuit board having a conductive bump 4 30 which is higher than the solder mask layer 420. The external component IC wafer 20 can directly form an electrical connection with the flip-chip package substrate 400 without a bump forming process. However, not only in the application of flip-chip packaging substrates, but also in other fields, such as a circuit board that is used to connect a semiconductor chip package, a light-emitting element, connection = passive element, another circuit board, or other external components. The above-mentioned external components can be skipped to form a pin such as a ball, etc. to form an electrical connection with the areal density circuit board. This can reduce the manufacturing steps of i or the assembly of electronic products, not only shortening, 'θ plus output, and in the case of reducing one process step and reducing the risk of yield reduction once, f can be produced into a too. i ^ can also increase the process yield and reduce production. Additional advantages. Due to the combination of the flip-chip package substrate 3 00 and the IC chip 10, the design of the pad 312, the flip-chip bump 12 increases in degree after the bonding, and the neighboring flip-chip bump 12 bridges his In the field, for example, ^-, connection cry, # 述 _ μ Japanese film package, light-emitting element connection ... leather moving parts, another circuit board, or circuit board of other components 1: JQ702- 8994TW (nl); 91P61 ; Dwwang ptd Page 16 200410611 V. Description of the Invention (13)

Ten: After connecting the external components to be connected as described above, increase the neighboring flip-chip bumps as described above, such as R pps. The risk of a short circuit occurring when 1 block is bridged to 2 is the same. Second tone J: Application in flip chip packaging substrate i, in subsequent packaging (unde; π Π 3 0 1 C ^ 1 〇 ^ ^ ^ Λ, Clothing, and the above-mentioned flip-chip bumps 12 decrease in height and width: 4 ^ increase, which means that in the process of filling the bottom of the glue to reduce the flow of the primer is caused by the extension of the filling process and increase the occurrence of primer The risk of void. However, the high-density circuit board with a padless design as the mounting substrate 400 in the second embodiment of the present invention in FIGS. 5A to 5C has external contacts without a solderless design 41 2 and the bump 43 instead of the solder pad function. After the combination of Ic and 20, the height and width of the conductive bump 43 will be hardly affected by the difference. The adjacent conductive bump 43 is reduced due to bridging. The risk of a short circuit. ^ In the application of flip-chip packaging substrates, in other areas, such as circuits used to connect semiconductor chip packages, light-emitting components, connectors, passive components, another circuit board, or other components On the board, after connecting the external components to be connected as described above, The same problem as the risk of short-circuiting of the adjacent conductive bumps 43 bridged as described above is reduced. Especially in the application of the flip-chip package substrate, it can be adjusted by 09 in the process of the flip-chip package substrate 40 () "Guide" the height and width of the electric bumps 430, so that when filling the primer process, there is enough space between the package substrate 400 and the 1C chip 20 for the primer to flow when the primer is filled, Not only can reduce the process time of primer filling, but also reduce the risk of occurrence of primer voids. The above-mentioned high-density circuit board of the present invention is designed without increasing the number of circuit layers or surface area of the circuit board.

9] p2-8994TW (nl); 91P61; Dwwang.ptd 200410611 V. Description of the invention (14) In the case of 'in the same layer of the circuit, accommodate more circuits in order to reduce the thickness and surface area of the above-mentioned high-density circuit board And manufacturing costs, and can help reduce the size of the final product, "in addition to providing advantages for the industry. 'In addition, in FIG. 5A, when the material of the conductive bump 43o is copper or gold, when the flip-chip package substrate 4o () and 1 (: wafer 20 are bonded), the screen can be used. After a conductive paste 30 is formed on the conductive bump 430 in a screen print or dipping manner, the flip-chip package substrate 400 is directly formed with 1 (: wafer 20) through a conventional reflow soldering process. In the case of FIG. 5B, in the case that the material of the conductive bump 43o is copper or gold, if the flip-chip is to be sealed by the traditional re-soldering process, the mounting substrate 400 may be placed in The conductive bumps are formed at 43 °-the material is tin fault: ί, not 3 wrong tin-based alloy metal layer 432, and then the board 400 and the 1C wafer 20 are electrically connected through a reflow process; the material is tin Wrong alloy or if-shaped without fault = base π can form an electrical connection directly by re-soldering wafer 20. Although autumn: =: said package substrate 400 and 1C high-density circuit boards are covered Crystal Seal =: This Ming Ming pad is designed to be used in other fields: J Semi = concept can also be a circuit board. Another circuit board, or other Although the invention has to be limiting of the present invention, any of those skilled in this;} Γ away; it is not used and the range, can be made to run a little of: no = 0702.8994TW (nl); 91P61; Dwwang.

Ptd Page 18 200410611 V. Description of Invention (15) The scope shall be determined by the scope of the attached patent application. ill ·! Page 19 0702-8994TWF (nl); 91P61; Dwwang.ptd 200410611 Illustration of the diagram is simple The first picture is a top view, which is based on one system. /. The density of circuit traces is limited. Figures 2A to 2C show a series of sections w. Using the example as a flip-chip package substrate, the method of the present invention is described. The circuit board and the 3A ~ 3B diagrams are shown in a series of cross-sectional views. Application: The solderless pads used as flip-chip package substrates are clear-a traditional flip-chip package substrate. The 4D and 4D drawings of the circuit board and the circuit board are a series of cross-sectional views. The solderless pad as the flip-chip package substrate of the second embodiment is shown in FIG. 3A-a conventional flip-chip package substrate. -Description of circuit board and symbols 10, 20 ~ 1C chip 30 ~ Conductive glue 100'200 ~ 300 110 > 210 \ 310 112, 212 ~ 312 114, 214, 314 120 ^ 22 0 ^ 320 122 > 22 2 ^ 322 on τη 〇ti 12 ~ Flip-chip bump 4〇〇 ~ Flip-chip package substrate 41 0 ~ External wiring 41 2 ~ Pad 41 4 ~ Wire 42 0 ~ Solder mask 422 ~ Seal mask opening

Page 20 200410611 Brief description of drawings 23 0, 43 0 to conductive bumps 25 0, 35 0, 45 0 to circuit board substrate 4 4 0 to metal layer 4 3 2 to metal layer

, ¢ 702 -89941HVF (η 1); 91P61; Dwwang. P td p.21

Claims (1)

200410611 VI. Application Patent Scope 1. A high-density circuit board without pad design, including at least: a circuit board substrate, one surface of the circuit board substrate is dielectric; a negative layer and an external circuit are formed in the On the dielectric layer, the external circuit has a plurality of external contacts, and the widths of the external contacts are not large. 含 Including the line width of the circuit; Γ 4 wires and a solder mask covering the dielectric layer With the external circuit, the solder reed has a plurality of solder resist openings, exposing the external contacts, and the diameters of the solder resist ^ openings are not less than the & degrees of the exposed external contacts, respectively; and The two ghosts are: formed in the solder mask openings, and connected to an external component. • The high-density households without pad design as described in item 1 of the scope of the patent application, wherein the diameters of the openings of these solder mask layers are respectively 1 to 2 times to 2 times the width of the exposed "external contacts. The 3 For example, please contact the high-density customer with a padless design as described in the patent scope μ. The distance between external circuits is not less than 60 °. And the circuit board 13: a high-density circuit with a padless design as described in item 1 Board, wherein the substrate of the circuit board is damaged ^ a laminated circuit substrate, the dielectric; a surface of the dielectric layer 5. If an application is made ㈣ a circuit board, wherein the external component item is returned without a solder pad Designed high-density R ^ from 4W for + conductor wafer. 6 · For example, the scope of the patent application No. 1 a circuit board, where the external component to the small density of the padless design 丨 Vulture at least includes: semiconductor wafer 、 Semiconductor: -5702-8994TWF (nl); 91P61; Dwwang.ptd 200410611 ~-" " " `` I VI. Patent application scope: package, light-emitting component, connector, passive component, or other-circuit 7 . As described in item 1 of the patent application, the soldering heat # leaf of the circuit Board, in which the conductive bumps. ,,, # MAT6 are counted between the costs 8. As in the scope of the patent application item i: What is the formula \ no electricity + electricity money. Circuit boards, ... some conductive bumps The formation method of the block is the high density of the electric device 2. The solderless pad as described in item 7 of the scope of the patent application ^ ^ $ circuit board, in which the material of the conductive bumps 1 is recorded, tin-lead alloy, or Tin-based alloys that do not contain lead ...., gold-plated 10. The solderless installation as described in item 7 of the scope of the patent application ~ circuit board, where the conductive bumps are ancient. No less than the thickness of the solder mask layer. Therefore, the high-density output of the padless design as described in item 8 of the patent application scope =, where the material of the conductive bumps is selected from: copper, copper, copper Copper, *, tin-coated tin-free alloys with no wrong tin-based alloys: wrong tin-based alloys. Gold-based gold, tin-coated alloys' or no 12. No solder pads as described in item 8 of the scope of patent applications Designed high-density circuit board, where the height of the conductive bumps is higher than the thickness of the solder resist layer 20 // m ～ 60 fim 〇13 · —A solderless installation A method for producing high-density circuit board, comprises: providing a circuit board substrate, a surface of the circuit board substrate-dielectric layer, P. 23, 0702-8994TWF (η1); 91P61; Dwwang.p td 200410611 The external contacts within the opening range are respectively formed with a plurality of conductive bumps on the solder resist layers. 14 · The method for manufacturing a high-density circuit board without a pad design as described in item 13 of the scope of the patent application, wherein the diameters of the solder resist openings are respectively the width of the exposed external contacts 丨 · 2 times to 2 times. 1 5 · The method for manufacturing a high-density circuit board without a pad design as described in item 丨 3 of the scope of patent application, wherein the distance between the external circuits is not less than 60 " m 〇1 6 · If the scope of patent application The high-density circuit board of the padless design according to item 13, wherein the substrate of the circuit board is selected from a laminated circuit substrate whose surface is the dielectric layer, and a circuit composed of the dielectric layer. Board substrate. 17 • The method for manufacturing a high-density circuit board with a padless design as described in item 13 of the scope of the patent application, wherein the conductive bumps are formed by electroless plating. 18 · The method for manufacturing a non-fresh design-oriented directional density circuit board as described in item 13 of the scope of patent application, wherein the conductive bumps are formed by electroplating. .〇07〇2-8994TWF (nl); 91P61; D ^ ang.Ptd 200410611 19. The method of manufacturing a high-density circuit board without a pad design as described in item 17 of the scope of the patent application, wherein the material of the conductive bumps is selected from: copper, gold-on-chain nickel, tin-lead alloy, or Lead-free tin-based alloy. 20 • The method for manufacturing a high-density circuit board with a padless design as described in item 17 of the scope of the patent application, wherein the height of the conductive bumps is not higher than the thickness of the anti-frying layer. ° 2 1 · The method for manufacturing a high-density circuit board with a padless design as described in item 18 of the scope of the patent application, wherein the conductive bumps are formed in a more 'inclusive' manner: a conductive metal layer is formed to cover On the solder resist layer, the solder resist openings and the external contacts; '9 forming a resist layer covering the conductive metal layer; patterning the resist layer, exposing and covering the resist layer The solder resist opening and the conductive metal layer on the external contacts; the substrate of the circuit board is placed in a plating solution, the conductive metal layer is energized, and the conductive bumps are plated on the conductive bumps. External contacts; and removing the resist layer and the conductive layer overlying the solder mask. Metal 22 · The method for manufacturing a high-density circuit board without a pad design as described in item 18 of the scope of the patent application, wherein the materials of the conductive bumps are selected from copper, copper-plated tin-lead alloy, and copper-plated Lead-free tin-based alloy steel, gold, tin-based alloy gold, μ-plated tin-based alloy μμ witch, gold kick alloy, or lead-free tin-based alloy . 2 3 · Padless design as described in item 18 of the scope of patent application ^ 200410611 _iimi surface 1-VI. Patent application scope 3 Manufacturing methods ... The height of the conductive bumps is higher than the anti-J 7 hand _ ~ 60 // m. The reported high-density circuit board without solder pads is suitable for forming an electrical connection with an external component that has been formed into a foot or a bump, and includes at least: a circuit board substrate, one surface of the circuit board substrate is a The multiple dielectric layer = material path is formed on the material circuit. The material circuit includes an external contact, and the width of the external contacts is not greater than the line width of the external circuit. Covering the dielectric layer and the external circuit, the solder mask has a plurality of solder mask openings, exposing the external contacts, and the direct control of the solder mask openings is not less than the exposed external contacts, respectively. The width of the metal bumps; and a plurality of metal bumps formed by electroless plating on the external contacts within the solder mask layer, respectively, and the height of the metal bumps is not higher than the solder mask layer. thickness of. 2 5 · The high-density circuit board with a padless design as described in item 24 of the scope of the patent application, wherein the diameters of the openings of the solder resist layers are each 1 · 2 times the width of the exposed external contacts. ~2 times. 26. The high-density circuit board with a padless design as described in item 24 of the scope of the patent application, wherein the distance between the external circuits is not less than 60 v m. 2 7 · The high-density circuit board with a padless design as described in item 24 of the scope of the patent application, wherein the circuit board substrate is selected from a laminated circuit substrate with a dielectric layer on one surface, A circuit board substrate composed of a dielectric layer. Page 26 and 7〇2-8994TWF (η 1); 91P61; Dwwang. Ptd 200410611 VI. Patent Application Scope 2 8 · High-density circuit board with no fresh design as described in item 24 of the patent application scope ' The external component includes at least a semiconductor wafer, a semiconductor wafer package, a light emitting device, a connector, a passive device, or another circuit board. 2 9 · The high-density circuit-free design of the high-density circuit board as described in item 24 of the patent application, where the material of the metal bumps is selected from the group consisting of: copper, gold-plated nickel, tin-lead alloy, Or lead-free tin-based alloys. 30 · —A high-density circuit board without a pad design, suitable for forming an electrical connection with an external component without pins or bumps, including at least a circuit board substrate, the circuit board substrate One surface of is a plurality of dielectric layers, formed on the dielectric layer-a plurality of external points, and the line width of the external path;宽度 The width of the contact is not greater than the outer surface of a shield. The layer 'covers the dielectric sound blood and travels to the right IHr I day, said one outer 4 lines' The solder sound has a plurality of solder mask openings The diameters of the openings of the & Γ layer are not less than the exposed diameters: point j, the width of the external solder joint and the external contact points of 7 Gonglu; with a plurality of metal bumps, the points are separated by electroplating. The external contacts within the range are formed by the thickness of the solder mask opening solder mask 20 # ^ 60. ~ The height of some metal bumps is higher than the 3 1 · For example, the circuit board of the 30th degree of the scope of patent application, wherein the openings of the solder resist layer-the design of the pad-free high density of the width of the external contact 丨 · 2 Times to 2 times. , Diameters are each of the exposed 200410611 VI. Scope of Patent Application ---- 32. The high-density circuit board with padless design as described in item 30 of the patent application park, where the distance between the external lines is not less than 6 0 // m. 33. The high-density circuit board with a padless design as described in item 30 of the scope of the patent application, wherein the substrate of the circuit board is selected from a laminated circuit substrate with a dielectric layer on one surface, Circuit board substrate consisting of multiple layers. 34. A high-density circuit board with a padless design as described in item 30 of the scope of patent application, wherein the external components include at least: a semiconductor wafer, a semiconductor chip package, a light-emitting component, a connector, or a passive component. 35. The high-density circuit board with solderless design as described in item 3Q of the scope of patent application, wherein the material of the conductive bumps is selected from: copper, copper plated with tin boat alloy, lead-free on the clock Copper, gold of tin-based alloys, gold of tin-based alloys, gold-plated tin-based alloys without lead, tin-lead alloys, or tin-based alloys without faults. _.07p2-8994TWF (nl); 91P61; Dwwang. Ptd page 28