TW200410320A - An ultra-shallow junction formation by amorphous silicon/silicon dioxide stacked structure for nano MOS device fabrication - Google Patents

Abstract

The present invention provides a new ultra-shallow junction formation method for nano-MOS technology applications by using conventional ion implantation and rapid thermal annealing techniques without requirement of low energy implant equipments to fabricate ultra-shallow junctions. Diffusion from implanted amorphous silicon (DIA) is performed by junction implant through an amorphous capping layer; the amorphous layer thus acts as a surface solid diffusion source during annealing. A thin oxide is deposited to serve as etching stop layer beneath the amorphous layer. This bilayer amorphous-oxide structure enables easy removal of the amorphous layer and provides good process control and device reliability. By using amorphous silicon layer as the diffusion source for junction formation, implant defects are reduced. Defect-free ultra-shallow junctions can be formed.

Description

200410320 V. Description of the invention (l) Field of the invention • The present invention relates to the manufacturing process of standard complementary metal-oxide-semiconductor (CM0SFET), especially to a method for forming an ultra-shallow junction in nano-scale M0S technology. BACKGROUND OF THE INVENTION—The 1C manufacturing industry must continue to shrink MOSFET devices to increase the density and speed of digital ICs. Reducing the length and width of component channels can increase the density of ICs, and the saturation drain current of MOSFETs must be increased to achieve faster speeds. The technological improvements in the past 35 years are in accordance with rMore's law, which means that the number of transistors on the wafer doubles every three years. However, when the component is shrunk to a gate length less than 1 # m, the M0SFET begins to exhibit some phenomena different from the long channel M0SFET. When the gate length is less than 0.5 m, the drain saturation current Idsat does not increase as the gate length decreases, and a short-channel effect occurs in the element. In very small MOSFETs, IDSAT is not expected to be affected by the gate length. Therefore, when a large MOSFET saturation current is required, reducing the thickness of the θ oxide becomes the most effective way. The current M0S element structure will start to encounter serious problems. Those with a lateral dimension of less than 0 · 0 5 // m need a very thin gate oxide, but the gate oxide cannot be reduced below 1 ~ 1 · 5nm because Electrons can easily penetrate such thin oxides. Moreover, at this size, it is difficult to avoid mutual influence of the pN junction. Innovations in components and manufacturing are bound to continue to appear to reduce the size of integrated circuits and enable technological advancements to exceed international semiconductor technology milestones

200410320 V. Description of the invention (2) (The process used by International Semiconductors CMOS devices produces two main requirements: the on-state and the south-current “off” state. There is also a drain-to-source entry into the source. The key design parameter is to reduce the gate length when “opening”, and a high level of parasitic resistance is needed. It will usually be the main criterion for the junction length.

Technology Roadmap of ITRS). Continuous shrinking poses a series of severe challenges for forming active layers in sub-micron transistors. Reducing the size of the M0SFET suppresses the "off" leakage current, and "turns on the low resistance. When the gate length is extremely small, even if the element reduces the threshold voltage ντ due to the reduced gate length, the leakage current is near the drain The space charge region can also be in the substrate, so that the gate bias cannot control the potential, and then a punch-through phenomenon occurs. The current in the "off" state cannot be reduced because the junction is shallow. In order to reduce the channel resistance of the M0SFET, dopants must be activated when the channel resistance is as small as the source and drain resistance to reduce the electrical activation of the doped atoms implanted in the source / drain and extension regions. The limiting factor of the diffusion cycle. These contradictory arguments are to study the formation of super shallow super shallow junctions: The formation of super shallow junctions has become a strict and ultra-low heat of component shrinkage to limit diffusion. For combat purposes, it is necessary to remove the system loss. , 乂 / Fedor active dopants, and horse-doped and fully activated shallow junctions. The most stringent: the junction depth of "= produced polar extension zone".

V. Description of the invention (3) Must be between 20 and 40 nm. Known method: First, a low-energy ion implantation is applied, followed by an I ^ ACKapid Thermal Annealing (rapid heating annealing) step, and a shallow junction that can be copied is formed. However, the ion implantation technology causes damage to the silicon crystal, so that the annealing must be performed at high temperature, and when the dopant is driven by the diffusion of thorium, instantaneous addition and expansion (TED), accelerated diffusion of boron and accelerated diffusion of oxidation, the Will be subject to the punch-through effect of dopants. There are many strategies such as annealing temperature for f system, reducing heat by pulse annealing, high rise / fall rate, etc. == present and interface, but all are temporary solutions, rapid heating 1 ^ (RTP) still faces the limit of solid solubility Low activation problem. Other methods for manufacturing super shallow junctions: Ion technology uses plasma doping (plasma) and plasma immersion: Plasma doping is better because it is easy to control and source plus acceleration. However, the wafer is Directly placed in the plasma (_, fast and fast gas phase doping *, the original pass is always controlled: the penetration effect of the dopant, first use inactive crystallization, [confirmed that The surface of Shi Xi's surface does not cause the implantation area but the implantation itself will be dislocated. This is high: the damage caused by the amorphous implantation in the form of a gap ring near the amorphous interface is difficult to use V. Explanation of the invention (4) Fire completely eliminates the additional defects. It can also be said that the superficial junction of accelerated diffusion (TED) can also be formed by outward diffusion. The glass (PSG) and boron glass (BSG) Oxides such as phosphorus overcome the above-mentioned problems of ion implantation and the large expansion of the junction depth. N The expansion and discharge usually leads to the chip resistance laser heating treatment (LTP), which was a method, Rl i θ; Substitute dopants to activate RTP can be low and non-uniform. ^ Τρ is still not suitable for production 'because of its capacity Ming Zong Zi Zi Zhi 211 proposed a process for forming junctions, retaining the current separation equipment. The technology of rapid heating annealing, but does not require the use of low-energy diffusion surface 2 amorphous silicon diffusion method (dia) The concept is to form a -tg scattered source, and remove this shielding layer after diffusion. After crystalline silicon I, a thin oxide is used as an etch barrier layer. 1 After depositing non-6i, RTA ^ m ^ implantation method to form a highly doped Amorphous silicon layer. The two layers are removed by wet etching after the subsequent non-metallic junction. This double layer is good: the oxygen-making material of the stone enables the amorphous silicon layer to be easily removed, so Provides JI control and component reliability. 200410320 Invention details The super shallow junction formed by the implanted amorphous silicon diffusion: Please refer to Figure 1, first grow a thin oxide as a barrier layer, and use the ion implantation method A highly doped amorphous silicon layer is formed. In the subsequent RTA step, the dopant diffuses into the underlying silicon layer to form a p-n junction. After the junction is formed, the two layers are removed by wet etching. Controlling the penetration of dopants when implanting through this pre-deposited amorphous silicon layer At the same time, the defects of implanting peaks are also limited to the amorphous silicon layer: Therefore, the transient accelerated diffusion (TED) effect is suppressed, and the result is easy to control. 9: The energy and large dose can be applied to form a highly doped layer. The direction of the ::::::: interface makes the replacement of the material completely active, and it is completely unprofitable. The shielding layer is more jealous than the use of oxides. The difference in diffusibility in the film, The amorphous non-emulsified emulsion has a large diffusion coefficient (3xl0_4cm2 / s). The number of dopants that can enter the junction is two-fold-the reason is the junction with a doping concentration on the Li plane. Diffusion of oxygen-enhanced diffusion, penetration of impurities] 2 :: Dagger, pre-amorphous implantation to reduce edge-containing defects. The implantation itself will cause the implanted area to be near the non-B interface. A gap-shaped annular dislocation region is formed everywhere. 5. Description of the invention on page 9 (6) It is a serious consideration to completely remove the defects caused by ion implantation. The additional defect p A = ^ Leakage ^ Connected to the early ## n 1 卜 的 失It will also enhance the TED effect. The present invention adopts the advantages of the amorphous shielding layer and modifies it. First, the amorphous layer on the surface is used, so it can be approved and requires additional implantation steps. The channel effect of the industrial debris, without the solid 'di' form a fully activated interface that can be replicated, and at the same time, it has no implant damage in Shixi Zhongbei's showing particularly excellent results. System, the two supplementary items of ^ The experiments are as follows', respectively focusing on the application of the interface diffusion machine. (B) the effect of implanting this 1, and (C) the effect of RTA temperature and time on the DIA experimental procedure: the material used to form the super shallow junction is n-type, doped with phosphorus, (100): Silicon wafers with a nominal resistivity of 4 ~ 7D_cm. In a standard RCA clear; ^ 'at a temperature of one or two temperature and air pressure of 1 500 ° C to grow to a thickness of 50,000 Angstroms i%

Active lithography and wet etching techniques are used to form the active area, and a 20 angstrom thick oxide pad is grown with high density plasma chemical vapor deposition (HDPCVD) at h 0 as the rest of the future money engraving of amorphous stone. Blocking layer. Low-pressure chemical vaporization (LPCVD) / earth engraving layer of amorphous stone with a thickness of 500 angstroms, a variety of energies /, BF in Zhili / implanted with amorphous stone Layer, followed by various rta programs. Thereafter, the amorphous polysilicon layer was removed with a conventional polycrystalline silicon etching solution (HN03 + H20 + NH4F), and the thin etch stop layer was removed with BOE (HF: NH4F = 6: 1). Immediately after removing the shielding oxide, the wafer was loaded into a physical vapor deposition system (PVD) and a TaN buffer layer and a 500 Angstrom Al-Si-Cu film were deposited. definition

Page 10 200410320 V. Description of the invention (7) --- A1_Si-Cu is deposited on the back of the wafer at the position of the metal electrode. Figure 2 shows the flow of D I A sample preparation. 1.Experiment A: DIA junction formation mechanism In Experiment A, the implantation energy is 40 keV and a dose of 5 × 10 i5 atoms / cm2 of 卯 2+ dopants. The RTA conditions are shown in Table 1. The RTA conditions are 950 ° (5s, 1050. 5s and 1050 ° C Is · 1 · 1 · Junction Depth and Sheet Resistance RTA and SIMA Samples without RTA are shown in Figure 3 The silicon layer is used to observe the distribution of boron through shielding amorphous silicon, oxide pads, and silicon substrates. The implantation peak before RTA after implantation is controlled to be inside the crystalline silicon, so that defects are confined within the shielding layer. This boron ion The figure shows two discontinuous mass interference effects in the SIMS measurement at the boundary of the oxide (the depth is about 45 followed by 52) 1111. The number of oxide regions cannot be analyzed by y. The precise interface of the oxide is precisely determined. = We can see that if the thickness of the oxide is limited, the thickness of the oxide layer is not affected. The usS1 an pattern shows that an oxide pad will not affect the dopant or the diffusion. The depth of the junction before RTA after implantation was 67.7 nm. The junction depth at rta j was tested under RTA conditions 95 (rc 5s, 105). (rc 5s and 0C Is 疋 72.6nm, 84.2nm and 62.1nm, the surface concentration of the interface is as high as 2xl (P atom / em3, which is close to the solid solubility pole). Comparison of the sample distribution of m samples without RTA after implantation In the previous picture, I can see that a steep connection can be formed with a slope similar to the picture before RTA after implantation.

Page 11 200410320 V. Description of the invention (8)

surface. We assume that the formation of the DI A junction reduces the number of implant defects and the TED effect. It can be seen that the punch-through effect of the dopant still causes the tail of the boron distribution to be explained in comparison with the implantation studies through thin shielding oxides. The implantation through shielding oxides focuses on reducing the punch-through effect, but it has been found that boron atoms will encounter the punch-in effect that is scattered. When the boron atoms pass through the oxide, the nuclear scattering of the amorphous silicon layer expands the angular distribution of the ion beam. Using an oblique implant, the ion beam is initially guided away from the < 1 00 > axis channel, but due to the scattering in the oxide layer, some ions may be directed back to the < 100> axis channel, but with Compared with the direct punch-through effect, this scattering punch-through effect is smaller, and the punch-through effect is greatly reduced by DIA. Table 2 shows the sheet resistance of these samples, about 14 ~ 240Ω / □, which is close to the ideal sheet resistance value of the junction of 60 ~ 80 nm, so a large amount of doping can be added and fully activated. 1. 2. Diffusion mechanism The diffusion mechanism on the DIA interface can also be observed from the SIMS chart in Figure 3. We can see that at a short RTA time (1050 ° C 1 s), the peak of the butterfly pattern shifts to the left. Rather than diffusing inward, the outward diffusion of such dopants is commonly seen when interfacing with RTA. The shielding amorphous silicon thus acts as a cover layer to suppress the amount of dopants that diffuse outward. At low temperature and long RTA time (95 ° F (: 5s sample), the outward diffusion of the implanted peak planting is also visible. However, note that the shape of the boron diagram after “100 ° A”, 95 (TC 5s The sample showed inward diffusion, but the sample at 1050 s and 1 s was not. Therefore, sufficient RTA time is required to overcome the

Page 12 200410320 V. Description of the invention (9) " ----- = ϋ ί scattered, shielded amorphous stone layer is used as a diffusion source, so that the map of # 杂物 diffuses. Under the annealing conditions of 105 (rc 5s), a deep junction is formed by the inward ϊ of the dopants. At a long RTA time i, due to the inward diffusion and outward expansion effects, the The distribution of boron ions is reduced. 1 · 3 · In the summary of experiment a, we conclude that the diffusion mechanism at RTA is the first outward diffusion, while the dopant diffuses from the shielded amorphous silicon layer during the longer RTA. Shielding = The number of impurities that the amorphous silicon layer first serves as a cover layer to suppress outward diffusion «After a long RT A time, the amorphous silicon layer then serves as a diffusion source, and the dopant pattern diffuses inward, This is consistent with the concept of the DIA interface formation method. 2 · Experiment B: The relationship between the DIA interface and the planting energy in the shell test B. The 'BF2 + planting energy is 35keV, 40keV, 45keV, 50keV' agent篁 is 2χΐ 〇i5 atoms / cm2, and the RTA conditions are shown in Table 3. Under different annealing times, the RTA temperature changed from 900 ° C to 100 ° C. 2 · 1 · Junction depth and sheet SIMS diagram of boron before RTA after resistor placement, as shown in Figure 4, showing boron in RTA as shielded amorphous silicon, oxide pads and silicon-based The implantation peak of the implantation is controlled inside the amorphous silicon, so that the defects are limited to the inside of the shielding layer. As predicted, higher implantation energy makes the dopants implanted deeper into the wafer ' Diagram of boron shows two discontinuous points at the oxide boundary

200410320 V. Description of the invention (ίο) (j 罙 degree = 45nm and 57nm), not after the implantation! ^ The previous interface depth can be set to 35keV to 50keV for the implantation at 14.3nm, 23.3nm, 35 9nm and 37 3nm. The peak of the boron concentration on the surface of the silicon substrate or the junction surface is implanted under π "approximately 1X1019 atoms / Cm3" at 45 and 50 keV. The peak of the cloth :: hetero "1 02. Atom / ⑽3. This means that low dopant implantation energy causes the concentration interface to form a low initial interface concentration. The peak value of our results is :: the planting energy * forms a deeper junction depth, but it is much worse than forming a low sheet resistance. • The surface concentration is very high. Left /, will greatly affect the component characteristics. The doped Ξν Eryao 7 2Bie wide BF2 + 40 keV, 45 keV and 50 keV samples are related, dia is followed by 3 sheet resistance and Q / nc m7 between the junction depth and RTA time. It shows a low slice Resistance, for 50keV samples and even <8 00 comparison m junction resistance decreases with increasing RTA temperature and time. less. In fact, it can be seen that the interface resistance also decreases with the increase of the implantation energy. The degree of woodiness depends on the S 1MS measurement, which is shown in Figures 8, 9, and 10 and increases. / Clothing degree should be based on the planting energy, RTA temperature and RTA time

Figure 8, 9 X 1 a I 1 0 0 0 ° c 1 0 'not showing RTA at 900 ° C 25s, 100 ° c 5s, analysis of the SIMS data, which is close to the standard, SIMS measurement The surface and interface facet signals require j. Samples with native oxides will cause spikes in the surface to be filled with oxygen 1 and a stable region. The removal of the surface effect must be normalized by measuring the surface effect = Jiang growth of a surface oxide, where the SIMS diagram is divided by the limit g because of the lack of an oxygen source. The junction depth at the boron concentration of 1018 atoms / cm3 is indicated on the curve description label.

Page 14 200410320 The depth of the surface increases with the implantation energy, and the depth of the interface also increases with the increase of RTA time, as shown in Figures 9 and 10. Higher RTA temperatures also enhance the diffusion of dopants (Figure 8). And 9).… But 'after the sample map with poor RTA conditions with the same implanted energy but with poor RTA conditions', we noticed that the effects of different RT A conditions are not obvious, and the different RTA conditions only cause the junction depth of 5 ~ 1 Onm The difference, the depth of the interface is mainly determined by the initial implantation energy, that is, compared with the effect of humans, the depth of the interface is more strongly affected by the implantation energy. Another side SIMS image of the 5s RTA sample is shown in Figure 11 along with the image before RTA after implantation. To observe the dopant diffusion after RTA, the SIMS surface effect of RTA sample # has not been removed, and the junction depth Similar results were obtained in samples with only 5 10 nm, 9 50 C 2 5 s, and 1000 ° c 10 s after RTA. The boron concentration on the surface decreased by about an order of magnitude, resulting in a surface / chenity of 1 019 atoms / cm1 at 40 keV samples, and a decrease of 45, 50 and 50 keV samples, which fell around Q atoms / cm2. Insufficient dopant concentration has a large sheet resistance and a large leakage current for the sample, but the 45 &amp; 50keV sample has a large peak / cage degree, which is beneficial to the formation of a low sheet resistance junction. . It is also worthwhile to note that the slope of the boron diagram is the same before and after the RTA, which means that the steep junction can be made by the D IA method. Table 4 shows a summary of the junction depths for these different RTAs and implant conditions. ·

Page 15 1 · 2 · ρ + η junction leakage current 2 • Figure 12 and Figure 13 do not show the reverse bias steam leakage current density at the D I Α junction and the cumulative plot of different plant energy I. The measured diode area is 丨 〇 〇χ 丨 〇 〇 200410320 V. Description of the invention (12) V m, the junction leakage current shows a lower wave leakage current with the plant energy office. $ 是 是 面面 的 ’Deeper junction a w w m +% 4 Artificial junction defects are usually located near the wafer surface, so shallow junctions include large but large, &gt; μ α ^ 8 ° points to attack some defect areas. However, when the interface penetrates into the single crystal substrate, the leakage current will increase, and the leakage current will decrease as the interface depth increases. We can predict that the leakage current density of 40 keV should be between 45 and 35 keV, sT7 t method y ^ somewhere, the low leakage current density of 45 keV and 50 keV samples is about 10-7A / cm2, $ Human μ-μ ^ persons are suitable for applications of το pieces. 2 · 3 · Reverse-biased junction bubble leakage characteristics Using a liver 4 156 semiconductor parameter analyzer to measure the current-voltage characteristics of junctions formed by square diodes with DI A ^, measured at different temperatures. Directional current-voltage characteristics (Ir vs. shown in Figure 14. Figure 15 shows a schematic diagram of the junction vapor leakage component in the reverse bias junction. The total reverse current of the two β-body is about the diffusion component of the neutral zone and The sum of the generated currents in the empty region is shown in the following formula: = qADniV (NAx Ld) + qAniW / 2 τ (Equation 1) where Δ is the junction area, D is the diffusion coefficient, ~ is the intrinsic density, and Να Is the party impurity density, Ld is the diffusion length, w is the empty width, and r is the effective lifetime. In Equation 1, 1din is proportional to T3exp (-EA / kT), and Igen is proportional to

Page 16 200410320 V. Description of the invention (13) T3 / 2exp (-EA / 2kT), where Ea is the activation energy. For the diffusion current, Ea is equal to Eg (the energy gap of Si), and for the generation current, &amp; is equal to Eg / 2. The two interfaces, the leakage component A ', the leakage current density (jra) in the interface area, and the leakage current selection (JRP)' in the periphery of the interface can be separated as shown in Figure 16:

L = A x jra + P X JRp + △ I jr = Jra + (P / A) x jRp + A I / A

JrP-JrPI + JrP2

Jrpi: Peripheral current density along the Shi Xi / oxide interface (A / cm)

Jrp2: Peripheral current density (A / cm) along the periphery where A: Junction area (cm2) P: Junction perimeter (cm) jra: Regional current density (A / cm2)

Jrp: Peripheral current density (A / cm) △ 1: System leakage current If the reverse leakage current density is plotted as a function of p / A ratio, the slope is JRP, and the intersection point with the Y axis is Jra, as shown in Figure 17 As shown. We have found this method to be very successful for D 丨 A junctions. Divide the area between 1 0 0x 1 0 0 _, 200x200 _ and 300x3 00 / zm.

When measured in-situ, the reverse junction current of -3 v is determined as the leakage current of its periphery relative to the area ratio map. Figure ^ is the p / A ratio of ^ ⑽ ^ 5s rta sample = ^ implantation energy, implantation defects are usually the most at the implantation peak =, 'usually sin near the surface of the interface, so the defect of the interface leakage is large Part of the crime, the interface around the interface, at the same time, the interface between silicon and oxide also generates interface traps, which become the main leakage path around the plutonium; peripheral effects can be in the p / A ratio

200410320 V. Description of the invention (14) '&quot; When the slope of the P / A ratio graph decreases with the increase of the implantation energy, we can assume that the defect effect on the plantar surface of the 50keV sample is the smallest, = assuming that this is due to the deeper connection of the & It is caused by surface defects, because the defect of the implantation affects the leakage around the interface, in the deeper interface, the proportion of the periphery containing the defect is small. We wish to see the MA method in the more prominent fabrics. ^ ^ ^ Snail 丨 Measure the activation energy in the evening to further verify that both JRA and JRP are diffusion currents. &Amp; Wu Ba Μ τ Α Α generates the sum of currents, so we can analyze JRA and JRP to understand the interface characteristics ^ _ mechanism, so we observe the reverse electricity and 丄 τ to study the correlation between the area and the surrounding current (I / kT), as shown in Figure 19 n ra / T3) and ln (JRP / T3) are not connected to fir y. 囷 9 relative to the measurement. Change temperature from 25 ℃ to j 9 〇t: the reverse junction 'sets the slope of the P + n connection to the Arrhenius diagram at _3V (1 τ / T3 +, $ is the active R of the leakage current density in the region For the 1 / kT) is the activation energy. E (1. 12eV), 抟 a is 9.5 eV, which is close to the defects of silicon, and the diffusion current :: f step does not produce the same slope in the region. At low temperature, FRA. Regarding the peripheral current density, there are two leading JRPs. Because along the Xixi 52eV, nearly E〆2, the state of J in this region has some interface states at the interface where the defect becomes a chemical product. The current is generated here. At lower temperatures, it lowers the activation energy. As a result, the higher activation energy is shown in Table 2. At high temperatures, EA is 1 · 1 3eV, and current becomes the main leakage ^ = Jf2 dominates Λρ in this region. Current, diffusion 0 · 9 5 e V and 1 · 1 3 e ν, original = ,. The slopes of the jrp and jra in the temperature zone are wells existing in the silicon / aircraft 1 because 'for the peripheral current density, There are some trapped emulsions at the interface. The implantation step did not produce a substantial 200410320

V. Description of the Invention (15) Defects. _ △ u not m μ The plot of the current density of the area relative to the back pressure of the Feng parameter. For an ideal junction Jra should not be affected by voltage: = because no defects occur in the area, and the diffusion current The main current is not affected by voltage. However, because the junction is connected in series, the linear relationship between the leakage current and the voltage is seen. Figure 2 丨 shows the graph of the peripheral current density relative to the reverse bias with a parameter of 7 degrees. We can see To JRP is relatively affected by the bias voltage. The Arrhenius diagrams of the area and surrounding leakage currents measured at different voltages are shown in Figures 22 and 23. The calculated area leakage and tongue energy are about 1 eV. At high temperatures dominated by the diffusion current, the surrounding steam leakage is reduced. The Arrhenius diagram shows the activation energy of 1. lev. However, the activity at low temperature decreases with the increase of the reverse voltage. At low bias, heat emission is: the main mechanism of current, but at high bias, the penetration distance is significantly smaller than ^ sheng (d 1 &gt; d2), as shown in Fig. 24, most of the generated current is increased due to a higher punch-through opportunity, so the activation energy is reduced. The predominant mechanism η changes from hair to diffusion at a temperature of about 90 ° C. The graph of the ratio of jRp and JRA versus voltage for different temperatures for a long time is shown in Figure 25. Although JRP and JRA increase with the applied voltage, the Jrp / Jra ratio remains almost the same. No obvious junction leakage. FIG. 26 shows a graph of ln (jR / T3) vs. 1 / kT for different areas of 50 × 50 0 // m, 1000 × 50 0 “claw and 1000 × 1000 // m, the activation energy is almost Maintain approximately the same 1 e V. The temperature at which the dominant mechanism changes from occurrence to diffusion is approximately 90 ~ 100 ° C, and this result is consistent with previous observations.

200410320

2 · 4 · Summary of Experiment B The DIA method can form a shallow and steep junction with a high surface, through non-condensing, low resistance, and good electrical effects, and the implantation of peak defects, impurities, and teeth through

Arrhenius B t ^ ^ may form around the interface. In order to determine and say this product, but the defect is closed, the subsequent experiments will reduce the planting energy to; k: Whether Guangye and planting have 3. Experiment C: The correlation between the DIA interface and the RTA conditions is in Experiment C. Medium, BF, the implantation energy is reduced to 40 keV, the dose atom is wide, and the m conditions are shown in Table 5. The RTA time, temperature, and temperature are shown in the form of reducing the rat flow rate. Variable, this: General: &quot; Fast decline rate affects the junction depth and dopant activation concentration 3 · 1 · junction depth and sheet resistance Figure 27 shows the ρ — η connection after initial implantation and after rta S ^ MS image of boron in the surface, the SIMS surface effect of the RTA sample was not removed, and the junction depth of the 1J junction was 50.5 nm. In experiment C, the out-diffusion mechanism of short RTA time can also be observed at 9 50 ° C, 100 ° C and 105 (TC &lt; 5s samples) to obtain the fRTA time and high RTA temperature to make the dopants diffuse into the substrate. The depth of the junction of these samples is determined by 1018 atoms / cm3. The peak concentration of the dopant is not within the range of 10-9 ~ 1 (P atoms / cm3) as shown in the figure.

200410320 V. Description of the invention (17) The effect of the decline rate on the depth of the joint has been confirmed. A faster decline rate is very effective in suppressing the diffusion of boron and obtaining a high degree of activation, so a shallow and steep joint with a south concentration can be formed. In the rapid heat processing equipment, the wafer is heated immediately by the lamp tube surrounding the chamber, but the cooling of the wafer is determined by the nitrogen flow through the chamber. The decline rate is similar to the cooling rate, which is the rate of the nitrogen scrubber. The commonly used flow rate is 3 sccm. In order to increase the decline rate, the n2 air flow is increased by s5sccm qD1 sample (105t &lt; 5s, N2: 5sccm). The results presented are consistent with other reports, and the steepness of the depth is 40nm. And the peak concentration is equivalent to the initial planting map without RTA treatment.

The junction depth and sheet resistance of Experiment C are summarized in Table 6, and the sheet resistance decreases as the junction depth increases. Although there is no C1 sample (105Q c '&lt; 5s,%: 3sccm) as measured by SIMS, the sheet resistance value can be expected to be around 50nm, so the effect can be confirmed. More evidence of this effect is shown in the following sections. Figure 28 shows the resistance measured by the SSM I50 spreading probe (SRP) and the doping concentration of the nose. The spreading measurement provides an electrical measurement of the activation concentration. When the dopant concentration is formed, only the dopant is electrically activated, which means that it can be measured at the lattice position. Comparing the boron diagram of SIMS with the SRP analysis, you can check the activation of the dopant =, the peak of the chemical concentration (SIMS) of the sample 〇1 (105. 00, ＜ 5 ^ 3 "]) It is about 4xl019 atoms / cm3, and the peak value of the electrical concentration in Figure 28 is also about 4xl (Fatoms / W. Using M㈣ conditions combined with the ma junction formation method can obtain fully activated dopants.

200410320 V. Description of Invention (18)

3 · 2 · P + η junction leakage current Bidirectional bias attack leakage current density vs. different RTA conditions cumulative Figure 29, three RTA temperatures 95 (rc, 100 (rc and 105 = The current density decreases with increasing temperature, and a longer m time also shows = control leakage current, which is consistent with the results in the previous chapters. Deeper junctions show less leakage current. Main considerations for large RTA decline rates It is the consistency of wafer cooling. From the cumulative leakage chart, we can see that the wafer consistency is good, even for D1 RTA conditions. = Cl (105〇C, &lt; 5s, N2: 3sccm) leakage The current is the smallest of the samples in Figure 29. Assuming that the leakage current is affected by the depth of the interface, we can assume that the depth of the interface is deeper than D1, so the effect of the RTA decline rate on the depth of the interface provides further proof. 3 · 3 · Reverse bias junction leakage characteristics Use the HP4 156 semiconductor parameter analyzer to measure the current-voltage characteristics of the junction formed by DIA. The reverse current-voltage characteristics (IR vs. VR) measured at different temperatures ) Is shown in Figure 30. In Figure 31, different faces The three diodes of 500x500 / zm, 1000x500 // m and 1 000x1 00 0 / z ni were measured for the leakage current at the interface, and the graph was plotted as a function of the P / A ratio, showing the p / A ratio and RTA The conditions are irrelevant. This means that the defects in the interface have been reduced, and the p / A effect of the interface is irrelevant. The leakage current in the interface area and the surrounding area will be discussed separately. Analysis of JRA and JRP and perspective of the interface characteristics, D 1 ( 1 0 5 0

Page 22 200410320 V. Description of the invention (19) ° C, &lt; 5s, N2: 5sccm) The activation energy of both samples showed 1.05eV, so it was hardly produced, and the temperature dominated by the diffusion current is now suppressed to The lower implantation energy used in the chamber is 50 ke V to 40 ke V, and the implantation defects are achieved in the cloth. Figures 33 and 34 are again confirmed at the density and the reverse voltage. Almost leakage mechanism. The Arrehnius diagram is shown in Figure 32. JRA and JRP are close to s ^ Eg, that is, the 103e ^ jRp of Jra is defective in the interface area and the surrounding area due to the cloth value. The dominant mechanism is changed from occurrence to diffusion below μ ′ We speculate the result of the removal of all defects. When we implanted the energy from the peak of the implantation, we confirmed that the amorphous silicon layer was completely removed. The area and surrounding current measured at the same temperature, both Jra and JRP are not affected by the reverse voltage, no defects are formed, and the diffusion current is the Arrhenius diagram of the area and surrounding leakage current measured at different voltages. 05 eV。 Figure 35 and Figure 36, the activation energy calculated for regional leakage is about leV, Arrhenius diagram for the surrounding leakage current activation energy is about 1. 05 eV. The ratio of JRP to JRA at different temperatures is shown in Figure 37. It can be seen that it is little affected by temperature or reverse voltage. Therefore, no obvious interface leakage is seen in the D IA interface formation method. Figure 38 shows the plots of ln (JR / T3) vs. 1 / kT in different areas (500x500 // m, 1000x500, and 1 0 0xl 000 // m), because the leakage current in the area of the junction and the surrounding area are diffused. Dominant, so the calculated activation energy for different P / A ratios is about the same.

Page 23 200410320 V. Description of the invention (20) 3.4 Summary of experiment C The junction depth, sheet resistance, and electrical properties in the DI A junction were found to be independent of the conditions of RTa. The junction depth varies with the annealing temperature and RTA. Increase with time. In addition, the decline rate of RTA was discussed, and it was found that an increase in the decrease rate will reduce the expansion of boron ’and present a South activation concentration. By reducing the implantation energy, the planned D j A method can form a junction with almost no fabric defect. The area and surroundings have been discussed and found that the shielded amorphous silicon layer can isolate defects caused by the peaks of the implant. 4 · Summarizing shallow and steep junctions with high physical and electrical concentration and good thunder &amp; electrical properties can be formed using the planned DI Α junction formation method, and the private &amp; 7 results will be taken. Consistent with the DIA law. Shielding the amorphous silicon layer almost removes the DIA method to form a defect-free junction. ”Defects” series technology obtained by our technology. Our non-defective DIA connection surface makes ten nanometers of PM0S should be applied for the following patent application scope. Skotnicki's diagram shows the completeness of the different resistance and interface depth. For comparison (Figure 3-9), the surface is also attached to this map, and you can see that DI a is landing in the feasible field. The spirit and field of the present invention are limited only by the embodiments described above.

200410320 Brief Description of the Drawings Figure 1 is a schematic diagram of the D I A (D i f f s i ο n f r om m m p 1 a n t e d a m 0 r p h 0 s si 1 icon, diffused by implanted amorphous silicon) method. Figure 2 is a process diagram of the DIA (Diffusion from implanted amorphous s i 1 i c ο η ′) method. Table 1 is a table of RTA conditions for experiment A. Figure 3 shows the secondary mass spectrum of boron ion in experiment A. Table 2 shows the sheet resistance results of experiment A. Table 3 is a table of RTA time and temperature conditions for experiment B. Figure 4 is a SIMS image of boron before RTA after implantation. Figure 5 is a graph of the relationship between sheet resistance and RTA time and temperature of a 40keV BF2 + implanted sample. Figure 6 shows the relationship between the sheet resistance of a 45keV BF2 + implanted sample and the RTA time and temperature. Figure 7 is a graph of the relationship between sheet resistance and RTA time and temperature for a 50keV BF2 + implant sample. Fig. 8 is a sims diagram of different butterfly implantation energies after 25 seconds of RTA 900 C.

Figure 9 is a simS diagram of different butterfly implantation energies after 5 seconds at RTA 1000 ° C. Figure 10 is a SIMS plot of different boron implantation energies after 10 seconds at RT A 1 000 ° c. Fig. 11 is a graph showing the difference in implanted energy before RTA before RTA and after RTA 1 00 t 5 seconds after implantation. Table 4 shows the relationship between the junction depth and the implantation energy and RTA conditions in Experiment B.

Page 25 200410320 Schematic description of the table. Figure 12 is the cumulative graph of reverse bias (3V) leakage current density and different implantation energy RTA 1 0 5 0 ° C for 5 seconds at the D IA interface. Figure 13 is the cumulative graph of reverse bias (3V) bubble leakage current density and different implantation energy RTA 1 0 0 0 ° C for 5 seconds at the DIA interface. Figure 14 shows the reverse current-voltage characteristics of a 50keV RTA 100 ° C sample for 5 seconds at different temperatures. Figure 15 is a schematic diagram of the leakage component of the reverse bias junction. Figure 16 shows that the junction leakage current IR is the sum of the peripheral current IRP and the area current IRA. Figure 17 is a graph of reverse leakage current density versus different P / A ratios. Fig. 18 is a graph of the shallow leakage current density versus the P / A ratio for the reverse junction at the condition of 1050 C 5 seconds R T A. Figure 19 is an Arrhenius plot of reverse current versus ι / kT. Figure 20 is a graph of current density versus reverse bias for a region with temperature as a parameter. Figure 21 is a graph of the peripheral current density relative to the reverse direction with temperature as a parameter. , I Figure 22 is the Arrhen i us plot of the area current density versus l / kT at different voltages. Figure 23 shows the peripheral current density under different voltages relative to Arrhen i us H °. Figure 24 shows the current generation mechanism at (a) low bias and (b) high bias.

Page 26 200410320 Brief description of the diagrams Figure 25 is the schematic diagram of the ratio of JRP to JRA versus voltage for different temperatures. Figure 26 shows Arrhenius plots for different areas. Table 5 is a table of conditions of RTA time, temperature, and rate of decrease in Experiment C. FIG. 27 is a boron SI MS chart of the 40 keV BF2 + dose 5 × 1 015 atoms / cm 2 before RTA and the different RTA conditions after the cloth value. Table 6 shows the junction depth and sheet resistance data of experiment C. Fig. 28 is a graph of the resistance measured by the spreading probe (SRP) and the calculated doping concentration. Figure 29 is a cumulative plot of reverse bias leakage current density versus different R T A conditions. Figure 30 shows the reverse current-voltage characteristics measured at different temperatures. Figure 31 is a graph of the leakage current of the diodes with different areas relative to the p / a ratio. FIG. 32 is an Arrhenius plot of the current density in the junction area and the periphery. Figure 33 is a graph of the area current density versus reverse bias measured at different temperatures. Figure 34 is a graph of peripheral current density versus reverse bias measured at different temperatures. Figures 3 to 5 are Arrhen i us plots of regional current costs measured at different voltages. Figure 36 is an Arrhen i us plot of the peripheral current bifurcation measured at different voltages. Figure 37 is a graph of JRP / JRA ratio versus voltage for different temperatures.

Page 27 200410320 Simple illustration of the drawing Figure 38 is the Arrheuius plot for different areas. Figure 39 shows the complete comparison of chip resistance and junction depth obtained by different technologies. Page 28

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Claims (1)

200410320 VI. Application for Patent Scope 1.-A nanometer-level over-range is formed by stacking amorphous silicon and oxide layers, including the following steps: The coat of ¢ 7 is manufactured in a standard complementary metal-oxide-semiconductor (CMOSFET) process. After the formation of the gate dielectric layer and the gate electrode, the gate region 'plasma-assisted chemical vapor deposition (PECVD) grows a stone's nest' is deposited on the non-_ cover layer, and then the ion cloth-plant emulsification Amorphous silicon cover layer is used as a solid-state diffusion source. With the annealing method, the material can diffuse into the wafer and activate it. Therefore, the super shallow junction is required for the formation of nano-components and then the wet method is used. The etching technology removes the amorphous silicon layer, and this long ultra-thin oxide layer becomes a etch stop layer to prevent damage to the surface of the shallow engraved interface xt. The plasma-assisted chemical vapor phase of low temperature (100 ~ 40 0 ° C) is used for the ultra-thin oxide layer. It is used to grow 5 ~ 30 angstroms. , Its ^ 40〇Ϊ): Ικ assisted chemical rolling phase precipitation And deposition 丨 〇〇 ～ 500 〇 埃 的 电 4. As in the process of applying for the scope of the patent application item !, the date is Shi Yue. Wen (800 ~ 1100. 0 rapid annealing (RTA) square method) using high-fire Annealing. Fly or use low temperature thunder 5. The process of item 1 in the scope of patent application, in which the ionic species include boron difluoride (Bf2), boron (B), and the amount used is 50,000 to 50,000 electrons. Volts (eV), ^) used, energy used W is per square centimeter Page 29 200410320 VI. Application scope 1013 ~ 1016 ions. liglHi Page 30