TW200410264A - High-speed memory sensing circuit - Google Patents

Abstract

The present invention discloses a sensing circuit that uses high-speed charge transferring technique when reading data inside the memory for sensing voltage variation of data input terminal. In the invention, the purpose of high-speed sensing is obtained according to the difference of charge transferring amount generated during the precharge and data reading period.

Description

200410264 V. Description of the invention α) Technical field to which the invention belongs The present invention relates to a high-speed sensing circuit for a memory. The invention relates to a sensing circuit that uses a charge transfer technique to increase the rate of reading a memory material. In the prior art, data reading of a semiconductor memory is achieved by using a voltage sense amplifier (ν ο 1 t · ag e s e n s e a m ρ 1 i f i e r) or a current sense amplifier (s e n s e a m p 1 i f i e r). The voltage change of the sensing node of the original memory of the voltage sensing amplifier during data reading, the logical value of the data. Unfortunately, in high-speed devices, the process of reading data is often prone to errors due to process differences, which can lead to system errors. SUMMARY OF THE INVENTION . Because the amount of charge generated by different pre-charges is the same as the amount of charge generated by the sensing data; therefore, as long as a slight difference in the amount of charge can be sensed, the purpose of the memory invention is to provide a kind of internal data reading Measuring electricity-road. The sensing circuit inserts a charge storage element between the sensing and breaking circuits, so that the sensing circuit can immediately generate a corresponding output as long as the voltage of the sensing node changes during data reading, for the purpose of rapid sensing. According to the present invention, a high-speed sensing circuit and a circuit of a memory are sensed by an internal current device to determine a change or abnormal operation of the asset. The resulting electrical path is not relevant. The high-speed sense node / point / discrimination method is thus achieved. Including 200410264 V. Description of the invention (2) Connect a pre-charge circuit to the sensing node of the memory and between the sensing node and the judgment circuit A charge storage element is connected. During the pre-charging period, the sensing node is charged to a pre-charging voltage:. Then, during the sensing period, when the memory array is connected to the sensing node, the voltage of the charge storage element is changed to enable the judgment circuit to quickly Sensing memory data. Preferably, the judgment circuit includes a comparator, so that the sensing circuit has a large noise tolerance. 1 shows an embodiment of the present invention, in which the memory circuit 10 0 includes a current mirror 10 2, a reference array 108 and a memory array 1 10, and the signal BIAS switching transistor 10 104 and 106 The reference array 108 and the memory array 110 are connected to the current mirror 102 respectively, and the signal GN is an enable signal for data reading. The reference terminal of the current mirror 10 2 is connected to the transistor 104, and the f crystal 11 2 is controlled by the signal G N to connect the reference array 108 to the power supply voltage V si. The mirror end of the current mirror 102 is connected to the transistor 106 via the sensing node 1 and the transistor 114 is controlled by the signal 卩 to connect the memory array 110 to the power supply voltage V s s. The pre-charging circuit 1 2 0 is coupled to the sensing node 1 2 4, the sensing node 1 2 4 is also connected to the charge storage element 1 2 8, and the charge storage element 1 2 8 is connected to the judgment circuit 1 3 4. In addition, a switch 1 3 2 is connected between the input t a and the output 0 U T of the judgment-circuit 1 3 4. The pre-charging circuit 120 and the switch 132 are controlled by a pre-charging signal. During the pre-charging, the pre-charging signal controls the pre-charging circuit 1 2 0 and the switch 1 3 2 to be turned on, so that the pre-charging circuit 1 2 0 will sense. Nodes 1 2 4 are charged to one. Pre-charge voltage. When this circuit is switched to the sensing mode, the pre-charge circuit 1 2 0 is no longer active 丨

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200410264 V. Description of the invention (3), and the switch 132 is open, the signal BIAS controls the transistors 104 and 106 to be turned on ', and the signal GN controls the transistor 1 to be turned on, and 1 1 2 and 1 1 4 are turned on, as shown in the memory array 1 10 Stored data: a voltage change is generated at the sensing node 124 through the current mirror 1 Q 2 compared with the reference array 1 Q 8. The voltage change value is immediately displayed on the judgment circuit input terminal v a via the charge storage element 1 2 8, and then judged by the judgment circuit 1 3 4 to output its data. Figure 2 above shows an embodiment of the circuit of Figure 1. The memory circuit 2 is a conventional technology, including a current mirror 2 02, a reference array 2 0 8 and a memory array 2 10 'signal GN for data reading. Enabling signal. The current mirror 2 〇2 contains a reference, the transistor 2 0 3 is connected to the transistor 2 0 4 and the mirror-side transistor 2 0 5 is connected to the transistor 2 0 6 via the sensing node 2 2 4, and the transistor 2 1 6 is subject to Controlled by the precharge signal, the power voltage V dd is connected to the transistor 2 0 5. . & The transistor 2 2 0 is connected to the power supply voltage V dd, the transistor 2 2 2 is connected between the transistor 2 2 0 and the sensing node 2 2 4. /, and the gate of the transistor 2 2 0 is coupled to ^ The output of Xiangjie 2 1 8's input surface of inverter 2 1 8 is connected to the precharge signal, and the gate of the electric crystal 2 2 2 | Ma receives the signal BIAS. The capacitor 2 2 8 is connected between the sensing node 2 2 4 and the inverter 2 3 4. In addition, a switch 2 3 2 is connected between the input Va and the output OUT of the inverting p 2 3 4. During the pre-charging period, the pre-charging signal is "1". This signal controls the transistor 2 1-6 to turn off and cuts off the current 2 0 2 and creates the terminal transistor 2 0 5's original charge. The transistor 2 2 0 is turned on through the inverter 2 1 8, and the sensing node 2 2 4 is charged to a precharge voltage through the crystal 2 2 2. The switch 2 3 2 is also controlled by the precharge signal as' 1 ”And turned on, the capacitor 2 2 8 therefore stores electricity, why 0

Page 7 200410264 V. Splash * · Explanation (4_) ^ 一一 _ 一 —— 一 ___ ^ ~ The signal is 2 1 2, 2 1 During the sensing period after the top charge, the transistor 2 1 6 is subject to Controlling the pre-charge ^ turn-on signal MAS and GN makes the transistor 2 0 4, 2,…… let 11 ^ 2 ^ ^ stored f material through the sense node 'y 丨 丨〗 丨 丨 i i' Variety. When the sensed data is horse / guard, the change in the charge on the capacitor 2 2 8 is very small, which cannot make the reverse 2 3 4 transition; when the data is " 〇 „, the charge on the capacitor 2 2 8 The larger green and green voltage are enough to make the inverter 2 3 4 transition state. Therefore, this circuit reads the internal data of the memory 2 by the amount of change in charge transfer. The circuit shown in Figure 3 is shown in Figure 1. The second embodiment is the same as the circuit of FIG. 2 but the judgment circuit uses a comparator 334. The comparator 334 has a negative input 3 3 0 and a positive input 3 3 8, and the negative input 3 3 0 is connected to the capacitor 3 2 8, positive input 2 3 3 8 is connected to—reference signal vref, a switch 3 3 2 is connected across the negative wheel input 3 3 〇 of the comparator 3 3 4 and the output 0 UT. In this implementation, the reference The signal Vref turns a voltage to the comparator 3 3 4 and the positive input is 3 3 8. During the pre- '^, the switch 3 3 2 receives the pre-charge signal, and the 4 blanking is turned on, which causes the comparator to return negatively. Terminal 3 3 0 and the positive wheel: the input terminal 3 3 8 has the same short circuit potential. During the test, the switch 3 3 2 is controlled by the pre-charge signal to open, so that the capacitor 3 2 8 is at the negative input 3 3 0 only. There is a change in charge, and it immediately responds to the noise tolerance of the output 0ϋτ. The tolerance of noise is higher than that of the circuit of Fig. 2. Fig. 4 is another embodiment of the present invention. The pre-charging circuit 4 2 0 and the test node 4 2 4 and Charge storage element 4 2 8, Thunder y for six ', Pinjiu Magic 丨 β 1 child 4 B. Electric storage element 4? R far s Another charge storage element 43 8 and judgment circuit 434, can not be connected to VI factory To the switch 44 0, the switch 44 0 is controlled to connect the charge storage element to one, test WV., Open the display.

200410264 V. Description of the invention (5) Power on, voltage. The pre-charging circuit 4 2 0 and the switch 4 3 2 are controlled by the pre-charging circuit. The pre-charging signal controls the pre-charging :: in the pre-charging towel. 4 q 9 Please make this pre: the charging circuit 4 2 0 charges the sensing node 424 to the-pre: when this circuit is switched to the sensing mode, the pre-charging is not / ¾ and the switch 432 is open, the signal BIAS controls the transistor 4〇 The data stored in 4 and 0 2 and the signal GN control transistors 412 and 41 4 1 0 generate voltage changes through the current mirror 4 02 ratio array sensing node 424. The voltage / test voltage] 4 0 8 and the elements 42 8 and 4 3 8 will immediately appear in the judgment ^ = stored by the ^ load circuit 434 and output its data. Then on Va, it is judged during the period of pre-charging and sensing data, because-the total charge stored by storage elements 4 2 8 and 4 3 8 is only ^ 1 constant principle to maintain a certain ratio of charge charge storage elements, then ί 彳 inches are not affected. So just electricity: decided. … Characteristics can be used / used ”; = FIG. 5 is an embodiment of the circuit of FIG. 4, where ## is two capacitors with a proportional ratio. 2 4. Feel the pre-charge signal connected to 5 2 8 :, capacitor 5 2 8 is connected to cover capacitor 5 3 8 and anti-heart 5 2 4 is connected to switch 54. Connected to the ground terminal is 34.芩 5 $ 8 is connected between the input va and the output 〇u T of the inverter 5 3 4. The switch 5 3 2 is connected across the electric sun body 5 2 0 and the switch 5 3 2 is controlled by pre-fen # v The pre-charging signal controls the 52% signal of the transistor. During the pre-charging period, and the switch 5 3 2 is turned on, the electric

Page 9 200410264 V. Description of the invention (6) Crystal 5 2 0 charges the sensing node 5 2 4 to a precharge voltage. When the circuit is switched to the sensing mode, the transistor 5 2 0 stops functioning and the switch 5 3 2 is open. The voltage change of the memory circuit 5 0 0 at the sensing node 5 2 4 passes electricity: the capacitances 5 2 8 and 5 3 8 will be immediately displayed on the judgment circuit input terminal V a, and then judged by the judgment circuit 5 3 4 and output Its information. In this embodiment, an inverter 5 3 4 is used as the judgment circuit. In different implementations, a comparator or other similar devices may be used.

The above description of the preferred embodiments of the present invention is for the purpose of illustration, and is not intended to limit the present invention to the precise form disclosed. Modifications or changes based on the above teaching or learning from the embodiments of the present invention are Possibly, the embodiments are selected and described for explaining the principle of the present invention and for those skilled in the art to use the present invention in practical applications in various embodiments. The technical idea of the present invention is intended to be covered by the following patent application scope and its equivalent To decide.

Page 10 200410264 Brief description of the diagram For those skilled in the art, the present invention will be more clearly understood from the detailed description and accompanying diagrams made below, and its above and other objectives and advantages will change. It is more obvious, in which: FIG. 1 is a schematic diagram of a first embodiment according to the present invention; FIG. 2 is a circuit of a first embodiment of the device of FIG. 1; FIG. 3 is a circuit of a second embodiment of the device of FIG. FIG. 5 is a schematic diagram of a second embodiment of the present invention; FIG. 5 is a circuit diagram of an embodiment of the device of FIG. 4. Comparison table of components and their numbers 100 Memory circuit 1 02 Current mirror 104 MOS transistor 106 MOS transistor 108 Reference array 110 Memory array 1 1 2 MOS transistor 114 MOS 'transistor 12 0 Pre-charge circuit 12 4 — Sense node '' 128 charge storage element 1 3 2 switch 134 judgment circuit 200 memory circuit

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200410264 Schematic description 20 2 Current mirror 20 3 MOS transistor 20 5 MOS transistor 20 5 MOS transistor 20 6 MOS transistor 208 Reference array 2 10 Memory array 2 12 MOS transistor 214 MOS transistor 2 16 MOS transistor 21 8 Inverter 220 MOS transistor 222 MOS transistor 224 Sensing trip point 22 8 Capacitance 232 Switch 234 Inverter 30 0 Memory circuit 31 6 MOS transistor 3 18- Inverter 320 MOS transistor 322 MOS transistor 324 sense node 328 capacitance

Page 12 200410264 Simple illustration of the diagram 3 3 0 Va node 3 3 2 Switch 3 3 4 Comparator: Comparator 3 3 8 Comparator reference voltage 4 0 0 Memory circuit 4 0 2 Current mirror 4 0 4 MOS transistor 4 0 6 MEMS transistor 4 0 8 Reference array 4 10 Memory array 412 MOS transistor 4 1 4 MOS transistor 4 2 0 Pre-charge circuit 42 4 Sense node 4 2 8 Charge storage element 4 3 2 Switch 4 3 4 Judgment circuit 4 3 8 Charge storage element 44 0 Switch 5 0 0-Memory circuit 5 2 0 MOS transistor 5 2 4 Sense node 5 2 8 Capacitor 5 3 2 Switch

Page 13 200410264 Simple illustration of the diagram 534 Inverter 538 Capacitor 5 4 0 On Off

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Claims (1)

200410264 6. Application patent scope 1 * A high-speed sensing circuit of a memory determines the stored data of the memory by sensing a voltage change on a sensing node during a sensing period. The sensing circuit includes: 'a A pre-charging circuit that charges the sensing node to a pre-charging voltage during a pre-charging period before the sensing period; a judging circuit that connects an input signal and outputs a data signal in response to the input signal during the sensing period; The charge storage element is coupled between the sensing node and the input of the judgment circuit; and a switch is connected between the input and output of the judgment circuit, thereby bypassing the judgment circuit during the pre-charging period. 2 · The sensing circuit according to item 1 of the patent application scope, wherein the precharge voltage is less than the power supply voltage. 3. The sensing circuit according to item 1 of the patent application scope, wherein the judgment circuit includes an inverter. / 4 · The sensing circuit according to item 1 of the patent application range, wherein the judgment circuit includes a comparator to compare the input signal with a reference voltage to determine the data signal. 5 — A high-speed sensing circuit of a memory, for sensing during a sensing period—a voltage change at a sensing node determines the storage, storage, and data of the memory. The sensing circuit includes: a precharge A circuit that charges the sensing node to a precharge voltage during a precharge period before the sensing period; a judgment circuit that connects an input signal and responds during the sensing period Page 15 200410264 VI. Patent application input signal outputs a data signal; a first charge storage element is coupled between the sensing node and the input of the judgment circuit; a second charge storage element is controlled by the sensor Inserted between the input of the judgment circuit and a reference voltage during the test to transfer an amount of charge from the first charge storage element; and a switch connected between the input and output of the judgment circuit, thereby pre-charging The judgment circuit is bypassed during this period. 6 • If a patent is applied, the sensing circuit of item 5 in which the precharge voltage is less than the power supply voltage. 7. The sensing circuit according to item 5 of the patent application ^, wherein the judgment circuit includes an inverter. 8. The sensing circuit according to item 5 of the patent application, wherein the judgment circuit includes a comparator to compare the input signal with a second reference voltage to determine the lean signal. / 9 · If the sensing circuit according to item 5 of the patent application scope further comprises a third switch controlledly connecting the reference voltage to the second charge storage element. 1 0 · A high-speed sensing method of a memory to sense the stored data of the memory from a sensing node of the memory, the method includes the following steps: connecting-a charge storage element to the sensing node; r Charging the sensing node to a pre-charging voltage during pre-charging; connecting a memory array to the sensing node during sensing; and determining a data signal according to a voltage change generated by the charge storage element. Page 16 200410264 Page 17