TW200410264A - High-speed memory sensing circuit - Google Patents
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200410264 五、發明說明α) 發明所屬之技術領域 本發明係關於一種用於記憶體之高速感測電 是關於一種利用電荷轉移的技巧來提升讀取記憶 料速率之感測電路。 先前技術 半導體記憶體的資料讀取係利用電壓感測放 (ν ο 1 t· a g e s e n s e a m ρ 1 i f i e r )或電流感測放大器( s e n s e a m p 1 i f i e r )來達成。電壓感測放大器的原 記憶體的感測節點在資料讀取期間的電壓變化, 料的邏輯值。不幸地,在高速元件中,常因製程 差使得資料讀取容易發生錯誤,造成系統的不正 發明内容 / 本發明提出一種偵測不同路徑的電荷轉移所 荷差值,以達到高速感測的目的。因為經由不同 預充電(p r e - c h a r g e )與感測資料所產生的電荷量 同;因此只要些微的電荷量差即可感測到記憶體 發明的目的,在於提供一·種記憶體内部資料讀取 測電-路。該感測電路係將電荷儲存元件插入感測 斷電路之間,使得資料讀取期間感測節點只要'有 壓變化,判斷電路就能立即地產生因應的輸出, 快速感測的目的。 根據本發明,一種記憶體之高速感測電路及 路’特別 體内部資 大器 current 理係感測 以決定資 變動或偏 常運作。 產生的電 路徑進行 並不相 資料。本 之高速感 節/點/與判 些微的電 因而達到 方法.包括 200410264 五、發明說明(2) 連接一預充電電路至該記憶體的感測節點以及在該感測節 點與判斷電路之間連接一電荷儲存元件。在預充電期間, 該感測節點被充電至一預充電電壓:.,然後在感測期間,當 記憶陣列連接至感測節點時,藉由該電荷儲存元件的電壓 變化,使判斷電路能快速感測出記憶資料。較佳者,該判 斷電路包括一比較器,使該感測電路有較大之雜訊容忍能 力。 實施方式 圖1顯示本發明之一實施例,其中記憶體電路10 0包括 電流鏡1 0 2、參考陣列1 0 8及記憶陣列1 1 0,信號B I A S開關 電晶體1 0 4及1 0 6以分別連接參考陣列1 0 8及記憶陣列1 1 0到 電流鏡1 0 2,信號G N為資料讀取之致能信號。電流鏡1 0 2之 參考端連接到電晶體1 0 4,f晶體11 2受控於信號G N以連接 參考陣列108到電源電壓V si。電流鏡102之鏡射端經感測 節點1 2 4連接電晶體1 0 6,電晶體114受控於信號卩?^以連接 記憶陣列1 1 0到電源電壓V s s。預充電電路1 2 0耦接至感測 節點1 2 4,感測節點1 2 4亦連接電荷儲存元件1 2 8,電荷儲 存元件1 2 8連接至判斷電路1 3 4。此外,一開關1 3 2跨接在 判斷-電路1 3 4之輸入t a與輸出0 U T之間。 , 預充電電路12 0及開關132受控於預充電信號,在預充 電期間,該預充電信號控制預充電電路1 2 0以及開關1 3 2導 通,使該預充電電路1 2 0將感測節點1 2 4充電至一。預充電電 壓。當此電路切換到感測模式後,預充電電路1 2 0不再作 丨200410264 V. Description of the invention α) Technical field to which the invention belongs The present invention relates to a high-speed sensing circuit for a memory. The invention relates to a sensing circuit that uses a charge transfer technique to increase the rate of reading a memory material. In the prior art, data reading of a semiconductor memory is achieved by using a voltage sense amplifier (ν ο 1 t · ag e s e n s e a m ρ 1 i f i e r) or a current sense amplifier (s e n s e a m p 1 i f i e r). The voltage change of the sensing node of the original memory of the voltage sensing amplifier during data reading, the logical value of the data. Unfortunately, in high-speed devices, the process of reading data is often prone to errors due to process differences, which can lead to system errors. SUMMARY OF THE INVENTION . Because the amount of charge generated by different pre-charges is the same as the amount of charge generated by the sensing data; therefore, as long as a slight difference in the amount of charge can be sensed, the purpose of the memory invention is to provide a kind of internal data reading Measuring electricity-road. The sensing circuit inserts a charge storage element between the sensing and breaking circuits, so that the sensing circuit can immediately generate a corresponding output as long as the voltage of the sensing node changes during data reading, for the purpose of rapid sensing. According to the present invention, a high-speed sensing circuit and a circuit of a memory are sensed by an internal current device to determine a change or abnormal operation of the asset. The resulting electrical path is not relevant. The high-speed sense node / point / discrimination method is thus achieved. Including 200410264 V. Description of the invention (2) Connect a pre-charge circuit to the sensing node of the memory and between the sensing node and the judgment circuit A charge storage element is connected. During the pre-charging period, the sensing node is charged to a pre-charging voltage:. Then, during the sensing period, when the memory array is connected to the sensing node, the voltage of the charge storage element is changed to enable the judgment circuit to quickly Sensing memory data. Preferably, the judgment circuit includes a comparator, so that the sensing circuit has a large noise tolerance. 1 shows an embodiment of the present invention, in which the memory circuit 10 0 includes a current mirror 10 2, a reference array 108 and a memory array 1 10, and the signal BIAS switching transistor 10 104 and 106 The reference array 108 and the memory array 110 are connected to the current mirror 102 respectively, and the signal GN is an enable signal for data reading. The reference terminal of the current mirror 10 2 is connected to the transistor 104, and the f crystal 11 2 is controlled by the signal G N to connect the reference array 108 to the power supply voltage V si. The mirror end of the current mirror 102 is connected to the transistor 106 via the sensing node 1 and the transistor 114 is controlled by the signal 卩 to connect the memory array 110 to the power supply voltage V s s. The pre-charging circuit 1 2 0 is coupled to the sensing node 1 2 4, the sensing node 1 2 4 is also connected to the charge storage element 1 2 8, and the charge storage element 1 2 8 is connected to the judgment circuit 1 3 4. In addition, a switch 1 3 2 is connected between the input t a and the output 0 U T of the judgment-circuit 1 3 4. The pre-charging circuit 120 and the switch 132 are controlled by a pre-charging signal. During the pre-charging, the pre-charging signal controls the pre-charging circuit 1 2 0 and the switch 1 3 2 to be turned on, so that the pre-charging circuit 1 2 0 will sense. Nodes 1 2 4 are charged to one. Pre-charge voltage. When this circuit is switched to the sensing mode, the pre-charge circuit 1 2 0 is no longer active 丨
難difficult
200410264 五、發明說明(3) 用,且開關132開路,信號BIAS控制電晶體104與1〇6導 通’以及信號GN控制電晶體1 1 2與1 1 4導通,在記憶陣列 1 1 0中所儲存之資料:經由電流鏡1 Q 2比較參考陣列1 Q 8而在 感測節點124產生電壓變化。該電壓變化值經由電荷儲存 元件1 2 8會立即呈現在判斷電路輸入端v a上,再由判斷電 路1 3 4判斷後輸出其資料。 上 圖2所示為圖1電路之一實施例,記憶體電路2 〇 〇如習 知之技術,包括電流鏡2 〇 2、參考陣列2 0 8及記憶陣列 2 1 〇 ’信號GN為資料讀取之致能信號。電流鏡2 〇 2包含參考 ,電晶體2 0 3連接到電晶體2〇4與鏡射端電晶體2 0 5經感測 節點2 2 4連接到電晶體2 〇 6 ,電晶體2 1 6受控於預充電信號 連接電源電壓V d d至電晶體2 0 5。 。& 電晶體2 2 0連接到電源電壓V d d,電晶體2 2 2連接在電 晶體2 2 0與感測節點2 2 4.之間/,電晶體2 2 0之閘極耦接到^ 相杰2 1 8的輸出’反相器2 1 8的輸入麵接預充電信號,電晶 叙2 2 2之閘極|馬接到信號B I A S。電容2 2 8連接在感測節點 2 2 4及反相器2 3 4之間。另外,一開關2 3 2跨接在反相p 2 3 4 之輸入Va與輸出OUT之間。 在預充電期間,預充電信號為” 1,,,該信號控制電晶 肢2 1— 6截止,切斷電流叙2 0 2叙創端電晶體2 〇 5的電丨原 外’預充電信號經過反相器2 1 8使得電晶體2 2 〇導通,經 晶體2 2 2對感測節點2 2 4充電至一預充電電壓。開關2 3 2亦' ^控於預充電信號為,'1”而導通,電容2 2 8因此而儲存電、 何0200410264 V. Description of the invention (3), and the switch 132 is open, the signal BIAS controls the transistors 104 and 106 to be turned on ', and the signal GN controls the transistor 1 to be turned on, and 1 1 2 and 1 1 4 are turned on, as shown in the memory array 1 10 Stored data: a voltage change is generated at the sensing node 124 through the current mirror 1 Q 2 compared with the reference array 1 Q 8. The voltage change value is immediately displayed on the judgment circuit input terminal v a via the charge storage element 1 2 8, and then judged by the judgment circuit 1 3 4 to output its data. Figure 2 above shows an embodiment of the circuit of Figure 1. The memory circuit 2 is a conventional technology, including a current mirror 2 02, a reference array 2 0 8 and a memory array 2 10 'signal GN for data reading. Enabling signal. The current mirror 2 〇2 contains a reference, the transistor 2 0 3 is connected to the transistor 2 0 4 and the mirror-side transistor 2 0 5 is connected to the transistor 2 0 6 via the sensing node 2 2 4, and the transistor 2 1 6 is subject to Controlled by the precharge signal, the power voltage V dd is connected to the transistor 2 0 5. . & The transistor 2 2 0 is connected to the power supply voltage V dd, the transistor 2 2 2 is connected between the transistor 2 2 0 and the sensing node 2 2 4. /, and the gate of the transistor 2 2 0 is coupled to ^ The output of Xiangjie 2 1 8's input surface of inverter 2 1 8 is connected to the precharge signal, and the gate of the electric crystal 2 2 2 | Ma receives the signal BIAS. The capacitor 2 2 8 is connected between the sensing node 2 2 4 and the inverter 2 3 4. In addition, a switch 2 3 2 is connected between the input Va and the output OUT of the inverting p 2 3 4. During the pre-charging period, the pre-charging signal is "1". This signal controls the transistor 2 1-6 to turn off and cuts off the current 2 0 2 and creates the terminal transistor 2 0 5's original charge. The transistor 2 2 0 is turned on through the inverter 2 1 8, and the sensing node 2 2 4 is charged to a precharge voltage through the crystal 2 2 2. The switch 2 3 2 is also controlled by the precharge signal as' 1 ”And turned on, the capacitor 2 2 8 therefore stores electricity, why 0
第7頁 200410264 五、潑*·明說明(4_) ^一一_一——一___^ 〜 信號為 2 1 2 、2 1 在頂充電曾之後的感測期間,電晶體2 1 6受控於預充電 ^導通’信號MAS與GN使得電晶體2 0 4、2 、 …使11^2^ ^所儲存的f料經由感剛節點' y丨丨〗丨丨士 i£'生笔荷變化。當所感測的資料 马/守,電容2 2 8上的電荷變化量很小,無法使得 反^目裔2 3 4轉態;而當資料為"〇„時,電容2 2 8上的電荷綠、 化^較大,足夠使反相器2 3 4轉態,因此,此電路是籍= 電荷轉移的變化量來讀取記憶體2 〇 〇内部資料。 曰 圖3所示係圖1電路之第二實施例,其與圖2之電路 同’但是判斷電路使用比較器334。比較器334具有—負^ 入3 3 0與一正輸入3 3 8,負輸入3 3 0連接至電容3 2 8,正輸二 3 3 8連接至—參考信號v r e f,一開關3 3 2跨接在比較器3 3 4 之負輪入3 3 〇與輸出0 U T之間。在此實施列中,參考信號 Vref輪人一電壓至比較器3 3 4之正輸人3 3 8。在預‘ ‘ ^ 間,開關3 3 2受預充電信號,4空制導通造成比較器之負回/ 授 貞輸入端3 3 0與正輪:入端3 3 8虛短路電位相等。、名咸測 期間,開關3 3 2受預充電信號控制斷開,使得電容3 2 8在負 輸入3 3 0只要有電荷變化,立即反應於輸出〇ϋτ。 的 雜訊容忍度較圖2的電路高。 、—圖4為本發明之另一實施例,預充電電路4 2 〇叙咸 測節點4 2 4及電荷儲存元件4 2 8 ,雷y作六 '、 品 久电幻丨β 1儿4乙。电何儲存元件4 ? R遠s 另一電荷儲存元件43 8以及判斷電路434, 法連接 VI接厂至開關44 0,開關44 0受控連接電荷儲元件至一 ,考WV。,開顯2.跨接在判斷電路川之輪人^食輸出Page 7 200410264 V. Splash * · Explanation (4_) ^ 一一 _ 一 —— 一 ___ ^ ~ The signal is 2 1 2, 2 1 During the sensing period after the top charge, the transistor 2 1 6 is subject to Controlling the pre-charge ^ turn-on signal MAS and GN makes the transistor 2 0 4, 2,…… let 11 ^ 2 ^ ^ stored f material through the sense node 'y 丨 丨〗 丨 丨 i i' Variety. When the sensed data is horse / guard, the change in the charge on the capacitor 2 2 8 is very small, which cannot make the reverse 2 3 4 transition; when the data is " 〇 „, the charge on the capacitor 2 2 8 The larger green and green voltage are enough to make the inverter 2 3 4 transition state. Therefore, this circuit reads the internal data of the memory 2 by the amount of change in charge transfer. The circuit shown in Figure 3 is shown in Figure 1. The second embodiment is the same as the circuit of FIG. 2 but the judgment circuit uses a comparator 334. The comparator 334 has a negative input 3 3 0 and a positive input 3 3 8, and the negative input 3 3 0 is connected to the capacitor 3 2 8, positive input 2 3 3 8 is connected to—reference signal vref, a switch 3 3 2 is connected across the negative wheel input 3 3 〇 of the comparator 3 3 4 and the output 0 UT. In this implementation, the reference The signal Vref turns a voltage to the comparator 3 3 4 and the positive input is 3 3 8. During the pre- '^, the switch 3 3 2 receives the pre-charge signal, and the 4 blanking is turned on, which causes the comparator to return negatively. Terminal 3 3 0 and the positive wheel: the input terminal 3 3 8 has the same short circuit potential. During the test, the switch 3 3 2 is controlled by the pre-charge signal to open, so that the capacitor 3 2 8 is at the negative input 3 3 0 only. There is a change in charge, and it immediately responds to the noise tolerance of the output 0ϋτ. The tolerance of noise is higher than that of the circuit of Fig. 2. Fig. 4 is another embodiment of the present invention. The pre-charging circuit 4 2 0 and the test node 4 2 4 and Charge storage element 4 2 8, Thunder y for six ', Pinjiu Magic 丨 β 1 child 4 B. Electric storage element 4? R far s Another charge storage element 43 8 and judgment circuit 434, can not be connected to VI factory To the switch 44 0, the switch 44 0 is controlled to connect the charge storage element to one, test WV., Open the display.
200410264 五 發明說明(5) 一一 〇U丁之間。 電期 通, 壓。 用, 通, 預充電電路4 2 0及開關4 3 2受控於預充帝ρ跋 間’該預充電信號控制預充電::在預充 巾」ί月九兒包路4 2 〇以及開關4 q 9请 使該預:充電電路4 2 0將感測節點424充電至—預: 當此電路切換到感測模式後,預充 不/ ¾ 且開關432開路,信號BIAS控制電晶體4〇4與〇二^ 以及信號GN控制電晶體412與41 峄 41〇中所儲存之資料經由電流鏡4 0 2比陣列 感測節點424產生電壓變化。該電壓/考車歹]4 0 8而在 元件42 8及4 3 8會立即呈現在判斷^=由^荷儲存 斷電路434判斷後輸出其資料。 則鳊Va上,再由判 在預充電與感測資料期間,因為 — 儲存元件4 2 8與4 3 8儲存之總電荷量唯^ 1恒原理使電荷 荷儲存元件維持一定比值,則電冇ί彳寸不受。所以只要電 :決定。…特性便可/利用“;= 圖5係圖4電路之一實施例,其泰# 為具-比例之兩個電容。電晶體何儲存兀件528及538 接電源電壓Vdd至感測節點5 2 4,感於預充電信號連 5 2 8:,電容5 2 8連接蓋電容5 3 8以及反即心5 2 4連接電容 接至開關54〇,以受控連接至接地端為34,電芩5 $ 8連 反相益5 3 4之輸入v a與輸出〇 u T之間。,開關5 3 2跨接在 電日日體5 2 0及開關5 3 2受控於預奋# v 間,該.預充電信號控制電晶體52〇 %信號,在預充電期 乂及開關5 3 2導通,使電200410264 V. Description of the invention (5) Power on, voltage. The pre-charging circuit 4 2 0 and the switch 4 3 2 are controlled by the pre-charging circuit. The pre-charging signal controls the pre-charging :: in the pre-charging towel. 4 q 9 Please make this pre: the charging circuit 4 2 0 charges the sensing node 424 to the-pre: when this circuit is switched to the sensing mode, the pre-charging is not / ¾ and the switch 432 is open, the signal BIAS controls the transistor 4〇 The data stored in 4 and 0 2 and the signal GN control transistors 412 and 41 4 1 0 generate voltage changes through the current mirror 4 02 ratio array sensing node 424. The voltage / test voltage] 4 0 8 and the elements 42 8 and 4 3 8 will immediately appear in the judgment ^ = stored by the ^ load circuit 434 and output its data. Then on Va, it is judged during the period of pre-charging and sensing data, because-the total charge stored by storage elements 4 2 8 and 4 3 8 is only ^ 1 constant principle to maintain a certain ratio of charge charge storage elements, then ί 彳 inches are not affected. So just electricity: decided. … Characteristics can be used / used ”; = FIG. 5 is an embodiment of the circuit of FIG. 4, where ## is two capacitors with a proportional ratio. 2 4. Feel the pre-charge signal connected to 5 2 8 :, capacitor 5 2 8 is connected to cover capacitor 5 3 8 and anti-heart 5 2 4 is connected to switch 54. Connected to the ground terminal is 34.芩 5 $ 8 is connected between the input va and the output 〇u T of the inverter 5 3 4. The switch 5 3 2 is connected across the electric sun body 5 2 0 and the switch 5 3 2 is controlled by pre-fen # v The pre-charging signal controls the 52% signal of the transistor. During the pre-charging period, and the switch 5 3 2 is turned on, the electric
第9頁 200410264 五、發明說明(6) 晶體5 2 0將感測節點5 2 4充電至一預充電電壓。當此電路切 換到感測模式後,電晶體5 2 0停止作用,且開關5 3 2開路。 記憶體電路5 0 0在感測節點5 2 4之電壓變化值經由電:容5 2 8 及5 3 8會立即呈現在判斷電路輸入端V a上,再由判斷電路 5 3 4判斷後輸出其資料。 在此實施例中使用反相器5 3 4作為判斷電路,在不同 的實施列中,亦可使用比較器或其他類似的裝置。Page 9 200410264 V. Description of the invention (6) Crystal 5 2 0 charges the sensing node 5 2 4 to a precharge voltage. When the circuit is switched to the sensing mode, the transistor 5 2 0 stops functioning and the switch 5 3 2 is open. The voltage change of the memory circuit 5 0 0 at the sensing node 5 2 4 passes electricity: the capacitances 5 2 8 and 5 3 8 will be immediately displayed on the judgment circuit input terminal V a, and then judged by the judgment circuit 5 3 4 and output Its information. In this embodiment, an inverter 5 3 4 is used as the judgment circuit. In different implementations, a comparator or other similar devices may be used.
以上對於本發明之較佳實施例所做的敘述係為闡明之 目的,而無意限定本發明精確地為所揭露的形式,基於以 上的教導或從本發明的實施例學習而作修改或變化是可能 的,實施例係為解說本發明的原理以及讓熟習該項技術者 以各種實施例利用本發明在實際應用上而選擇及敘述,本 發明的技術思想企圖由以下的申請專利範圍及其均等來決 定。The above description of the preferred embodiments of the present invention is for the purpose of illustration, and is not intended to limit the present invention to the precise form disclosed. Modifications or changes based on the above teaching or learning from the embodiments of the present invention are Possibly, the embodiments are selected and described for explaining the principle of the present invention and for those skilled in the art to use the present invention in practical applications in various embodiments. The technical idea of the present invention is intended to be covered by the following patent application scope and its equivalent To decide.
第10頁 200410264 圖式簡單說明 對於熟習此項技藝之人士而言,從以下所做的詳細敘 述配合伴隨的圖示本發明將能夠更清楚地被了解,其上 述及其他目的及優點將會變得更明顯,其中: 圖1係根據本發明之第一實施例的示意圖; 圖2係圖1之裝置的第一實施例電路; 圖3係圖1之裝置的第二實施例電路; 圖4係根據本發明之第二實施例的示意圖; 圖5係圖4之裝置的一個實施例電路。 元件及其標號對照表 100 記憶體電路 1 02 電流鏡 104 MOS電晶體 106 MOS電晶體 108 參考陣列 110 記憶陣列 1 1 2 MOS電晶體 114 MOS'電晶體 12 0 預充電電路 12 4 — 感測節點 ’ 128 電荷儲存元件 1 3 2 開關 134 判斷電路 200 記憶體電路Page 10 200410264 Brief description of the diagram For those skilled in the art, the present invention will be more clearly understood from the detailed description and accompanying diagrams made below, and its above and other objectives and advantages will change. It is more obvious, in which: FIG. 1 is a schematic diagram of a first embodiment according to the present invention; FIG. 2 is a circuit of a first embodiment of the device of FIG. 1; FIG. 3 is a circuit of a second embodiment of the device of FIG. FIG. 5 is a schematic diagram of a second embodiment of the present invention; FIG. 5 is a circuit diagram of an embodiment of the device of FIG. 4. Comparison table of components and their numbers 100 Memory circuit 1 02 Current mirror 104 MOS transistor 106 MOS transistor 108 Reference array 110 Memory array 1 1 2 MOS transistor 114 MOS 'transistor 12 0 Pre-charge circuit 12 4 — Sense node '' 128 charge storage element 1 3 2 switch 134 judgment circuit 200 memory circuit
第11頁Page 11
200410264 圖式簡單說明 20 2 電流鏡 20 3 MOS電晶體 204 MOS電晶體 20 5 MOS電晶體 20 6 MOS電晶體 208 參考陣列 2 10 記憶陣列 2 12 MOS電晶體 214 MOS電晶體 2 16 MOS電晶體 21 8 反相器 220 MOS電晶體 222 MOS電晶體 224 感測卸點 22 8 電容 232 開關 234 反相器 30 0 記憶體電路 31 6 MOS電晶體 3 18- 反相器 320 MOS電晶體 322 MOS電晶體 324 感測節點 328 電容200410264 Schematic description 20 2 Current mirror 20 3 MOS transistor 20 5 MOS transistor 20 5 MOS transistor 20 6 MOS transistor 208 Reference array 2 10 Memory array 2 12 MOS transistor 214 MOS transistor 2 16 MOS transistor 21 8 Inverter 220 MOS transistor 222 MOS transistor 224 Sensing trip point 22 8 Capacitance 232 Switch 234 Inverter 30 0 Memory circuit 31 6 MOS transistor 3 18- Inverter 320 MOS transistor 322 MOS transistor 324 sense node 328 capacitance
第12頁 200410264 圖式簡單說明 3 3 0 Va節點 3 3 2 開關 3 3 4 比較:器 3 3 8 比較器參考電壓 4 0 0 記憶體電路 4 0 2 電流鏡 4 0 4 MOS電晶體 4 0 6 Μ 0 S電晶體 4 0 8 參考陣列 4 10 記憶陣列 412 MOS電晶體 4 1 4 Μ〇S電晶體 4 2 0 預充電電路 42 4 感測節點 4 2 8 電荷儲存元件 4 3 2 開關 4 3 4 判斷電路 4 3 8 電荷儲存元件 44 0 開關 5 0 0 - 記憶體電路 5 2 0 MOS電晶體 5 2 4 感測節點 5 2 8 電容 5 3 2 開關Page 12 200410264 Simple illustration of the diagram 3 3 0 Va node 3 3 2 Switch 3 3 4 Comparator: Comparator 3 3 8 Comparator reference voltage 4 0 0 Memory circuit 4 0 2 Current mirror 4 0 4 MOS transistor 4 0 6 MEMS transistor 4 0 8 Reference array 4 10 Memory array 412 MOS transistor 4 1 4 MOS transistor 4 2 0 Pre-charge circuit 42 4 Sense node 4 2 8 Charge storage element 4 3 2 Switch 4 3 4 Judgment circuit 4 3 8 Charge storage element 44 0 Switch 5 0 0-Memory circuit 5 2 0 MOS transistor 5 2 4 Sense node 5 2 8 Capacitor 5 3 2 Switch
第13頁 200410264 圖式簡單說明 534 反 相器 538 電 容 5 4 0 開 關Page 13 200410264 Simple illustration of the diagram 534 Inverter 538 Capacitor 5 4 0 On Off
第14頁Page 14
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