CN107665718B - Charge transfer type sense amplifier - Google Patents
Charge transfer type sense amplifier Download PDFInfo
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- CN107665718B CN107665718B CN201710851521.1A CN201710851521A CN107665718B CN 107665718 B CN107665718 B CN 107665718B CN 201710851521 A CN201710851521 A CN 201710851521A CN 107665718 B CN107665718 B CN 107665718B
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- data line
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/062—Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
- G11C7/08—Control thereof
Abstract
The invention discloses a charge transfer type sensitive amplifier, comprising: a compensation circuit unit connected between a power supply voltage and a column data line node for providing a compensation current; the compensation circuit unit is in a structure that the compensation current can change in a self-adaptive manner according to the voltage of the column data line node; when the memory unit is in a programming state, the pull-down current of the memory unit to a column data line node is small, the column data line node is required to reach a high potential, the higher the voltage of the column data line node is, the larger the supplementary current is, and the larger the supplementary current is, the higher the rate of the column data line node rising to a target value is; when the memory unit is in an erasing state, the pull-down current of the memory unit to the column data line node is large, the column data line node is required to reach a low potential, the lower the voltage of the column data line node is, the smaller the supplementary current is, and the smaller the supplementary current is, the higher the rate of the column data line node dropping to a target value is. The invention can improve the change rate of the column data line nodes, thereby improving the reading rate.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit, and more particularly, to a charge transfer type sense amplifier.
Background
As shown in fig. 1, it is a circuit diagram of a conventional charge transfer type sense amplifier; the conventional charge transfer type sense amplifier includes:
the grid electrode of the NMOS tube n101 is connected with a clamping voltage VCLAMP and keeps a starting state; the source is connected to a bit line node Bl through which a memory cell (cell)102 is connected.
The source of the PMOS transistor p101 is connected to a power voltage VDD, the drain of the PMOS transistor n101 is connected to the drain of the NMOS transistor n101 and both connected to the column data line node VD, and the gate of the PMOS transistor p101 is connected to a control signal PBIAS, which is a fixed voltage, such as a bias voltage through a current mirror.
The positive phase input end of the comparator 101 is connected with the column data line node VD, the negative phase input end is connected with the reference voltage VREF, the output end is used as the output end of the charge transfer type sensitive amplifier, and the output signal DOUT is formed by comparing the VD and the VREF.
After the precharge is completed, the VD voltage is charged to the power supply voltage VDD, and in the comparison stage when the memory cell 102 is read, the conventional charge transfer type sense amplifier:
if the memory cell is a write cell (Program cell, pcell), the memory cell 102 is not turned on, the current is theoretically zero, the bit line voltage is unchanged, the node BL voltage is unchanged, the node VD voltage is kept at VDD, and the node VD voltage is greater than the reference voltage VREF.
If the memory cell is an Erase cell (Erase cell, e-cell), the memory cell 102 is turned on, i.e., there is a current, the bit line voltage will decrease, i.e., the voltage of the node BL will decrease, resulting in a decrease in VD voltage, which is smaller than the reference voltage VREF.
In the latch phase, the voltage of the node VD is compared with the reference voltage VREF, and results of 0 and 1 are obtained.
However, in practical situations, the p-cell still has a small current, the current increases after the p-cell decays, and the VD voltage slowly decreases. Therefore, the PMOS transistor p101 is needed to provide the compensation current, which PBIAS is controlled externally, and the compensation current can avoid the drop of VD voltage.
In the prior art, the current value of the compensation current is set to a value intermediate between the e-cell current and the p-cell current. The disadvantages of this arrangement are: the compensation current is beneficial to reading the p cell, and the VD voltage cannot be reduced; it is not good for reading e-cells, which results in slow VD voltage drop and reduced reading speed.
Disclosure of Invention
The invention aims to provide a charge transfer type sensitive amplifier which can improve the change rate of a column data line node so as to improve the reading rate.
In order to solve the above technical problem, the present invention provides a charge transfer type sense amplifier, including:
a compensation circuit unit connected between a supply voltage and a column data line node, the compensation circuit unit to provide a compensation current during a comparison phase.
And the output unit reads the voltage signal of the column data line node and then outputs data.
And the bit line adjusting unit is connected between the output end of the compensation circuit unit and a bit line node of the memory unit, and provides a switch to connect the bit line node and the column data line node.
The compensation circuit unit is in a structure that the compensation current can change in a self-adaptive mode according to the voltage of the column data line node.
When the memory unit is in a programming state, the pull-down current of the memory unit to the column data line node is small, the column data line node is required to reach a high potential, the higher the voltage of the column data line node is, the larger the supplementary current is, and the larger the supplementary current is, the larger the rate of the column data line node rising to a target value is.
When the memory unit is in an erasing state, the pull-down current of the memory unit to the column data line node is large, the column data line node is required to reach a low potential, the lower the voltage of the column data line node is, the smaller the supplementary current is, and the smaller the supplementary current is, the larger the rate of the column data line node dropping to a target value is.
In a further improvement, the compensation circuit unit includes a first mirror path and a second mirror path that are in mutual communication.
The current of the output of the first mirror path is the compensation current and is connected to the column data line node.
The current output end of the second mirror image path is connected to the drain electrode of a first NMOS tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected with the column data line node.
The higher the voltage of the column data line node is, the larger the source-drain current of the first NMOS transistor is, the larger the current of the second mirror path is, and the larger the current mirrored to the first mirror path by the second mirror path is.
The higher the voltage of the column data line node is, the larger the source-drain current of the first NMOS transistor is, the larger the current of the second mirror path is, and the larger the compensation current formed by the current mirror of the second mirror path to the first mirror path is.
The smaller the voltage of the column data line node is, the smaller the source-drain current of the first NMOS tube is, the smaller the current of the second mirror image path is, and the smaller the compensation current formed by the current mirror image of the second mirror image path to the first mirror image path is.
In a further improvement, the first mirror path includes a first PMOS transistor, and the second mirror path includes a second PMOS transistor.
The source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both connected with power supply voltage.
The grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube are all connected with the drain electrode of the first NMOS tube.
And the drain electrode of the first PMOS tube outputs the compensation current.
In a further improvement, a first resistor is connected between the drain of the first PMOS transistor and the column data line node.
In a further improvement, the bit line adjusting unit includes a second NMOS transistor, the second NMOS transistor is used as a switch for connecting the bit line node and the column data line node, a source of the second NMOS transistor is connected to the bit line node, and a drain of the second NMOS transistor is connected to the column data line node; and the grid electrode of the second NMOS tube is connected with a clamping voltage.
In a further improvement, the output unit includes a comparator, a non-inverting input terminal of the comparator is connected to the column data line node, and an inverting input terminal of the comparator is connected to a reference voltage.
The size of the supplementary current provided by the compensating circuit unit of the charge transfer type sensitive amplifier is directly controlled by the voltage of the column data line node, so that the compensating current can be adaptively changed according to the voltage of the column data line node, when the memory unit is in a programming state, the supplementary current can be increased, the rising rate of the column data line node is increased, and the reading rate of the memory unit in the programming state can be increased; when the memory unit is in an erasing state, the complementary current can be reduced so as to increase the descending speed of the column data line node, and therefore the reading speed of the memory unit in the erasing state can be increased; therefore, the invention can improve the change rate of the column data line nodes, thereby improving the reading rate.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
fig. 1 is a circuit diagram of a conventional charge transfer type sense amplifier;
fig. 2 is a circuit diagram of a charge transfer type sense amplifier according to an embodiment of the present invention.
Detailed Description
As shown in fig. 2, the circuit diagram of the charge transfer type sense amplifier according to the embodiment of the present invention is shown, and the charge transfer type sense amplifier according to the embodiment of the present invention includes:
a compensation circuit unit connected between a supply voltage VDD and a column data line node VD, the compensation circuit unit for providing a compensation current during a comparison phase.
And the output unit reads the voltage signal of the column data line node VD and then outputs data DOUT. Preferably, the output unit includes a comparator 1, a non-inverting input terminal of the comparator 1 is connected to the column data line node VD, and an inverting input terminal of the comparator 1 is connected to a reference voltage VREF.
And the bit line adjusting unit is connected between the output end of the compensation circuit unit and a bit line node BL of the memory unit 2, and the bit line adjusting unit provides a switch to connect the bit line node BL with the column data line node VD. Preferably, the bit line adjusting unit includes a second NMOS transistor n0, the second NMOS transistor n0 is used as a switch for connecting the bit line node BL and the column data line node VD, a source of the second NMOS transistor n0 is connected to the bit line node BL, and a drain of the second NMOS transistor n0 is connected to the column data line node VD; the grid electrode of the second NMOS transistor n0 is connected with a clamping voltage VCLAMP.
The compensation circuit unit is in a structure that the compensation current can change in a self-adaptive manner according to the voltage of the column data line node VD.
When the memory unit 2 is in a programmed state, the pull-down current of the memory unit 2 to the column data line node VD is small, the column data line node VD is required to reach a high potential, the higher the voltage of the column data line node VD, the larger the supplementary current, the larger the rate at which the column data line node VD rises to a target value.
When the memory unit 2 is in an erase state, the pull-down current of the memory unit 2 to the column data line node VD is large, the column data line node VD is required to reach a low potential, and the lower the voltage of the column data line node VD, the smaller the supplementary current is, the larger the rate of the column data line node VD dropping to a target value is.
In an embodiment of the present invention, the compensation circuit unit includes a first mirror path and a second mirror path that are mutually conducted.
The current of the output of the first mirror path is the compensation current and is connected to the column data line node VD.
The current output end of the second mirror image path is connected to the drain electrode of a first NMOS transistor n1, the source electrode of the first NMOS transistor n1 is grounded GND, and the gate electrode of the first NMOS transistor n1 is connected to the column data line node VD.
The higher the voltage of the column data line node VD is, the larger the source-drain current of the first NMOS transistor n1 is, the larger the current of the second mirror path is, and the larger the current mirrored to the first mirror path by the second mirror path is.
The higher the voltage of the column data line node VD is, the larger the source-drain current of the first NMOS transistor n1 is, the larger the current of the second mirror path is, and the larger the compensation current formed by the current mirror of the second mirror path to the first mirror path is.
The smaller the voltage of the column data line node VD is, the smaller the source-drain current of the first NMOS transistor n1 is, the smaller the current of the second mirror path is, and the smaller the compensation current formed by the current mirror of the second mirror path to the first mirror path is.
Preferably, the first mirror path includes a first PMOS transistor p1, and the second mirror path includes a second PMOS transistor p 0.
The source electrode of the first PMOS transistor p1 and the source electrode of the second PMOS transistor p0 are both connected with a power supply voltage VDD.
The grid electrode of the first PMOS tube p1, the grid electrode of the second PMOS tube p0 and the drain electrode of the second PMOS tube p0 are all connected with the drain electrode of the first NMOS tube n 1.
The drain of the first PMOS transistor p1 outputs the compensation current.
And a first resistor R1 is also connected between the drain electrode of the first PMOS tube p1 and the column data line node VD.
The magnitude of the supplementary current provided by the compensation circuit unit of the charge transfer type sensitive amplifier in the embodiment of the invention is directly controlled by the voltage of the column data line node VD, so that the supplementary current can be adaptively changed according to the voltage of the column data line node VD, when the memory unit 2 is in a programming state, the supplementary current can be increased, the rising rate of the column data line node VD is increased, and the reading rate of the memory unit 2 in the programming state can be increased; when the memory unit 2 is in an erasing state, the complementary current can be reduced so as to increase the descending rate of the column data line node VD, thus increasing the reading rate of the memory unit 2 in the erasing state; therefore, the embodiment of the invention can improve the change rate of the line data line nodes VD, thereby improving the reading rate.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (5)
1. A charge transfer type sense amplifier, comprising:
a compensation circuit unit connected between a supply voltage and a column data line node, the compensation circuit unit for providing a compensation current during a comparison phase;
the output unit reads the voltage signal of the column data line node and outputs data;
a bit line adjusting unit connected between an output terminal of the compensation circuit unit and a bit line node of the memory unit, the bit line adjusting unit providing a switch to connect the bit line node and the column data line node;
the compensation circuit unit is in a structure that the compensation current can change in a self-adaptive manner according to the voltage of the column data line node;
when the memory unit is in a programming state, the pull-down current of the memory unit to the column data line node is small, the column data line node is required to reach a high potential, the higher the voltage of the column data line node is, the larger the compensation current is, and the larger the compensation current is, the higher the rate of the column data line node rising to a target value is;
when the memory unit is in an erasing state, the pull-down current of the memory unit to the column data line node is large, the column data line node is required to reach a low potential, the lower the voltage of the column data line node is, the smaller the compensation current is, and the smaller the compensation current is, the larger the rate of the column data line node dropping to a target value is;
the compensation circuit unit comprises a first mirror image path and a second mirror image path which are mutually conducted;
the current of the output of the first mirror path is the compensation current and is connected to the column data line node;
the current output end of the second mirror image path is connected to the drain electrode of a first NMOS tube, the source electrode of the first NMOS tube is grounded, and the grid electrode of the first NMOS tube is connected with the column data line node;
the higher the voltage of the column data line node is, the larger the source-drain current of the first NMOS tube is, the larger the current of the second mirror image path is, and the larger the current mirrored from the current of the second mirror image path to the first mirror image path is;
the higher the voltage of the column data line node is, the larger the source-drain current of the first NMOS tube is, the larger the current of the second mirror image path is, and the larger the compensation current formed by the current mirror image of the second mirror image path to the first mirror image path is;
the smaller the voltage of the column data line node is, the smaller the source-drain current of the first NMOS tube is, the smaller the current of the second mirror image path is, and the smaller the compensation current formed by the current mirror image of the second mirror image path to the first mirror image path is.
2. The charge transfer type sense amplifier according to claim 1, wherein: the first mirror image path comprises a first PMOS tube, and the second mirror image path comprises a second PMOS tube;
the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both connected with power supply voltage;
the grid electrode of the first PMOS tube, the grid electrode of the second PMOS tube and the drain electrode of the second PMOS tube are all connected with the drain electrode of the first NMOS tube;
and the drain electrode of the first PMOS tube outputs the compensation current.
3. The charge transfer type sense amplifier according to claim 2, wherein: and a first resistor is connected between the drain electrode of the first PMOS tube and the column data line node.
4. The charge transfer type sense amplifier according to claim 1, wherein: the bit line adjusting unit comprises a second NMOS tube, the second NMOS tube is used as a switch for connecting the bit line node and the column data line node, the source electrode of the second NMOS tube is connected with the bit line node, and the drain electrode of the second NMOS tube is connected with the column data line node; and the grid electrode of the second NMOS tube is connected with a clamping voltage.
5. The charge transfer type sense amplifier according to claim 1, wherein: the output unit comprises a comparator, the positive phase input end of the comparator is connected with the column data line node, and the negative phase input end of the comparator is connected with a reference voltage.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710851521.1A CN107665718B (en) | 2017-09-19 | 2017-09-19 | Charge transfer type sense amplifier |
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| CN201710851521.1A CN107665718B (en) | 2017-09-19 | 2017-09-19 | Charge transfer type sense amplifier |
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| CN107665718B true CN107665718B (en) | 2020-08-11 |
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| US10522226B2 (en) | 2018-05-01 | 2019-12-31 | Silicon Storage Technology, Inc. | Method and apparatus for high voltage generation for analog neural memory in deep learning artificial neural network |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508966A (en) * | 1992-07-16 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Sense amplifier circuit for semiconductor memory device |
| CN1845253A (en) * | 2006-04-28 | 2006-10-11 | 清华大学 | Sensitive amplifier circuit for quickflashing memory |
| CN102013267A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | Memory and sensitive amplifier |
| CN106601278A (en) * | 2016-12-19 | 2017-04-26 | 佛山中科芯蔚科技有限公司 | Sense amplifier |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5607870B2 (en) * | 2008-04-25 | 2014-10-15 | ピーエスフォー ルクスコ エスエイアールエル | Current sensing circuit and semiconductor memory device having the same |
| US8830759B2 (en) * | 2011-12-09 | 2014-09-09 | Atmel Corporation | Sense amplifier with offset current injection |
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2017
- 2017-09-19 CN CN201710851521.1A patent/CN107665718B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5508966A (en) * | 1992-07-16 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Sense amplifier circuit for semiconductor memory device |
| CN1845253A (en) * | 2006-04-28 | 2006-10-11 | 清华大学 | Sensitive amplifier circuit for quickflashing memory |
| CN102013267A (en) * | 2009-09-07 | 2011-04-13 | 上海宏力半导体制造有限公司 | Memory and sensitive amplifier |
| CN106601278A (en) * | 2016-12-19 | 2017-04-26 | 佛山中科芯蔚科技有限公司 | Sense amplifier |
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