TW200406831A - Method for fabricating silicide - Google Patents

Abstract

A processing method for fabricating silicide is provided. First of all, a semiconductor structure having a semiconductor surface and an insulation surface is provided. Next, an epitaxial layer on the semiconductor surface is formed. And, the semiconductor structure is treated. The treat step is that the removal rate of the insulation surface is faster than the removal rate of the epitaxial layer. Then, a metal layer on the epitaxial layer is formed. Finally, heating the epitaxial layer forms silicide. The treatment step prevents the insulation surface from the formation of the silicide so as to reduce the degradation of device characteristics.

Description

200406831 V. Description of the invention (1) 1. [Technical field to which the invention belongs] The present invention relates to a method for semiconductor dream shoes and a groin coat method, in particular to a method for improving the process of silicided metal. J 疋 About a type II. [Prior art] Due to the reduction in the size of the semiconductor process, parasitics and chip resistance will increase. In order to reduce parasitic resistance ★ Second: resistance Silicide) process is widely noticed and enjoyed. Five genus (chemical metals, two ... (CoS12) and two dreams in two = same factory = value and learning. They can be applied to "1 standard: evening: clothing (SALICIDE) and in different The silicidated metal has a low resistivity with "significantly dry out". It is also required for improving thermal stability and epitaxial formation of chemically formed metals. Θθ, the first A to D graphs show the conventional technology process Sequence. The first alpha diagram shows a basic semiconductor structure 101, which includes a substrate 10 with two doped regions 103A, 103B, a gate electrode 104 with an upward surface and a plurality of sides, and a spacer. ] [05 is located on each side of the gate electrode 104 and a part of the doped region 103A is left, and 103B is exposed, and an isolation device or a number of insulators ι〇6Α, 106B to block other semiconductor structures. Figure B shows the deposition of an epitaxial silicon (

Epi taxial Si 1 icon) 111, exposed in the doped region ι〇3Α, 103B

Part and the upward surface of the gate electrode 104; at the same time, a part of the epitaxial silicon and the contaminant 112 are attached to the spacer 105 and several insulators 106A

Page 5 200406831 V. Description of the Invention (2), 106B. The first picture C shows the deposition of a metallic cobalt (c0b on the worm crystal stone m. Finally, the first picture D shows a heating,) 121 Thermal Tempering (RTA) is widely used in the King of Silicon Silicide, , And fast silicidating metal 1 3 1 steps. Clothing and formation Refer to the first D figure, a thick silicon silicide causes a leakage current and low reliability. The thick crystalline silicon that is to be joined from the substrate to the substrate will be like a thick silicided metal, and the leakage current will be combined. There is also a silicidation on the gap wall: the leakage current will be caused by the idler electrode to the doped region;; = leakage causes the semiconductor to fail. i-decision action even 3. [Summary of the invention] In view of the above-mentioned background of the invention, there are many shortcomings caused by the work β insulator. Ben # 于 于 纟 巴 缘边 边墙 and impurities on it, thereby improving the process edge spacer and insulators. A method for manufacturing petrochemical metal has been unveiled. First, a semiconductor structure has one: In the following embodiments, the structure Wherein, the processing step: =; = The reason, the removal rate of the semiconductor to the remote crystal layer, the removal rate of the missing bar and surface is greater than that of the semiconductor structure of the crystal layer, the most J ”-metal layer In the formation of the worm take Jun 'heating to make the epitaxial layer and the gold

Page 6 V. Description of the invention (3) Formed by the action of the metal layer # On the insulating surface, the processing step is reduced by two to avoid the formation of silicided metal and the characteristics of low components. 4. [Implementation] The following processes and Fang Niu. The existing dry circuit used in the present invention includes a complete process for manufacturing integrated circuits to assist the description of the present invention. Moreover, the following = is only used as a key reference here to control, and its role is only in the context. The related diagrams in the text are not drawn to scale to show the features of the method of the present invention. The contents of the disclosure can be uncovered through the following embodiments. First, — Λ a 1 ..., the related narrative surface. Secondly, a lithium :: structure has a semiconductor surface and-insulates the semiconductor structure, and: the middle = on the semiconductor surface ", processing J = on the" layer; ": the table :: removed Layer 'and = = 冓, and finally, the force: hot metal forms the L-cut metal. This processing step avoids cutting the surface of the bar, and the surface, so as to reduce the characteristics of the component. The consistent example of this matter is shown in the traditional Chinese-English diagram, which shows that any one can be used, and the "quotient" is not in the first-second diagram to the second-second diagram. The second method is to use the basic semiconductor structures 20 1, ^ ^ ^, 203A, and 203B produced by the method of arbitrarily, and 2 " 2 Yu Η = two majority side gate electrodes 204,- Spacer 20 5 digits J. ° " ^ 4 on the side with a part of the doped regions 203A, 203B blunders, and most insulators 206A, 206β to isolate other semiconductors 200406831 5 4. Description of the invention (4) bulk structure. For the present invention, the substrate 200 may be any suitable semiconductor material, such as Shi Xi (Si), germanium (Ge), and silicon germanium (Si Ge), and This embodiment is Shi Xi. The doped regions 203A and 203B can be divided into N-type or P-type dopants in the substrate 202, and N-type dopants are used in this embodiment. Gate The electrode 2 04 may be polycrystalline, and in this embodiment, polycrystalline silicon (poly-silicon) is used. The partition wall 2 05 and the insulator 2064, 2 0 66 may be silicon oxide or nitride. Silicon type 'in this embodiment is silicon dioxide (Si02). In this embodiment, it is necessary to pay attention to the exposed areas of the doped regions 230A, 203B and the upward surface of the gate electrode 204 to form A semiconductor surface In addition, the exposed area of the partition wall 205 and the exposed portions of the insulators 206A and 206B form an insulating surface. In the first figure, a stupid layer 211 is like stupid stone (Epitaxiai SU ^ C0n). ) Layer is formed on the semiconductor surface. Epitaxial silicon and contaminants 2 1 2 may be deposited and deposited on the surface of selective epitaxial silicon. In order to avoid epitaxial silicon and contaminants 2 丨2 is attached to the insulating surface ^, the following steps provide a method to remove epitaxial silicon and contaminants 212. Figure 2C shows the removal of the epitaxial 2 attached to the insulating surface. During this removal process It is the use of dilute chlorine acid (Du = and the etching process in this embodiment, removing the wall crystal ... the dirty has been moved ... two AI, the epitaxial silicon on the silicon surface today is removed less than 10 A. In other words, the removal rate of the layer in the present invention is slower than the removal rate of the insulating surface. In this specific embodiment, the removal rate, such as the rate of money engraving, is to be considered 200406831 V. Description of the invention (5 ) ~ _- Concerned. For the wet etching method, the dilute hydrogen f acid was chosen because it has The high removal rate of stone dioxide (insulating surface) and epitaxial silicon. In another embodiment, a buffered silicon oxide etching solution (boe, Buffer Onde etcher) is also used in the wet etching method. There are many different kinds of regulators that can target different insulation surfaces and semiconductor surfaces. On the other hand, for dry etching, hydrogen compounds can also be used in the present invention. In short, no matter what kind of wither is selected, as long as the removal rate of the insulating surface is faster than that of the epitaxial layer. The second diagram D shows that a metal layer 231 (such as a wrong metal layer) is formed on the epitaxial silicon 211 by an appropriate method (such as a deposition method). Finally, the second diagram e is a heating process on the semiconductor structure. In this invention, Rapid Thermal Tempering (RTA) is a step that is commonly used in the process of forming silicided metals and forming silicided metals. One step for rapid thermal tempering in accordance with this embodiment is to form a silicide metal cobalt silicide (cosi 2) at a temperature close to 650 degrees Celsius for about 20 minutes. For other applications such as titanium, its rapid thermal tempering has two Steps. The first step is tempering (A nnea 1 ing). For example, the temperature is close to 650 degrees Celsius for about 20 minutes in a nitrogen (n 2) gas, where nitrogen and titanium react to form titanium nitride (TiN 2). On the metal surface, at the same time titanium reacts with epitaxial silicon to form silicided metal in the area directly contacting epitaxial silicon. If the temperature is between 650 and 750 degrees Celsius, titanium silicide with a high resistance phase is formed faster than titanium nitride in the epitaxial silicon exposed area. At the same time, the reaction that has nothing to do with epitaxial silicon occurs at the same time. Metal-covered silicon dioxide or silicon nitride. versus

200406831 V. Description of the invention (6) The metal deposit in contact with the insulating surface mainly contains titanium nitride and unreacted titanium. The use of peroxide removes the titanium nitride and unreacted ”mentioned above, leaving the silicided metal region. Comparing the first D picture (known technique) and the second E picture, in the second E picture, we can see that there is no residue attached to the exposed insulating surface and the petrified metal has only become thinner. This means that the bridge leakage current has been improved and the semiconductor structure has become more reliable. Examples of revealing the technology of the present invention are from the consideration of this specification and the application of the present invention. And here is only a typical example of considering the specifications. The scope of the actual request and the spirit of the present invention are listed in the scope of the subsequent patent claims.

Page 10 200406831 Schematic illustrations Figures A through D show representative representations of conventional silicidated metal structure manufacturing; and Figures A through E show second Representative diagram; Representative symbols of main parts: 101 semiconductor structure 102 substrate 103A doped region 1 0 3 β doped region 104 gate electrode 105 spacer 1 0 6 Α insulator 10 6B insulator 111 Epitaxial silicon and contaminants 121 metal layer 1 3 1 silicided metal 201 semiconductor structure 2 0 2 substrate 2 0 3A doped region 20 3B doped region 204 gate electrode

Page 11 200406831 Brief description of the drawing 2 0 5 Partition wall 2 0 6 A Insulator 2 0 6 B Insulator 211 Stupid stone 212 Epitaxial silicon and contaminants 231 Metal layer 2 41 Petrochemical metal

Page 12

Claims (1)

200406831 VI. Application Patent Scope 1. A processing method for forming si 1 pesticide, comprising: providing a semiconductor structure having a semiconductor surface and an insulating surface; forming an epitaxial layer on the semiconductor On the surface; processing the semiconductor structure, wherein the removal rate of the insulating surface in the processing step is greater than the removal rate of the epitaxial layer; forming a metal layer on the stupid layer; and heating the stupid layer To form a petrified metal. 2. The method for forming a silicide metal as described in item 1 of the scope of the patent application, wherein the step of providing the semiconductor structure includes forming a substrate and a gate electrode to form a part of the semiconductor structure. 3. The method for forming a silicide metal as described in item 2 of the scope of the patent application, wherein the step of forming the semiconductor surface includes forming a doped region on the substrate to form a portion of the semiconductor surface. 4. The method for forming a silicide metal as described in item 2 of the scope of the patent application, wherein the step of forming the semiconductor surface includes forming an upward surface on the gate electrode to form a part of the semiconductor surface. 5. The method for forming a silicided metal as described in item 2 of the scope of the patent application, wherein the step of forming the insulating surface includes forming a spacer at an edge of the gate electrode to form a part of the insulating surface. Page 13 200406831 6. Scope of patent application 6. The method for forming a silicided metal as described in item 2 of the scope of patent application, wherein the step of forming the insulating surface includes forming an isolation element (is ο 1 ati ο ndevice) on the The substrate constitutes a part of the insulating surface. 7. The method for forming a silicided metal as described in item 1 of the scope of patent application, wherein the step of forming the epitaxial layer includes forming an epitaxial silicon layer. 8. The method for forming a silicided metal as described in item 1 of the scope of the patent application, wherein the step of forming the stupid layer includes forming a stupid crystal. 9. The method for forming a silicided metal as described in item 1 of the scope of the patent application, wherein the processing step includes removing a portion of the insulating surface in a wet manner. 10. The formation of the silicided metal as described in item 9 of the scope of the patent application A processing method, wherein the wet etching method uses a fluorine-containing solvent. 11. The method for forming a silicided metal as described in item 1 of the scope of patent application, wherein the processing step includes removing a part of the insulating surface by dry etching. 12. The process for forming the silicided metal as described in item 11 of the scope of patent application Processor Page 14 200406831 6. Method of applying for a patent, in which the dry etching method uses a fluorine-containing compound. 13. The method for forming a silicided metal as described in item 1 of the scope of the patent application, wherein the step of forming the metal layer includes forming a titanium metal layer. 14. The method for forming a silicided metal as described in item 1 of the scope of the patent application, wherein the step of forming the metal layer includes forming a starting metal layer. 15. A method for forming a silicided metal (s i 1 i c i de), comprising: providing a silicon substrate; Forming a polycrystalline stone gate electrode on the stone substrate; forming an insulating spacer on the side wall of the polycrystalline silicon gate electrode; forming an epitaxial layer on the silicon substrate and the polycrystalline silicon gate electrode On the upper surface; etching a part of the insulating spacer; forming a metal layer on the epitaxial layer; and heating the epitaxial layer to form a silicide metal on the upper surface of the polycrystalline silicon gate electrode and on the stone substrate . 16. The method for forming a silicided metal as described in claim 15 of the patent application, wherein the remaining steps include performing a wet silver engraving with a fluorine-containing solvent. 17. The method for forming a silicided metal as described in claim 15 of the application, wherein the remaining step includes performing a dry remaining step of the fluorine-containing compound. Page 15