TW200405272A - Bit synchronization detection means - Google Patents

Abstract

Detection means for detecting information in a signal, comprising integration means for integrating the signal over time such that the integration means is periodically reset at about the start time reference of a periodic time interval; and a sample-and-hold circuit for periodically sampling and holding the integrated signal (int) at about an end time reference of the periodic time interval and thereby delivering a farther signal (fs). The detection means further comprises a chain (CHDL) of signal time delay elements, an input of the chain (CHDL) being coupled to receive the further signal (fs); and combining means (CBMNS) having combining inputs coupled to signal taps of the chain (CHDL), such that the number of the combining inputs and the position of coupling the combining inputs to the signal taps of the chain (CHDL) correspond to the information in the signal.

Description

200405272 Description of the invention: [Technical field to which the invention belongs] The present invention discloses a detection device for detecting information in a signal, which includes an integration device for integrating the signal over time, so as to approximate the time interval Periodically reset the integration device at a start time reference; and a periodic acquisition and hold of the integration signal at an end time reference of approximately a periodic time interval, and thereby send a sample and hold of a further signal Circuit. [Previous technology] The detection device can be displayed from the general technology level seen in the figure. Such known detection devices can be used for various purposes. In the example of Figure 丨, the device is used to traverse the address data in a so-called wobble signal wbl originating from a magnetic disk (such as an optical disk). The known detection device of FIG. 1 includes a signal for multiplying the wobble signal wbl by a wobble reference signal wblrf, thereby providing a signal multiplier μ as a result; coupled with the known detection device for receiving The signal s also provides the integration device iNT for the integration signal int as the integration result; a sampling and holding circuit coupled to the known detection device for receiving the integration signal ratio and providing a further signal fs as a result SH; and a comparator CMp coupled to the known detection device for receiving the further signal pseudo and providing a comparator output signal cmp. The signal s can be directly coupled to the integrator INT to allow integration in the analog domain. Alternatively, the signal s is first digitized by an analog-to-digital converter ADC, and then coupled to the integration device INT to perform integration in the digital field. It should be noted that the combination of the integration device INT and the sample and hold circuit 85643 200405272 SH is usually referred to in the literature as an "integration and dump filter". The known detection devices shown in FIG. 1 are further described with reference to the signal charts I, Π, in, iv, and V of FIG. 2. The detection of a synchronization bit in the wobble kai wbl is shown in this example, and the synchronization bit will be further represented as bitsync. Figure I shows the wobble signal wbi. The wobble signal wbl starts at time t0 with 3 consecutive sine wave periods. Then at the moment. An inverse sine-wave period follows between and ^. The period of the reverse sine wave is one bitsync. From time u to, the wobble signal wbl continues to be normal, that is, as if the bitsync did not occur. Similarly, between time 1; 7 and 1: 8, there is a bitsync in the wobble signal wbl. Figure II shows the wobble reference signal wblrf which is actually equivalent to the wobble signal wbl, in order to replace each bitsync with a non-reverse sine wave period to obtain a monotonous wobble signal. The generation of the wobble reference signal wblrf can be achieved by all known methods, such as using a PLL (Phase Locked Loop). Figure III shows the signal s', which is the mathematical product of the wobble signal wbi and the wobble reference signal wblrf. This signal s becomes negative only when bitsync is present in the wobble signal wbl. Therefore, in principle, detection of bitsync can be achieved by directly coupling signal 3 to a comparator. However, in practice, the signal s does not have the ideal waveform shown in the graph II *. In some cases, the signal S is a (ten) noisy signal. As a result, the comparator can generate an error bitsync detection. To do this, first integrate this signal 3 periodically. The integral signal mt is shown in Figure iv. The length of a time interval corresponds to a sine wave period. The start and end times of the time interval Ti are denoted as Tb and τE, respectively. With a start / reset signal STRS (as shown in the figure) at approximately every time; the port time TB resets the integration device INT, and the sample and hold circuit 85643

i 4 B 200405272 SH enters the hold state. The sample and hold circuit SH enters the sampling state at (very close) W 'exactly every termination time τE. The sample and hold circuit provides the further signal fs of the synthesis, as shown in Figure V. Now, if the integration signal fs is coupled to a comparator CMP, a more reliable bitsync detection can be achieved. Sometimes 'the integration signal int still contains a lot of noise, so that the comparator cmp still generates an incorrect decision'. False detection or missing bitsync. [Summary of the Invention] Therefore, an object of the present invention is to provide a bitsync detection device with improved reliability for detecting a correct position of a bitsync. For this reason, according to the present invention, the detection device of the type defined in the preamble of the present invention is characterized in that the detection device includes a series of signal delay elements, and an input terminal of the read series is coupled to receive the further signal; and A combination device having a combination input terminal coupled to a series of signal taps, the number of these input terminals and the position of the light input of the combination input terminal and the series signal tap correspond to the information in the signal. κinter 'is now a series of signal delay devices and combined devices to replace the comparators used in known detection devices. Therefore, by considering a large number of swing cycles, a bitsync can be measured to achieve (statistical) calculation. The proper coupling between the combined input and the signal tap depends on the characteristics of the information in the signal. Therefore, a "pattern matching principle" for detecting bitsync or other special characteristics of information can be realized. In known detection devices, it is determined whether a bitsync is present in the wobble signal after each wobble period (sine cycle). Blood ψ ρ, which is in contrast 85643 200405272 The new detection device is 膺 τ! Swing cycle. The result is achievable-more reliable bitsync detection (due to the increased s / n ratio). The embodiment of the present invention is characterized in that the information includes a synchronization character portion followed by one or a plurality of possible types of data bit portions followed by synchronization, and the combining device transmits a The bit synchronization part of the one-character synchronization part is combined with the output signal of the banker, and is followed by a possible type of data bit part. Lingo-gate & Send combined output signal. Generally, there are two types of data bit portions, a type of data bit portion representing a logic "0", and a type of data bit portion representing a logic "i". These types of < data bit portions will be further represented as data ζ · and data ONE respectively. Another feature of the present invention is that the side device includes a processing device for processing all the combined output signals. The completion of the device processing is such that within a predetermined number of time intervals, the lowest (highest) signal value of all the signal values of the combined output signals at each land MM ^ Λ, and the corresponding time The position number accompanying the interval t is detected, and is lowered within a predetermined number of time intervals (the position number corresponding to the highest M 测 signal value is considered to be followed by the bit synchronization portion of the synchronization character portion. Correct position. "Dagger, the so-called" pattern matching principle π is implemented. A further embodiment of the present invention is characterized in that the device "is used for the step-by-step processing of the bit portion followed by the -word step portion. The correct position transmitted by the processing device of the synchronization part is regarded as the correct position. The further processing device is substantially compared with the predetermined number of sleep R < inter-call intervals. On 342 85643 -9- 200405272 for a longer period of time, the position of the bit synchronization part followed by a character synchronization part is detected as the correct position, and the further processing device includes a plus / Down counter, whenever the bit synchronization followed by a character synchronization part is deemed to be correct at the < position expected by the further processing device, the registration value is increased (decreased) by a unit value ) To the predetermined reference value of the up / down counter, and whenever a position deemed correct by the bit sync portion followed by a character sync portion does not appear at the position expected by the further processing device, a unit is used The registration value is reduced (increased), and the further processing device transmits a bit-synchronized portion of the character synchronization part, which has an improved position reliability. The operation method of the further processing device can achieve the Improved position reliability, where as long as the registered value is greater than (less than) another predetermined reference value, a character is synced after a character is transmitted by the further processing device The position of the synchronization portion of the bit is the same as that expected by the progressive processing device, and when the registered value is equal to another predetermined reference value, the bit of the synchronization portion of the word 7L is transmitted by the further processing device. The position of the synchronization part is the same as the position transmitted by the processing device. In the latter case, the up / down counter is reset. Exactly, the bitsync detection has improved reliability, and bitsyncw may be missed or detected. By using the further processing device, the reliability can be further improved. The further processing device basically operates as an electronic, flywheel. Therefore, the missing bitsync may or may not have, the flywheel, the expected position The bitsync, directly via the "flywheel," is added. If bitsync error detection occurs too frequently, it may be caused by signal changes. 85643 -10-200405272 So reset the "flywheel". The present invention also discloses a device substantially as defined in item 5 of the scope of patent application, and more particularly, an optical disc drive and magneto-optical drive as defined in item 6 and 7 of the scope of patent application, respectively. The present invention also discloses a method for detecting address data in a signal, which includes the following steps: ~-Periodically integrates the signal over time within a time interval,-Samples and holds at approximately the end of every time interval The integral signal, thereby transmitting a further signal, _delaying the further signal ', thereby providing a plurality of delayed signals with various delays,-at least in a sense, combining the signal with the address data consistent with the signal. The preferred implementation of this method is as described in item 9 and item H) of the patent scope. The principle of the 胄 detection device can also be used when there is no integrating device. It is described in detail in item 11 of the patent scope. [Embodiment] FIG. 3a shows a disc-shaped recording stage including continuous tracks 9 for recording, and the tracks are arranged in a spiral pattern of circle 3. The circles can also be arranged non-spirally. The track 9 on the record carrier can be included in a trajectory table (for example)-the groove 4 is pre-engraved so that the read / write head can move along the track during scanning. For example, it can also be formed by the regular trajectory of the ruled-line knife-blade. The sub-track P periodically causes a signal to be generated in the temple service track system. 85643 -11- 200405272 3b shows a line b_b along the record carrier. In cross section, a recording layer 7 and a protective layer 7 cover a transparent substrate 5. The pre-etched grooves 4 can also be arranged on the surface of a groove or have different material characteristics from their surroundings. The recording layer 6 can be deposited in an optical, magneto-optical, or magnetic manner by a device for reading and / or writing information, such as a recordable optical disk or hard disk known to be used in a computer. Figures 3c and 3d show two examples of periodic modulation (swing) of the pre-etched groove. The wobble results in an additional signal in the servo track recorder. A comprehensive description of a CD system containing disc information can be found in US Patent Nos. 4,901,300 and 5,187,699. Figure 4 shows the two-phase swing modulation. An upper track shows the wobble modulation for the character synchronization mode, and a second and third track shows the wobble modulation for the data bit (one of the data bits 7G1 to 51). The predetermined phase pattern is used to represent the synchronization of the synchronization number (ADIP (pre-etched in-groove address) bit synchronization) and a full address word tl (ADIP character synchronization) synchronization, and is used for individual data bits (ADip Shell material — 0 ', and ADIP data =' ι '). The ADIP bit synchronization is represented by a single reverse wobble (Wobble # 0). The ADIP word synchronization is represented by three reverse wobbles that are directly followed by the ADIP bit synchronization, and the data bits have non-reverse wobbles in this area (wobble # 1 to 3). An ADIp data area contains a number of wobbles used to represent a data bit. In Figure 4, the wobble period is numbered 4-7 (ie, wobble # 4 to 7). The wobble phase in the first half of the adip data area is opposite to the wobble phase in the second half of the area. Thus, each bit is represented by two sub-regions with different wobble phases, the so-called biphase. The modulation of the data bits is as follows: ADIP data =, 0 'is represented by two non-reverse wobbles followed by two reverse wobbles, while ADIP data =, Γ is followed by 85543 7 .4 C -12- 200405272 Two non-reverse swings are represented by two reverse swings. In this example, the modulation of the data bits is completely symmetrical, so that the two data bit values have the same probability of error. However, other combinations of wobble and reverse wobble, or other phase values may be used. Monotonic wobble is used after the first data bit, or other data bits can be encoded afterwards. Generally, most of the wobble is not modulated (ie, with a nominal phase) to ensure convenient locking and stable output of the PLL. In this example, these 8 possible modulation swings are followed by 85 non-modulation (ie, monotonic) swings (Swing # 8 to 92). The output frequency of the PLL must be as stable as possible, as the write clock is derived from the output of the PLL during the write process. An ADIP character contains 52 bits, which corresponds to 52 * 93 wobbles, and one wobble is equal to 32 channel bits. In the DVD format, a channel code EFM + is used, and channel bits are clustered in an EFM synchronization frame of 1488 channel bits. Therefore, one ADIP bit corresponds to two EFM sync frames, and the ADIP character corresponds to four sectors in the DVD format. An ECC (Error Correction Code) block in the DVD format contains 16 sectors, so an ECC block corresponds to 4 ADIP characters. Therefore, every four sectors are synchronized using an ADIP character to mark the beginning of a new address (ie, a new full ADIP character). In short, the detection of ADIP characters can be achieved in several steps: Step 1: Lock the swing (with the help of a PLL). Step 2: Detect the position of the bitsync, in other words, detect the position of the ADIP unit. Step 3 ·· Lock the bitsync and use a "flywheel" to keep it locked even if a bitsync is missed. Step 4: Detect the SYNC. 85643 -13-200405272 Step 5: Lock the SYNC and use a π flywheel '' In order to keep the lock even if a wordsync is missed. Step 6: Detect the data bit ZERO or ONE. Step 7: Use ECC to correct errors or obtain such correct addresses. The present invention mainly The focus is on steps 2, 3, 4, 5, and 6. Figure 5 shows a circuit diagram of an embodiment of a detection device according to the present invention. In addition to the comparator CMP, the circuit shown in Figure 1 also belongs to this embodiment The detection device further includes a series of CHDLs of a signal delay element, an input of a series of CHDL coupled to receive further signals fs; and a combination device CBMNS having a combined input coupled to a series of CHDL signal taps, The number of combined inputs and the position where the combined inputs are coupled to the signal taps of the system's 4 CHDL correspond to the information in the signal s. In this example, the information contains a character synchronization section followed by (a further one The step is represented by the bit synchronization part of SYNC), and the possible data ZERO and data ONE types of the data bit part. The combined device CBMNS sends a combined output signal corresponding to the data ZERO and a combined output signal corresponding to the data OKE '' Γ 'and a combined output signal "sync" corresponding to SYNC. The detection device further includes a processing device PRMNS for processing the combined output signal "1π and" sync ". This processing step is implemented such that within a predetermined number of time intervals Ti (as shown in FIG. 2), each time interval is the lowest (highest) signal value in combination with the output signal and the signal value of "ln & nsync" Even the corresponding position number corresponding to the corresponding time interval is detected together. The position number corresponding to the lowest (highest) detection signal value within a predetermined number of time intervals is regarded as the correct position P0 of SYNC. As shown in the graph of 85643 -14- 200405272 in Figure 6, for each swing (swing 0 to 92), the minimum value of ZERO, ONE or SYNC is determined and maintained along with the corresponding position number. In this example, the minimum detection value is -32. This indicates that the SYNC detection takes place at the position P0 which is regarded as correct. The pattern belonging to the 17th swing is shown by '' minimum pattern π in Fig. 5. In this patent application, for example, the definition of the detection device enables the determination of a minimum value (as shown in FIG. 6) and the related “minimum mode” corresponding to the “best pattern matching principle”. However, the definition of the detection device may also enable a maximum value and a related π-maximum mode to be determined. At this time, the "maximum mode" corresponds to the best pattern matching principle π. Fig. 7 shows a circuit diagram of another embodiment of the detection device according to the present invention, wherein the detection device further includes a device for further processing the The further processing device FPRMNS that is transmitted by the processing device PRMNS and is regarded as the correct position Po. This further embodiment involves steps 3 to 6. The further processing device FPRMNS is at a longer time than a predetermined number of time intervals Here, the position of the detected SYNC is regarded as the correct position P0. The further processing device FPRMNS will be further explained with reference to the diagram in FIG. 8, which illustrates such a `` flywheel principle π ''. The further processing device FPRMNS includes a An up / down counter CNT having a registered value RCN, and whenever the deemed correct position P0 of the SYNC appears at the position expected by the further processing device FPRMNS, the registered value RCN is increased (subtracted) by a unit value Small) to the predetermined reference value PRV of the up / down counter CNT. In this example, the predetermined reference value PRV is equal to 4. Whenever the SYNC is considered to be the correct position PG does not appear When the further processing device FPRMNS anticipates the position, the registration value RCN is reduced by a unit value of 85642 -15- 200405272 (increase). The higher the registration value RCN is, the higher the position P transmitted by the further processing device FPRMNS! The higher the "reliability" for correctness, the further processing device FPRMNS transmitting the position Pi of the SYNC (with improved position reliability) is realized by the operation method of the further processing device FPRMNS, as long as the registered value is used in this method When RCN is higher (lower) than another predetermined reference value FPRV, the position Pi of SYNC is the same as the position expected by the further processing device FPRMNS. When the position Pi of SYNC is equal to the position PG transmitted by the processing device PRMNS, the The registration value RCN is then equal to the further predetermined reference value FPRV, in which case the up / down counter CNT is reset. In this example, the other predetermined reference value FPRV is equal to 0. The two π flywheels are actually shown in FIG. 7 ": A BS (Bitsync) n flywheel" and a WS (wordsync) n flywheel ". They have similar operations. Therefore, Fig. 8 only shows the operation of a" flywheel " Process. Consider the graph of Figure 8. The first (upper) column includes positions of PRMNS = 16, FPRMNS = 16, and RCN = 4. RCN = 4 means that Pi has a high reliability π '. As long as RCN is greater than 0, the position ij transmitted by the further processing device FPRMNS remains constant, even if the position P0 changes (this change occurs for the first time in column 4 (P0 = 30)), the only effect of which is to register the The value RCN is reduced by one unit (in this case from 4 to 3). RCN becomes 0 in the 10th column. The effect is to reset the up / down counter CNT, and Pi assumes a new value transmitted by P0. Then repeat the procedure. It should be emphasized that the detection device is not limited to the examples disclosed in this patent application. The detection method is also applicable to, for example, a Blu-ray disc (formerly known as DVR), which uses MSK (Minimum Shift Key). MSK is well known in the general 85643 -16- 200405272 literature. In summary, in MSK, a b㈣nC continues with 3 pendulums, 〃, and v has a member rate of 1 · 5 times that of the single-cycle swing frequency of the cosine wave. , And a wobble period whose frequency is 1.5 times that of the single chirp. Other forms of modulation can also be used. [Brief description of the drawings] The present invention will be described in more detail with reference to the drawings, in which: FIG. 1 is a circuit diagram of a known detection device;

Fig. 2 is a signal diagram KV for explaining a known detection device; Figs. 3 (a to d) show a record carrier (disc); Fig. 4 shows a bi-phase wobble modulation; A circuit diagram of an embodiment of the detection device; FIG. 6 is a diagram for further explaining the invention; FIG. 7 is a circuit diagram of another embodiment of the detection device according to the invention; and FIG. 8 is a circuit diagram for further explaining the invention The other-the diagram of the embodiment.

In the drawings, components or elements having similar functions or uses have the same reference signs. [Illustration of representative symbols of the figure] 2 3 4 6 Dish-shaped record carrier address data circle pre-etched groove transparent substrate recording layer 85843 -17- 200405272 7 protective layer 9 track ADC analog digital converter ADIP pre-etched groove address BS bit synchronization CHDL series CBMNS Combined device CMP comparator CNT counter FPRMNS Further processing device FPRV Next predetermined reference value fs Next signal INT Integration device int Integration signal ONE One P0 (Figure 5, 7) Correct position P〇 (Figure 8) Position Pi (Figure 8) Position PRMNS Processing device PRV Preset reference value RCN Registered value s Signal SH Sample and hold circuit STRS Start / reset signal 85743 -18- 200405272

Sync TB start time Te end time Ti time interval wbl wobble signal wblrf wobble reference signal Ws character synchronization ZERO zero 19- 85643

Claims (1)

2004-0452 The scope of patent application: 1. A detection device for detecting information in a signal (S), which includes an integration device (INT) for integrating the signal (S) over time, Causing the integrating device (INT) to be reset periodically at a periodic time interval (the start time base (TB) of TO); and an end time for about one of the periodic time intervals (Ti) The reference (TE) sampling and holding circuit (SH) that periodically samples and holds the integral signal (int) and sends a further signal (fs) therefrom; the detection device is characterized in that it includes a signal delay A series of components (CHDL), one input of the series (CHDL) coupled to receive the further signal (fs); and a combination device (CBMNS) with a combined input coupled to a signal tap of the series (Chdl) The number of the combined input terminals and the combined position of the combined input terminals and the series (CHdl) signals as connectors correspond to the information in the signal (s). Detection device, characterized in that the information includes a subsequent A synchronization character portion or a bit synchronization portion of one of the possible types followed by a plurality of data bit portions, and the combining device (CBMNS) transmits a bit synchronization portion corresponding to a bit synchronization portion followed by a character synchronization portion Combine the output signal and send the combined output signal to each type of bit that can be infringed by a data bit part. 3. If the detection device of the scope of patent application for item 2 is characterized, the detection The test device includes a processing device (PRMNS) for processing all such combined output signals, and the processing is completed such that within a predetermined number of time intervals (Ti), all such combined outputs The signal value of the signal < The lowest (highest) signal value is detected together with a position number corresponding to the corresponding time interval 85743 200405272, and is detected with the time interval (τ〇 lowest (highest) within a predetermined number) The position number corresponding to the signal value is considered to be the correct position (P0) of the bit synchronization part followed by a character synchronization part. 4. The detection device such as the third item in the scope of patent application It is characterized in that the detection device includes a further processing device (FPRMNS) for further processing the bit-synchronized portion processing device (PRMNS) transmitted by the character synchronization portion followed by the bit-synchronization portion processing device (PGRM) , The further processing device (FPRMNS) detects the considered correct position (PG) of the bit synchronization portion of the subsequent word synchronization portion within a substantially longer time than the predetermined number of time intervals (Ti) Position, the further processing device (FPRMNS) includes an up / down counter (CNT) with a registered value (RCN), and whenever a bit synchronization part followed by a character synchronization part is considered to be the correct position (PG ) Appears at the expected position of the further processing device (FPRMNS), then increases (decreases) the registration value (RCN) to a predetermined registration value (PRV) of the up / down counter (CNT) by a unit value, Whenever a bit-synchronized portion of a character-synchronized portion followed by a character-synchronized portion is not considered to be at the expected position of the further processing device (FPRMNS), the registration value is changed by a unit value ( RCN) Small (increased), the further processing device (FPRMNS) that transmits the position (P!) Of the bit synchronization part (with improved position reliability) of the character synchronization part followed by the operation mode of the further processing device FPRMNS (FPRMNS ), As long as the registration value (RCN) is greater than (less than) a further predetermined reference value (FPRV), the position of the bit synchronization part of the last 200405272 followed by a character synchronization part transmitted by the further processing device (FPRMNS) (Pi) is equal to the expected position of the further processing device (FPRMNS), and when the registration value (RCN) becomes equal to the further predetermined reference value (FPRV), the data transmitted by the further processing device (FPRMNS) The position (Pi) of the bit synchronization part followed by a character synchronization part is equal to the position (PG) transmitted by the processing device (PRMNS). In the latter case, the up / down counter (CNT) will be reset. . 5 · —A device for reading the data of the disc (1) from at least one disc (1) that can obtain the address data (2), which comprises a device for reading the disc (丨) A device that generates a signal (s) in the process. The signal (s) is one of the address data (2) and includes a detection device as defined in one of the aforementioned patent applications. 6. —An optical disc drive for reading data from at least one optical disc (1), the address data (2) can be obtained from one of the pre-engraved grooves (4) of the optical disc (1), the optical disc drive includes A device that generates a signal ⑷ when reading the optical disc (1), the signal ⑷ is one of the address data (2), and the device contains items such as patent application scope 1, 2, 3, or 4 The defined detection device. 7 · —A magneto-optical disc drive for reading data from at least one magneto-optical disc (1), the address data can be obtained from the magneto-optical disc—a pre-engraved groove (4), the magneto-optical disc drive includes A device that generates a signal when reading the magneto-optical disc, the signal (s) is one of the address data (2), and the device contains a patent application such as $ 1, 2, 3, or 4 The detection device defined by the project. 8. —A method for detecting the address data (2) in a signal (s), which includes the following 85743 200405272 steps:-Periodically integrate the signal over time within a time interval (Ti),-at approximately every Sample and hold the integral signal (S) at the end time (τE) of the time interval (Ti), and thereby transmit a further signal (fs),-delay the further signal (fs), and thereby provide a plurality of signals with various delays Delayed signals,-at least part of the delayed signals are combined in a manner related to the address data (2) in the signal. 9 · A method for detecting address data (2) in a signal (s), the address data (2) includes one followed by a character synchronization part or one of several possible types of data bit parts Bit synchronization part, the method includes the following steps:-Integrate the signal (s) periodically over time within a time interval (TJ,-sample and hold the signal at the end time (Te) of approximately every time interval (Ti) Integrate the signal (s), and thereby send a further signal,-delay the further signal, and thereby provide a plurality of delayed signals with various delays, at least part of the delayed signals related to the signal ⑷ The combination of the address data (2) and the transmission of a bit synchronization part that is followed by a character synchronization part-the combined output signal, and thus the data points for each subsequent data bit Possible types of bit-synchronous parts transmit the combined output signal. 10. If the method of applying for enrollment in item 9 is' characterized in that the method further comprises the following steps: processing all such combined output signals, so that 85463 2004052 72 == the minimum (highest) signal value of all the " port output signals in each time interval㈤ within the time interval ㈤, together with the corresponding position number corresponding to the relevant time interval (Ti) The position number that is detected and corresponds to the lowest (highest) detection signal value within a predetermined number of time intervals (Ti) is considered to be the correct position of the bit synchronization part (P 〇). 11 · A detection device for detecting information in a signal (fs), which includes a series of signal delay elements (CHDL), and an input end of the series (CHDL) is coupled to receive the signal (fs ); And includes a combination device (CBMNS) with a combination input terminal coupled to a signal tap of the series (CHDL), the number of the combination input terminals and the signals of the combination input terminal and the series (CHDL) The coupling position of the tap corresponds to the information in the signal (fs).