200405210 玖、發明說明 [發明所屬之技術領域] 本發明係有關電子設計自動化之領域，、么 比先前技術較少的記憶體及處理能力 有關使用 選擇的互連線的寄生電阻及電容之方法。貝版电路中所 [先前技術] 一般破稱為電子設計自動化（Electr〇nic Automation;簡稱EDA)的領域已經進 一啡 且複雜的半導體積體電路設計工作。£ 、立处理可求的 設計及模擬一般稱為“B g 思指使用電腦來 月匕。非常適合利用電腦來執行與設 路之陡 ;古θ m达η* a 斤相關聯的工作， 乂疋口為可將電腦程式化以將大 解為多個較簡單的功能單元。 複相毛路精簡或分 在已設計出半導體晶片的電路且在 佈局好之後，即可測試積體電路的作業，、^ ^该電路 是否正確地工作。苴中一項 ” 驗證該晶片 俨之命；逆要μ ,. 抑日日片中與例如電晶 寄生效應特性m中1、=，'用狀連線）相關聯的 n f項測試可找出佈線寄生電阻 及電容之特性’而此種方式在本文中被稱為“：ί: / ReS1StanCeCapaC--(RC)e^^^^^^ 庫是才…h Ά所引起。找出佈線寄生效 4疋相§重要的，這是因為佈砷令 布'，泉可生效應會影響到晶片中 Γ 點傳輸到另—點的延遲，因而可能^塑 到處理速度。信號路徑中存在 θ J兒阻及（或）電容可能使 92394 6 200405210 晶片中的信號杯雨&i 耗用車乂長的時間才能自—點傳輸到另一點。 此，，可生效應可能影響到一般被稱為“電子遷移，， (eleCt1〇migratl〇n”）的一種現象。電子遷移意指使信號 、泉中之孟屬著使用時間而沿著電流的路徑遷移之問題。 最後，諸如數年等的一段時間之後，t亥電子遷移現象可能 把成斷路’使信號路徑中之信號中斷，因而造成晶片故障。 可月❿成私子遷移現象的高電流密度可能由—較大的電容 負載所引起。 找出互連線的寄生t JJ且及電容的特性之—方法可假 定互料中的每—金屬層之單位長度的寄生電阻及電容是 一固定值。然而，在互造綠 運、、泉早位長度中的實際寄生效應並 不是固定的’而是隨著金屬線寬度、彳質厚度、及其他穿 造及設計特性而變。因&，該方法可能會產生不精確㈣ 果，尤其對於包含多個複雜的互連線層的互連線更可能會 產生不精確的結果。 -些EDA供應商已開發出用來執行rc提取的更精確 之t法。例如，# AVANT! C〇RP〇RAT職所供應的-般 被稱為STAR-R軟體之一種軟，工呈士丨田 #人紐工具利用一個4步驟的程 提取，以便計算電子信號的延遲。在第-步驟 ，對設計中的每一互連線執行_只有電容（c_〇 提在第二步驟中，對該設計中的每-互連線執行_口 有電阻（R’ly)的提取。在第三步驟中，執行延料I 以便將只有電阻的延遲與只有電容的延遲比較。該延；； 异耗用了相當長的CPU時間。以將每—互連線逐—比較之 92394 200405210 方=，如果只有電阻的延遲與只有電容的延遲間之差里超 過某一誤差準則，則識別該互連 差，、起 逆、尿，以便進行詳細 RC提取。在第四步驟中 r,. t., t,. 使用—分佈式阻抗模型 mpeda则del)來解決窄金屬間隔及盆他 /木次彳放米效應的複雜性，而對 ’、 ^ 所識別的互連線執行詳細裎 取。耗料EDA供應商可能已 1& -提取的軟體工具，但是這些軟體工2確地執行 線執行計算繁複的Rc提取，因 P丨母―互連 理能力。 而要大置的記憶體及處 因此，需要開發出一種可精確地模# 之軟體工具，此種軟體工具係對一積雕啼二月且电路的性旎 互連線執行RC提取，而益須’、：：中之所選擇的 的Rc提取，因而使用比；： 連線執行計算繁複 力。 使用…技術較少的記憶體及處理能 [發明内容] 在一些實施例中，至少可部分地解、、办么 =，這些實施例識別積體電路中的-選: 目關互連線”），並修整其中包含積體 、桌 晶體之電路清單（netHst)，其方 -表列的電 擇相關互連喰的呢& 〜電路清單中只選 體、…; 各通道連接區域中之那此電曰 U及相關互連線的接收端的那些電日日㈤ Μ日日 到該等相關互連線的各佈局層之 可提取連接 可使這些提取的中+ + 电阻及電容值。然後 清單中：那此佈：Γ阻及電容值與連接到該修整的電路 布局層之電晶體相關聯。藉由使用相關互連 92394 2驅動_各通道連接區域巾之—修㈣電路清單之電 =、及該等相關互連線的接收端之電晶冑，即可進 异季父不繁複的R Γ接 憶口而可使用比先前技術較少的記 4恭一处理月b力。此外，藉由使每-被提取的佈局層之寄 生电容及電阻值與該修整 ^ B ° 聯，即可董“…々月早中之每一電晶體相關 子牙貝m %路的性能進行精確的模擬。 以便r:《明的—貫施例中，一種提取寄生電阻及電容值 :极：積體電路的性能之方法可包含下列步驟：識別 弓區動=連線（相關互連線”）。’然後可識別相關互連線的 轉、 通迢連接區域中之一個或多個電晶 = 目關互連線的接收端的一個或多個電晶體。亦即， =連接到相關互連線的驅動端的一個或多個 ，之-個或多個電晶體、以及連接到相關互連線的： 收立而的個或多個電晶體。 互連该積體電路的整體佈局中提取連接到該相關 ==層。亦即，可提取在電氣上連接到該等相 關互連、、泉之任何g且成A八 —^， 寄生電容及電阻值。；二各個所提取的佈局層之 的寄生電容及電阻“所二叫取的佈局層之該等提取 收端的該等所識別的-個或多個電晶體相關聯，接 則文已相當廣泛地概述了本發明的-個或多個實施例 ,υ.Γ 較易了解下文中對本發明的詳 、田。兄 g說明構成本發胡申請專利範圍的主題之 本發明額外的特徵及優點。 、 92394 9 200405210 [實施方式] 以思下文中將說明提取寄生電阻及電容值以 二二遲及—電子遷移分析，但是可將下文中概述的本 x 應用於諸如電源線網電壓降分析、時脈網路分 析、耦合分析等的其他類型的分析。又請注意，對此項技 術具有2般知識者可將本發明的原理應用於這些類型的分 析又明注意，執行此類分析的實施例將仍係在本 範圍内°又請以，為了易於㈣，可將寄生電^寄生 電阻分別簡單地稱為“電容“或“電阻，，。 統的硬體細色 ^弟1圖示出諸如工作站等的電腦系統（100)之典型硬 月丑組悲’代表了用來實施本發明的一硬體環境。電腦系統 〇〇〇)可有一處理器（110)，且係由系統匯流排（u2) 將省處理( 1 1 〇 ) I馬合到各種其他的組件。一作業系統 (1 40 )可在處理恭（i丨〇 )上執行，且控制及協調第1圖 所示的各種組件之功能。根據本發明原理的一應用程式 (1 5 0 )可配5作業系統（1 4 〇 )而執行，並提供向作業系 統（1 4〇 )的呼叫，其中該等呼叫執行要由應用程式（1 5〇 ) 執行的各種功能或服務。應用程式（15〇)可包括諸如一種 以蒼照第2圖所述提取寄生電阻及電容值以便分析延遲之 程式、以及一種以參照第3圖所述提取寄生電阻及電容值 以便分析電子遷移之程式。唯讀記憶體（Reacl 〇nJy Me.m〇1.y ;簡稱R〇M ) ( n6 )可被耦合到系統匯流排 (1 1 2 ) ’且包含一用來控制電腦系統（】〇〇 )的某些基本功 92394 200405210 月匕的基本輪i]入/輪出糸統（Basic Input/Output System ;簡 稱BIOS )亦可將隨機存取記憶體（Random Access Memory ;簡稱ram) ( 114)及磁碟配接器（118)耦合到 系統匯流排（112 )。請注意，可將軟體元件包括作業系統200405210 发明 Description of the invention [Technical field to which the invention belongs] The present invention relates to the field of electronic design automation, and has less memory and processing capacity than the prior art. A method for using parasitic resistance and capacitance of selected interconnection lines. The previous version of the circuit is generally called the Electronic Design Automation (EDA) field, which has been involved in the design of complex semiconductor integrated circuits. The design and simulation that can be obtained immediately is generally referred to as "B g refers to the use of a computer to the moon. It is very suitable to use a computer to perform the tasks associated with setting up the road; the ancient θ m up to η * a catty, 乂The pass is a computer that can be programmed to solve the problem into a number of simpler functional units. The complex phase circuit can be simplified or divided into circuits that have been designed with semiconductor chips and can be tested after the layout of the integrated circuit. ， ^ ^ Whether the circuit works correctly. One of the items "verifies the fate of the chip; the opposite is μ,. In the Japanese film, for example, the parasitic effect characteristic m of the transistor 1, =, 'connected with Line) associated nf term test can find out the characteristics of wiring parasitic resistance and capacitance ', and this method is called ": ί: / ReS1StanCeCapaC-(RC) e ^^^^^^ … H 引起. It is important to find out the wiring parasitic effect 4 疋. This is because the arsenic makes the cloth. The spring effect can affect the delay of Γ point transmission to another point in the chip, so it may To processing speed. The presence of θ J resistance and / or capacitance in the signal path may cause 92394 6 200405210. It takes a long time for the signal cup rain & i in the chip to transmit from one point to another. Therefore, the viable effect may affect what is generally called "electron migration," (eleCt10migraton) ). A phenomenon of electron migration refers to the problem of causing signals and springs in the spring to migrate along the path of current with the use of time. Finally, after a period of time such as years, the electron migration phenomenon may be broken. The signal in the signal path is interrupted, resulting in chip failure. The high current density that can cause the phenomenon of private migration may be caused by a large capacitive load. Find the parasitic t JJ of the interconnection and the characteristics of the capacitor The-method can assume that the parasitic resistance and capacitance per unit length of each metal layer in the mutual material is a fixed value. However, the actual parasitic effect in the mutual green transport, the early spring length is not fixed. Is a function of metal line width, texture thickness, and other piercing and design characteristics. Because of &, this method may produce inaccurate results, especially for layers that contain multiple complex interconnects Interconnects are more likely to produce inaccurate results.-Some EDA vendors have developed more accurate t methods to perform rc extraction. For example, # AVANT! As a kind of software of STAR-R software, Gongcheng Shi Tian # person button tool uses a 4-step process extraction in order to calculate the delay of the electronic signal. In the first step, each interconnect in the design is performed only Capacitance (c_〇) In the second step, the extraction of R_ly is performed on each interconnect line in the design. In the third step, the extension I is performed so that The delay is compared with the capacitor-only delay. The delay; the difference consumes a considerable amount of CPU time. In order to compare each interconnect line by line, 92394 200405210 square =, if the difference between the delay of only the resistor and the delay of only the capacitor exceeds a certain error criterion, then identify the interconnection difference, inverse, urine, so that Perform detailed RC extraction. In the fourth step, r ,. t., T ,. use the distributed impedance model (mpeda and del) to solve the complexity of the narrow metal interval and the pot / tall rice effect. Detailed interconnections are performed. Consumable EDA suppliers may have already extracted software tools, but these software workers did perform the computationally complex Rc extraction on line, due to the parent-interconnecting capability. To store large amounts of memory and therefore, it is necessary to develop a software tool that can accurately mold #. This software tool performs RC extraction on a product and interconnects the circuit's electrical properties. The selected Rc must be extracted by '::', so the ratio is used:: The computational complexity of performing the calculations on-line. Use of less technical memory and processing power [Summary of the Invention] In some embodiments, at least part of the solution can be solved. Do these =? These embodiments identify the -selection: the target interconnection line in the integrated circuit " ), And trim the circuit list (netHst) that contains integrated products and table crystals, and its square-listed electrical selection related interconnects & & ~ Only circuit selection in the circuit list, ...; The electrical connections at the receiving end of the U and related interconnects are connected to the layout layers of the related interconnects so that the extracted resistance and capacitance values can be obtained. In the list: then this cloth: Γ resistance and capacitance values are associated with transistors connected to the trimmed circuit layout layer. By using the relevant interconnect 92394 2 driver _ of each channel connection area-repair the circuit list =, And the electrical crystal at the receiving end of these related interconnects can enter the R Γ interface that is not complicated in different seasons, and can use less memory than the previous technology to handle the month b force. In addition, By making the parasitic capacitance and resistance value of each-extracted layout layer ^ B ° with the trimming can Dong "... 々 month earlier in the performance of each transistor associated passage Ziya Pui m% accurate simulation. In order to r: "In the Ming-Yuan embodiment, a method for extracting the parasitic resistance and capacitance value: pole: the performance of the integrated circuit may include the following steps: identify bow zone movement = connection (relevant interconnect line). One or more transistors in the turn-on, through-connection area of the related interconnect line can then be identified = one or more transistors at the receiving end of the interconnected line. That is, = a driver connected to the related interconnect line One or more terminals, one or more transistors, and one or more transistors connected to the related interconnection line: the isolated one or more transistors. The overall layout of the interconnection of the integrated circuit is extracted to connect to the related == layer. That is, you can extract any g that is electrically connected to these related interconnects, springs, and A to ^, the parasitic capacitance and resistance value. The parasitic capacitance of each of the extracted layout layers. And the resistance-required layout layer of the extraction end of the identified one or more transistors are associated, then the article has quite broadly outlined one or more embodiments of the present invention, υ.Γ makes it easier to understand the details of the present invention. Brother g describes additional features and advantages of the invention that form the subject of the claimed subject matter. 92394 9 200405210 [Embodiment] In the following, we will explain the extraction of parasitic resistance and capacitance values to delay the two-two-electron migration analysis, but this x, which is outlined below, can be applied to the analysis of power line network voltage drop, time Pulse network analysis, coupling analysis, and other types of analysis. Please also note that those who have general knowledge of this technology can apply the principles of the present invention to these types of analysis. It is also clear that the implementation of such analysis will still fall within this scope. Please also, for ease of use Alas, the parasitic electrical and parasitic resistances can be simply referred to as "capacitance" or "resistance," respectively. The hardware color of the system is as follows: Figure 1 shows a typical hard moon group of a computer system (100) such as a workstation. "Break" represents a hardware environment for implementing the present invention. A computer system (OO) can have a processor (110), and the system bus (u2) will save provincial processing (1 1 0) to Various other components. An operating system (1 40) can be executed on the processing unit (i 丨 〇), and controls and coordinates the functions of various components shown in Figure 1. An application program (1 5) according to the principles of the present invention 0) can be executed with 5 operating systems (14.0), and provides calls to the operating system (14.0), where these calls perform various functions or services to be performed by the application (150). Applications The formula (15) may include, for example, a A program for analyzing parasitic resistance and capacitance for delay analysis, and a program for extracting parasitic resistance and capacitance for analyzing electron migration as described with reference to FIG. 3. Read-only memory (Reacl 〇nJy Me.m〇1.y; for short Rom) (n6) can be coupled to the system bus (1 1 2) 'and contains some basic skills to control the computer system (] 〇〇) 92394 200405210 basic round i) in / out The system (Basic Input / Output System; BIOS for short) can also couple Random Access Memory (RAM) (114) and disk adapter (118) to the system bus (112). Please Note that software components can include operating systems
(140)及應用程式（15〇)載入ram ( 114 )中，而RAM (11 4 )可以是電腦系統（i 〇〇 )的用來執行之主記憶體。 磁碟配接器（118)可以是與諸如磁碟機等的一（12〇)互 通訊息的的一小型電腦系統介面（Small c〇mputer system(140) and the application program (15) are loaded into the ram (114), and the RAM (11 4) can be the main memory of the computer system (100) for execution. The disk adapter (118) may be a small computer system interface (Small c0mputer system) that communicates with one (12) such as a disk drive.
Intel face，簡稱SCSI )配接器。請注意，以參照第2圖所 述提取寄生電阻及電容值以便分析延遲的本發明之程式可 存放在磁碟單元（1 2 0 )或應用程式（1 5 0 )中。又請注意， 以荼照第3圖所述提取寄生電阻及電容值以便分析電子遷 移的本發明之程式可存放在磁碟單元（丨2〇 )或應用程式 (150 )中。 請參閱第1圖，電腦系統（1〇〇)可進一步包含一耦合 到系統匯流排（112)之通訊配接器（134)。通訊配接器（134) 可將系統匯流排（11 2 )連接到諸如區域網路（Local Area Network ;簡稱 LAN)或廣域網路（wide Area Netw〇rk ; 簡％ WAN )等的一外部網路，使電腦系統（丨〇〇 )能夠與 其他的此種系統通訊。亦可將各輸入/輸出（1/〇 )裝置經 由一使用者介面配接器（122)及一顯示配接器（136)而 連接到系統匯流排（11 2 )。可將鍵盤〇 24 )、滑鼠（} 26 )、 及喇队（1 j 0 )經由使用者介面配接器（丨22 )而都連接到 系統匯流排（Π2)。可經由任一這類的裝置而將事件資料 200405210 輸入到電《統㈤）。“配接hw)可將 視器（138)連接到系統匯流排⑴2)。在此種方式 使用者可經由鍵盤（124)或滑鼠（126)而輸入到電腦系 統（1⑽），並可經由顯示器（138)而自電腦 接收輸出。 本發明的實施例包括形式為其程式被設計成執行本發 明料的：種或多種方法之電腦系統以及形式為一電絲 式產品的實施例。根據電腦系統實施例，肖來執行該等： ，或多種方法之指令集係存在於大致以前文所示之方式設 定的一個或多個電腦系統之隨機存取記憶體（U;了 =¾糸統（_)需要用到之前，可將指令集以電腦程式 品形式儲存於另一電腦記憶體中，例如，磁碟單元12〇， ^ V ϋ匕括。者如最後將用於磁碟單元（1 20 )的光碟或軟碟 寺0抽換式记憶單元）。此外，亦可將該電腦程式產品儲存 包腦中，且於需要時由一網路或諸如網際網路等的 I外部網路將該電腦程式產品傳送到使用者的工作站。熟 習此：技術者當可了解，該等指令集的實體儲存會在物理 j改變了用來儲存該等指令集的媒體，因而該媒體載有電 月白可讀取的資訊。該改變可以是電氣、磁性、化學、或某 一其他的物理改變。 第 2 ' ~~^阻及電i值之方法 第2圖是本發明一種提取寄生電阻及電容值來模擬— 積電路的性能以便分析延遲的方法（200 )實施例之一流 Λ° 凡剑技術”一節中所述，雖然一些電子設計自 92394 2UU4Uy2l〇 ::(EDA)供應商可能已開發出可比先、 地執行電阻電容（虹）提取 先河的方法更精確 具需要對積體電路中的每_ 、具」：是這些軟體工 取，因而需要A旦 仃5十异繁複的HC提 而要大里的記憶體及處理 敌 出—種可精確地模P 因此，需要開發 隹地杈铋積體電路的性能之 -工具係對—積體電路中之 …，此種軟 取，而無須對每一互連 互連線執行RC提 使用比先前技二 計繁複的Rc提取，因而 綠 少的記憶體及處理能力。方法（20… -種可精確地模擬一積體電路的性能之方法：2。0)-須對該積體電路中 ^ 法，且忒方法無 取，因：：： 互連線執行計算繁…C提 意，"圖示出諸如延遲分處理能力。請注 行下文所、十、Μ 遲刀析寺的一種類型的分析，於執 丁下文所边的Rc提取時， 析。請注意，於執行下文所、;"對#貝肢毛路執行該延遲分 攸袖 執仃下文所述的RC提取時，可對積體電 的，; 丁諸如電源線網電壓降分析或躺合分析等的其他類型 j斤’且對此項技術具有—般知識者當可了解這些類型 二析。又凊庄意’執行此類分析的實施例也是在本發明 的範圍内。 請配合第1圖而參閱第2圖，在步驟（2〇1)中，可提 取一積體電路中的每一互連線（亦即連線網）之寄生電容。 亦 P 可使用 4如 Candace Design Systems，Inc. (CandaceIntel face (SCSI for short) adapter. Please note that the program of the present invention for extracting the parasitic resistance and capacitance value for analyzing the delay as described with reference to FIG. 2 can be stored in the disk unit (120) or the application program (150). Please also note that the program of the present invention for extracting the parasitic resistance and capacitance value as described in FIG. 3 for analyzing the electronic migration can be stored in the magnetic disk unit (20) or the application program (150). Referring to FIG. 1, the computer system (100) may further include a communication adapter (134) coupled to the system bus (112). The communication adapter (134) can connect the system bus (11 2) to an external network such as a local area network (LAN) or a wide area network (WAN). So that the computer system (丨 〇〇) can communicate with other such systems. Each input / output (1/0) device can also be connected to the system bus (11 2) via a user interface adapter (122) and a display adapter (136). The keyboard 〇 24), the mouse (} 26), and the team (1 j 0) can all be connected to the system bus (Π2) through the user interface adapter (丨 22). Event data 200405210 can be entered into the system via any of these devices. "Matching hw) can connect the viewer (138) to the system bus (2). In this way, the user can input to the computer system (1⑽) via the keyboard (124) or mouse (126), and via The display (138) receives output from the computer. Embodiments of the present invention include embodiments of a computer system in the form of a program designed to execute the material of the present invention: one or more methods and an embodiment in the form of a wire-type product. According to the computer In the system embodiment, Xiao Lai executes the following: The instruction set of one or more methods exists in the random access memory of one or more computer systems set in a manner roughly shown in the foregoing (U; 了 = ¾ 糸 system ( _) Before use, the instruction set can be stored in another computer memory in the form of a computer program. For example, the disk unit 12 〇, ^ V ϋ 括. If it will be used in the disk unit (1 20) CD-ROM or floppy disk 0 removable memory unit). In addition, the computer program product can also be stored in the brain, and when needed, it can be connected to a network or an external network such as the Internet. Send the computer program product to the user Familiar with this: technicians can understand that the physical storage of these instruction sets will change the medium used to store these instruction sets at physical j, so the medium contains information that can be read by Dianbai. The The change can be electrical, magnetic, chemical, or some other physical change. Figure 2 '~~ ^ Method of resistance and electrical i value Figure 2 shows the performance of an integrated circuit by extracting parasitic resistance and capacitance values according to the present invention In order to analyze the delay method (200), one embodiment of the method is described in the section ”° Fanfan Technology”, although some electronics designs have been developed from 92394 2UU4Uy2l0: :( EDA). (Rainbow) The more accurate method of extracting advanced methods requires the use of integrated circuits in the integrated circuit. These are the software tools, and therefore require the use of 5 different and complex HCs to extract the memory and process the enemy. —A kind of precise mode P Therefore, it is necessary to develop the performance of the bismuth integrated circuit-tool system pair --- in the integrated circuit, this kind of soft take, without the need to perform RC for each interconnect Mention using than the second technique Calculating complicated Rc extraction, so less memory and processing power. Method (20 ...-A method that can accurately simulate the performance of an integrated circuit: 2.0)-The method must be used in the integrated circuit, and the method is unavailable, because :: The interconnection line is complicated to perform calculations. ... C is a note, " diagrams such as delay split processing capabilities. Please note one type of analysis described below, X, and M. The analysis is performed when Rc is extracted as described below. Please note that when performing the delay analysis performed on # 贝 腿毛 路 and performing the RC extraction described below, it is possible to analyze the integrated power, such as the power line network voltage drop analysis or Other types of analysis, such as lying analysis, and those who have this technology-general knowledge should understand these types of analysis. Embodiments that perform such analysis are also within the scope of the present invention. Please refer to FIG. 2 in conjunction with FIG. 1. In step (201), the parasitic capacitance of each interconnect line (ie, the connection network) in an integrated circuit can be extracted. You can also use 4 such as Candace Design Systems, Inc. (Candace
DeSlgn SyStemS，Inc·的地址為 2655 Seely Avenue，San J〇se’ CA 9 5〗〇4 )製造的“Vampire，，等的軟體工具來量測每 互k、，泉的可生電谷。互連線（inte】.c〇nnecti〇n )意指一 13 92394 200405210 積體電路中的諸如各電晶體等的各電子裝置間之接線或連 線網。 在步驟（202 )中，可計算該積體電路中的每一互連線 的最大电阻之估計值。在一實施例中，可使用下列的方程 式來計算一互連線的最大電阻之估計值··DeSlgn SyStemS, Inc.'s address is 2655 Seely Avenue, San José CA 9 5 〇 04) software tools such as "Vampire," to measure the power generation valleys of each k. Connection (inte) .c0nnecti0n) means a wiring or a connection network between electronic devices such as transistors in a 13 92394 200405210 integrated circuit. In step (202), this can be calculated The estimated value of the maximum resistance of each interconnect line in the integrated circuit. In one embodiment, the following equation can be used to calculate the estimated value of the maximum resistance of an interconnect line ...
Rest - (mtCap*metalRes)/(min]y[etaiCap*miii Wire Width) (EQ1) 其中Rest疋互連線的估計之最大電阻，·其中是步 & ( 01 )中得到的所提取之互連線寄生電容；其中 i^talRes是互連線的一估計電阻係數；其中minMetaiCap 是互連f的估計最小電容；且其中minWireWidth是互連線 的估。十最小覓度。可從自製程接收的電阻係數、電容、及 互連線寬度值得到該等估計之電阻係數、最小電容、及互 連線最小寬度。 在步驟（ 203 )中，可使用下列的方程式來計算積體電 路中的每一互連線之一估計延遲：Rest-(mtCap * metalRes) / (min] y [etaiCap * miii Wire Width) (EQ1) where the estimated maximum resistance of the Rest 疋 interconnection line, where is the extracted mutual value obtained in step & (01) Parasitic capacitance of the connection; where i ^ talRes is an estimated resistance coefficient of the interconnection; where minMetaiCap is the estimated minimum capacitance of the interconnection f; and where minWireWidth is an estimate of the interconnection. Ten minimum search degrees. These estimated resistivity, minimum capacitance, and minimum interconnect width can be obtained from the resistivity, capacitance, and interconnect width values received during the self-made process. In step (203), the following equation can be used to calculate an estimated delay for each of the interconnect lines in the integrated circuit:
Delayest=.5*Rest*intCaP + Rest*Cgate (EQ 9) 其中Delayed電子信號自互連線中的某—點至另一點的 :計延遲；且其中Cgate是連接到互連線的每一電晶體的 :-：極之估：總電容。可自製程中取得連接到互連線的 母一電晶體的每一閘極之估計總電容。 ”在本發明的另-實施例中，可以如下文所述之方 异-互連線的一估計電容及一估計電m，而決定一 號自該互連線中的某—點至另—點的估計延遲。②D 可利用下列方程式來估計一互連線的電^ · 200405210Delayest = .5 * Rest * intCaP + Rest * Cgate (EQ 9) where the Delayed electronic signal is from one point to the other in the interconnection line: count the delay; and where Cgate is every electrical connection connected to the interconnection line Crystal:-: Extreme estimate: total capacitance. The estimated total capacitance of each gate of the mother-transistor connected to the interconnect can be obtained during the manufacturing process. "In another embodiment of the present invention, an estimated capacitance and an estimated electric m of the different-interconnection line may be determined as described below, and the number one is determined from a point in the interconnection line to another- The estimated delay of a point. ② D The following equation can be used to estimate the electricity of an interconnect line.
Capest = (maxDist*maxMetalCap) (EQ3) 一中Capest疋e亥互連線的估計電容·，其中maxDist是該互 連線的最大距離估計值；且其中maxMetalCap是該互連線 的估計最大電容。卩自佈局取得估計最大距離，且可自製 程取得該互連線的最大電容。 可利用下列方程式來估計一互連線的電阻··Capest = (maxDist * maxMetalCap) (EQ3) The estimated capacitance of the Capest 疋 e interconnect in ·, where maxDist is the estimated maximum distance of the interconnect; and where maxMetalCap is the estimated maximum capacitance of the interconnect.卩 The estimated maximum distance is obtained from the layout, and the maximum capacitance of the interconnection line can be obtained by the self-made process. The following equation can be used to estimate the resistance of an interconnect line ...
Rest ^maxDlst*metalRes)/minWireWidth (EQ4) /、中Rest是該互連線的估計電阻；其中⑽是該互 連線的-估計電阻係數；且其+ minwire width是該互連線 的—估計最小寬度。 一 Qj及EQ4的結果時，可使用下列的方程式來 ^异—電子信號自互連線中之某-點至另-點之估計延 (EQ5) 一點至另 的每一電 一實施例 線中之某 值，則可 ^elayest .5 *Rest*Capest + Rest*Cgate 其中叫叮⑽是—電子信號自互連線中之某 晶=計延遲；且其中㈣是連接到互連線 月且、母一閘極之估計總電容。 中 ^ ^ ( 2〇4 )中，可識別各相關互連線。在 —點:果步驟（2〇3)中計算出的電子信號自互連 識別出：門點之估計延遲超過-預先選擇的臨界 〜出相關互連線。 驅動端的 、以及該 即5可識 —個：Γ'(2°5)中，可識別該等相關互連線的 晶體。亦 等，3夕個通迢連接區域中之-個或多個電晶俨 寺"關互連線的接收端的一個或多個，… 200405210 別連接到該等相關互义車蜱 區域中之一個或多4二=:一個或多個通道連接 的接收端的一個或多個電曰- f到“相關互連線 子信號自-驅動哭 n 。一互連線的驅動端意指電 .^ 立運、、泉而。一互連線的拯跄浐立 私電子信號退出而將為一桩 妾收而思 、鱼抹f々 、、接收裔所接收的互連線端。通谨 連接區域忍指在相關互读 、 陣列之電晶體。連線與電源及接地線之間連接的- t 右千〃驟（2〇6)中，可藉由在其中包含積體電路中的所 有笔晶體的—電路清單中選擇在步驟⑽）中識別 斤 晶體修整該清單，以產 ^ 伤數目較少的電晶體清單。笋 由修整該電路清單，以吝 猎 乂產生一伤數目較少的電晶體清單， 而可以下文所詳述的方式勃 Λ執仃计π較不繁複的RC提取， 口而使用了比先前技術較少 一、 1杈〆的5己铖體及處理能力。此外， 錯由選擇該等相關互遠蜱 連、、泉的驅動^的一個或多個通道連接 £或中之一個或多個電 ^ 汉忑寺相關互連線的接收踹 的一個或多個電晶體，即 擬積體電路的性能。……之方式精確地模 ▲在步驟（ 207 )中，可自積體電路的整體佈局提取連接 到该等相關互連線之各係 。 布局層亦即，可提取在電氣上連 接到該等相關互連線之任何組成部分。例如，可提取連接 至丨J该寺相關互遠绩的*2丨 , -逑及）通孔。在另一個例子中，可提取該等 相關互連線的金屬接點。可使用諸如Va —“等各種市場 本供應的軟體工具來提取連接到該等相關互連線的佈局 居。在不發明的-實施例中’在提取連接到該等相關互連 92394 200405210 線的佈局層時，可得到連接到所提取的 ^ ^ rr 4® U 寻怖局層的電晶 月旦之座私。这些座標可指示該等電晶體 ^ ^ m 領版兒路的整體 佈局中之位置。如將於下文中說明的 J jib ]± 4® y-t ::被的佈局層之寄生電容及電阻值與修整：電：清 早中之各4寸定電晶體相關聯。 在步驟（2G8)中，可提取每—提取的佈局層 谷及電阻值。可利用嗜 ·尸 了生兒 邊如Vamplre寻的市場上供應的軟體 工具…（亦即量測）每一被提取的佈局 及電阻。 了王甩夺 乂 ’、4 ( 209 )中，可使每一提取的佈局層之提取的寄 '4-的-路清早中之各特定電晶體相關 写外 如一文所述，尤牛ξ取f Ο Π 7、1+» 在步恥（207 )中，可得到連接到該等接 取的佈局層的各電晶體之座標。藉由這些座標，可使每一 提取的佈局層的該等提取之寄生電容及電阻值與連接到佟 整的竭單中那些提取的佈局層之每一電晶體相關聯7 、藉由使用由該等相關互連線的驅動端的各通道連接區 域中之各a晶體及該等相關互連線的接收端的各電晶體構 成=修整的電路清單’即可以將於下文所詳述之方式執行 十^車乂不’τ、裣的Rc提取，因而使用比先前技術較少的記 ^體及處理能力。此外，藉由使每一提取的佈局層之寄生 兒谷及私阻值與修整的電路清單中之每一電晶體相關聯， 即可對積體電路的性能執行精確的模擬。 _ :在V馬个（2 1 0 )中，可執行一分析。例如，可執行與積 電子彳t號的延遲有關之分析。請注意，使用= 92394 200405210 提取的可生電容及電阻值來決定 …是此項技術中習知的，因而為；::：電子信號 办將不詳細說明上述的過程。請注音，可二書的續 的本發明之原理來執行諸如電源線網電屋降^前文所述 路分析、刼人八a 土刀析、時脈網 耦s分析、電子遷移分析等的 可使用前文斛、+、从丄々 ^ 、他刀析。例如， J文所述的本發明之原理而模擬一 能，以便測試電子遷移如將於下文中表昭第積二電路的性 說明，。 /‘、、、弟3圖進—步的 (:二可按照與所提供的不同之順序來執行方法 明。又4: 2圖的說明中所提供的該順序僅為舉例說 又…主思，可以幾乎同時之方式執行 步驟。 M 丫之系些 且及電容值以复^之方法 第3圖是本發明一種提取寄生電阻及電容值來模擬 積體電路的性能以便分析電子遷移的方法（3⑽）實施例之 流程圖。 請配合第1圖而參閱第3圖，在步驟（3〇1 )中，可計 算流經積體電路中之每一互連線的估計平均或均方根 (rms)電流。在一實施例中，可使用下列方程式來計算流 經一互連線的平均電流： lave = crossMult*maxCap*Vdd*frequency*toggle (EQ6) 其中lave是流經該互連線的估計平均電流；其中cr〇ssMuh 是交叉電流（交叉電流可意指自電源經由該互連線而直接 "il到接地點的遙成）之換异值，其中⑺以cap是該互連線 92394 38 200405210 估計“電容；其…是電源供應電屢；其中 requency疋與該互連線相關聯的時脈之頻率.且 :二,根據—信號的切換活動而由使用的一值^ 用:時脈動態閘，且·5係用於資料信號，這是因 :。、Μ相切換速率是時脈及動‘㈣的切換速率之一 在本發明的—實施例中，可利用下列的方程式 ^經一互連線的rms電流：Rest ^ maxDlst * metalRes) / minWireWidth (EQ4) /, where Rest is the estimated resistance of the interconnect; where ⑽ is the estimated resistance of the interconnect; and its + minwire width is the estimated of the interconnect- The minimum width. For the results of Qj and EQ4, the following equations can be used to calculate the difference between the one-point to the other-point of the electronic signal (EQ5) and the delay of the electronic signal from one point to another. Some value can be ^ elayest .5 * Rest * Capest + Rest * Cgate where Ding⑽is—the electronic signal from a crystal in the interconnection line = meter delay; and where ㈣ is connected to the interconnection line and, Estimated total capacitance of the female-gate. In ^ ^ (204), each related interconnection line can be identified. The electronic signal calculated in the -point: fruit step (203) is self-interconnected. It is identified that the estimated delay of the gate point exceeds the pre-selected threshold ~ the relevant interconnecting line. On the driver side, and the five identifiable ones: Γ '(2 ° 5), which can identify the crystals of these related interconnects. Wait, one or more of the receiving junctions of the electric crystal temples in one or more of the three connecting areas of the evening, 200405210, do not connect to the relevant mutual car tick area. One or more 4 ==: One or more electrical connections at the receiving end of one or more channels connected to -f to "the relevant interconnect line sub-signal self-driving cry n. The driving end of an interconnect line means electricity. ^ Li Yun, and Quan Er. An interconnected line's private electronic signal exits and will be thought of for a while. The end of the interconnected line received by the receiver. The connection area is sincere. Tolerance refers to the related inter-reading, array transistor. The connection between the connection and the power supply and the ground wire-t right thousand steps (206), which can include all pen crystals in the integrated circuit -In the circuit list, choose to identify the crystal in step ii) and trim the list to produce a list of transistors with a small number of injuries. You can trim the circuit list to produce a transistor with a small number of injuries. List, and can perform RC extraction in a less complicated manner in the manner detailed below, And it uses less than one and a half of the pentamed carcass and processing capacity than the previous technology. In addition, one or more channels connected by the selection of these related remote remote ticks, or springs, or medium The reception of one or more electric wires ^ the reception of one or more transistors of the related interconnecting lines of Hanyu Temple, that is, the performance of the quasi-integral circuit .... The mode is accurately modeled. ▲ In step (207), The overall layout of the integrated circuit extracts the lines connected to the related interconnects. The layout layer, that is, any component that is electrically connected to the related interconnects can be extracted. For example, the connections to J * 2 丨,-逑) through-holes related to this temple. In another example, the metal contacts of these related interconnects can be extracted. Software such as Va — “can be used in various markets. Tool to extract layouts connected to these related interconnects. In the uninvented embodiment, when extracting the layout layer connected to these related interconnects 92394 200405210 line, you can get the electric crystals connected to the extracted ^ rr 4® U camera layer. . These coordinates can indicate the position of the overall layout of the transistor ^ ^ m collar circuit. As will be explained below, J jib] ± 4® y-t :: The parasitic capacitance and resistance value of the layout layer are related to the trimming: electricity: each 4 inch fixed transistor in the early morning. In step (2G8), the valley value and resistance value of each-extracted layout layer can be extracted. Available software tools available on the market such as Vamplre ... (ie, measuring) each extracted layout and resistance. In the description of Wang Shao 乂 乂 4, 4 (209), the extraction of each extracted layout layer can be related to the specific transistor in the '4 -'- road early morning. The relevant writing is as described in the article. f Ο Π 7, 1+ »In step (207), the coordinates of the transistors connected to the access layout layer can be obtained. With these coordinates, the extracted parasitic capacitance and resistance values of each extracted layout layer can be associated with each transistor connected to those extracted layout layers in the finished exhaustion list. Each a crystal in each channel connection area of the driving end of the related interconnects and the transistor composition of the receiving end of the related interconnects = trimmed circuit list 'can be implemented in the manner detailed below. Since the car's Rc extraction is not τ, 裣, it uses less memory and processing power than the previous technology. In addition, by associating the parasitic valleys and private resistance values of each extracted layout layer with each transistor in the trimmed circuit list, an accurate simulation of the performance of the integrated circuit can be performed. _: An analysis can be performed among V horses (2 1 0). For example, an analysis related to the delay of the integrated electron 号 t can be performed. Please note that the use of = 92394 200405210 extractable capacitance and resistance value to determine… is known in this technology, so is: ::: The Electronic Signal Office will not explain the above process in detail. Please note that the principles of the present invention that can be continued from the second book can be used to perform the analysis of the power line network, electric house, etc. ^ Road analysis, 刼 人 a a soil knife analysis, clock network coupling analysis, electron migration analysis, etc. Analyze using Qian Wenhu, +, Cong 丄 々 ^, He Dao. For example, the principle of the present invention described in article J simulates a function in order to test the electron migration as shown in the following description of the second circuit. / '、、、 弟 3 pictures in step-by-step (: two can be performed in a different order from the provided method description. And the order provided in the description of 4: 2 pictures is just an example and ... The steps can be performed at almost the same time. The method of M and the capacitance value is restored. Figure 3 is a method of extracting parasitic resistance and capacitance value to simulate the performance of the integrated circuit in order to analyze the electron migration ( 3⑽) The flowchart of the embodiment. Please refer to FIG. 3 in conjunction with FIG. 1. In step (301), an estimated average or root mean square (RMS) of each interconnection line flowing through the integrated circuit can be calculated. rms) current. In one embodiment, the following equation can be used to calculate the average current flowing through an interconnect: lave = crossMult * maxCap * Vdd * frequency * toggle (EQ6) where lave is flowing through the interconnect Estimated average current; where crOssMuh is the transversal value of the cross current (cross current can mean the remote connection from the power source directly to the ground point via the interconnection line), where ⑺cap is the interconnection line 92394 38 200405210 Estimated "capacitance; it is ... Repeatedly; where the frequency is the frequency of the clock associated with the interconnect. And: two, a value used by the switching activity of the signal ^ used: the clock dynamic gate, and · 5 is used for data signals This is because: The M-phase switching rate is one of the switching rates of the clock and motion. In the embodiment of the present invention, the following equation can be used: rms current through an interconnection line:
Irrns^ S^e r〇^4/3)*-xCap*crossMuIt，vdd，square (iequency*toggle〇)*square root(trf) ^ 是流經該互連線的電流之均方根值；且其:二 是省如％脈信號等的信號之上升時間。 中，==(3G2)中，可識別各相關互連線。在-實施例 Γ步驟（3G1)中計算出的估計平均電流或估計 7电流超過-預先選擇的臨界值，則可識別各相關互連 線的驅動端的 晶體、以及該 。亦即，可識 多個通道連接 等相關互連線 •驅動端意指電 線的接收端意 連線端。通道 在步驟（303 ) +，可識別該等相關互連 :個或多個通道連接區域中之一個或多個電 等相關互連線的接收端的一個或多個電晶體 別連接到該等相關互連線的驅動端的一個或 區域中之一個或多個電晶體、以及連接到該 的接收端的一個或多個電晶體。一互連線的 子信號自一驅動器發出的互連線端。—互連 指電子信號退出而將為一接收器所接收的互 200405210 連接區域意指在相關互連線與電源及接地線之間連接的一 陣列之電晶體。 在步驟（ 304 )中，可藉由在其中包含積體電路中的所 有電晶體清單的一電路清單中選擇在步驟（3 〇 3 )中識別出 的電晶體修整該清單，以產生—份數目較少的電晶體清 :。:藉由修整該電路清單，“產生一份數目較少的電二 清單，而可以下文所詳述的方式執行計算較不繁複的E 提取，因而使用了比先前技術較少的記憶體及處理能力。 此外，藉由選擇料相關互連線的驅動端的—個或多個通 迢連接區域中之一個或多個電晶體、及該等相關互連線的 接收端的一個或多個電晶體，即可如 確地模擬積體電路的性能。 I之方式精 在步驟（305)中’可自積體電路的整體佈局 到該等相關互連線之各佈局亦即，可提取在電 接到該等相關互連線之任何組成部分。例如，可提 到該等相關互連線的通孔。扃 在另一個例子中，可提 上供應的軟體工具來提取被連接到該等相關互 项 層。在本發明的一實施例中，在 P ”的佈局 τ 在徒取被連接到該笙知 連線的佈局層時，可得到^ ^ 、忒互 才」k接到所提取的該等佈 晶體之座標。這些座標可指 。g的电 J ?日不该寺電晶體在積 體佈局中之位置。如將於下文中說明的，可利二： 使每一提取的佈局層之寄生兩六 攻二座標 單中之各特定電晶體相關聯。 /勺㊉路清 92394 20 200405210 步驟（3 0 6、rh 寄生 的軟 生電 … 中，可提取每一所提取的佈局層之 容及電阻值。可利 · 扪用褚如Vamplre等的市場上供應 工::來提取（亦即量測）每一所提取的佈局層之寄 ΐ二（3〇7)中，可使每一提取的佈局層之提取的寄 及㈣值與修整的電路清單中之各特定電晶體相關 :“Γ文所逑’在步驟（305)中，可得到連接到該等提 曰白、局層的各電晶體之座標。藉由這些座標，可使每一 提取的佈局層的該等提取之寄生電容及電阻值與連接到修 二的包路清皁中之那些提取的佈局層之每一電晶體相關 聯0 。、藉由使用由該等相關互連線的驅動端的各通道連接區 域中之各電晶體及該等相關互連線的接收端的各電晶體構 f =修整的電路清單，即可以將於下文所詳述之方式執行 j开幸乂不繁複的Rc提取，因而使用比先前技術較少的記 :體及處理能力。此外’藉由使每一提取的佈局層之寄生 4及电阻值與修整的電路清單中之每一電晶體相關聯， P可對積體電路的性能執行精確的模擬。 、y “（ 3 〇 8)中，可執行分析。例如，可利用方法（3 〇 〇 ) 測積體電路中之電子遷移。請注意，使用所提取的寄 、甩谷及电阻值來測試一積體電路中之電子遷移是此項技 ’、丁中白知的，因而為了顧及說明書的簡潔，將不詳細說明 上述的過程。 。月、左意，可按照與所提供的不同之順序來執行方法 92394 200405210 ( 300 )，且第3圖的說明中所提供的該順序僅為舉㈣ 明。又請注意’可以幾乎同時之方式執行第3圖中之某些 步驟。 一 雖然已參照數個實施例而說明了本系統、電腦程式產 品、及方法，但是並非將本發明限制在本說明書所述及的 特定形式；相反地，本發明將涵蓋可以被合理地包含在最 後的申請專利範圍所界定的本發明的精神及範圍内之此類 替代、修改、及等效物。請注意，只是為了組織的目的而 使用了一些標題，且該等標題之用意並非在限制說明或申 請專利範圍的範圍。 [圖式簡單說明] 若參閱前文中之詳細說明，並配合下列的圖式，將可 更易於了解本發明，這些圖式有： 弟1圖不出根據本發明而設定組態的一電腦系统； 弟2圖疋種根據本發明而提取寄生電阻及電容值以 便執行—延遲分析的方法之一流程圖；以及 第3圖疋一種根據本發明而提取寄生電阻及電容值以 便執订一電子遷移分析的方法之一流程圖。 1〇〇 112 150 114 ]2〇 電腦系統 系統匯流排 應用程式 隨機存取記憶體 磁碟單元 110 140 116 118 134 處理器 作業系統 唯讀記憶體 磁碟配接器 通訊配接器 92394 22 200405210 122 使用者介面配接器 136 顯示配接器 124 鍵盤 126 滑氣 130 口刺口八 138 顯示監視器 92394Irrns ^ S ^ er〇 ^ 4/3) *-xCap * crossMuIt, vdd, square (iequency * toggle〇) * square root (trf) ^ is the root mean square value of the current flowing through the interconnect; and its : The second is to save the rise time of signals such as% pulse signal. Medium, == (3G2), can identify each related interconnection line. In the example Γ step (3G1), the estimated average current or estimated 7 current exceeds a pre-selected threshold value, the crystals at the driving end of each relevant interconnection line, and the can be identified. That is, related interconnection lines such as multiple channel connections can be identified. • The drive end means the receiver end of the wire means the connection end. The channel is in step (303) + to identify the related interconnections: one or more transistors at the receiving end of one or more electrical and other related interconnection lines in the connection area of one or more channels are connected to the related One or more transistors in one or a region of the driving end of the interconnect and one or more transistors connected to the receiving end. The sub-signal of an interconnect line is from the end of the interconnect line sent from a driver. —Interconnection Refers to the interconnection of electronic signals that will be received by a receiver. 200405210 Connection area means an array of transistors that are connected between the related interconnection line and the power and ground lines. In step (304), the list identified by step (303) can be used to trim the list by selecting a circuit list containing a list of all the transistors in the integrated circuit to generate a number of copies Less transistor clear :. : By trimming the circuit list, "generating a smaller number of electric two lists, and performing the less complicated calculation of E extraction in the manner detailed below, thus using less memory and processing than previous techniques In addition, by selecting one or more transistors in one or more through-connection areas of the driving end of the related interconnects, and one or more transistors in the receiving end of the related interconnects, That is, the performance of the integrated circuit can be accurately simulated. The method of I is refined in step (305). 'The overall layout of the integrated circuit can be obtained from the overall layout of the related interconnect lines, that is, the electrical connection can be extracted. Any component of the related interconnects. For example, the through-holes of the related interconnects can be mentioned. 另一个 In another example, a software tool can be provided to extract the connected to the related interconnects In one embodiment of the present invention, when the layout τ of P ”is obtained by simply connecting to the layout layer connected to the Shengzhi connection, ^ ^, 忒 才 才 k are received. Coordinates of cloth crystals. These coordinates can refer to. The electric current of g should not be the position of the transistor in the integrated layout. As will be explained below, Kelly 2: Correlate each particular transistor in the extracted parasitic two-to-two coordinates of each layout layer. / Scoop Lu Qing 92394 20 200405210 Step (3 06, rh parasitic soft power generation ..., the capacity and resistance value of each extracted layout layer can be extracted. Keli 扪 uses Chu such as Vamplre and other markets Supplier :: To extract (that is, measure) each of the extracted layout layers (307), the extracted list of each extracted layout layer, the threshold value, and the circuit list for trimming The specific transistors are related: "In the step (305), the coordinates of the transistors connected to the white and local layers can be obtained. With these coordinates, each extraction can be made These extracted parasitic capacitances and resistance values of the layout layers are associated with each transistor of those extracted layout layers that are connected to the two-packed soap, by using the related interconnect lines. Each transistor in the channel connection area of the drive end and each transistor configuration of the receiving end of the related interconnects f = a list of trimmed circuits, that is, it can be performed in the manner detailed below. Rc extraction, thus using fewer notes than previous techniques: body and processing In addition, 'by associating the parasitic 4 and resistance value of each extracted layout layer with each transistor in the trimmed circuit list, P can perform an accurate simulation of the performance of the integrated circuit., Y "( The analysis can be performed in 3 0 8). For example, method (3 00) can be used to measure the electron migration in the integrated circuit. Please note that the extracted parasitic, threshing and resistance values are used to test the integrated circuit The electronic migration is known by this technology, Ding Zhongbai, so in order to take into account the conciseness of the description, the above process will not be described in detail. The month and the left, the method can be performed in a different order from the provided 92394 200405210 (300), and the sequence provided in the description of FIG. 3 is just an example. Please also note that 'the steps in FIG. 3 may be performed almost simultaneously. Although one has already referred to several embodiments, Describes the system, computer program product, and method, but does not limit the invention to the specific forms described in this specification; rather, the invention will cover the scope of patent applications that could reasonably be included in the final patent application Such alternatives, modifications, and equivalents are within the spirit and scope of the invention as defined. Please note that some headings are used for organizational purposes only, and that these headings are not intended to limit the scope of the description or patent application [Brief description of the drawings] If you refer to the detailed descriptions in the foregoing and cooperate with the following drawings, you will be able to understand the present invention more easily. These drawings are: A computer system; FIG. 2 is a flowchart of a method for extracting parasitic resistance and capacitance values according to the present invention for performing-delay analysis; and FIG. 3 is a flowchart of extracting parasitic resistance and capacitance values according to the present invention for subscription A flowchart of one method of electronic migration analysis. 10012 150 114] 2. Computer system system bus application program random access memory disk unit 110 140 116 118 134 processor operating system read-only memory disk Adapter Communication Adapter 92394 22 200405210 122 User Interface Adapter 136 Display Adapter 124 Keyboard 126 Sliding Air 130 Mouth Pierce 138 Display The monitor 92394