200404304 玫、發明說明： 【發明所屬之技術領域】 本發明係關於用於控制一元件之電子控制裝置，更具體 而吕，係關於一種能夠覆寫控制資料的電子控制裝置。 【先前技術】 控制資料，例如用於控制一元件等之控制程式及控制參 ^ ,儲存於一非揮發性記憶體（R〇M)中，藉此即使當電池 斷開且有時提供給使用者時控制資料亦不會被擦除。舉例 而τ，一電子控制裝置用於控制引擎、變速箱及其它汽車 ‘件且所產生的控制貝料鍺存於該電子控制裝置内的一 ROM 中。 在眾電子控制裝置裝入一汽車中之後，汽車製造商或經 銷商可能希望根據一受控元件（例如實際引擎或變速箱）之 特性來校準控制資料。因此，控制資料通常儲存於一可重 寫的非揮發性記憶體（例如一 EEPr〇m(電可擦可程式規劃 ROM)或一快閃記憶體（快閃EEPR〇M))中，從而可覆寫該等 控制資料。快閃EEPROM之特徵在於其内部電路相對簡單 且其成本較低。 快閃EEPROM之儲存區劃分為複數個儲存塊，因此在一 覆寫作業中可針對每一儲存塊擦除及/或寫入資料。舉例而 ;，對於一具有兩個儲存塊且每塊之儲存容量為32千位元 組（KB)的64 KB快閃EEPROM，每32 KB實施一資料覆寫作 業。然而，對於快閃EEPR0M ,在實施一資料覆寫作業時 ，該儲存塊内的資料無法讀出。 404304 )中余；，閃EEPR0M，與在-Ram(隨機存取記憶體 相—資料覆窝作業所需時間很長。因此， ^要根據-受控元件（例如_引擎）之特性實施校準，則擬 件 〗EEPR0M之貪料通常暫時儲存於一外部儲存元 外.…除錯器)中。爾後，在引擎停機後，使用儲存於該 卜邵儲存元件中的資料對快閃EEP峨實施—覆寫作業。 若要對單個快閃EEP職實施多項校準，則需針對 母技準重複上述作業，該等重複作業極其耗時。 本發明針對上述問題而設計，且其目標為提供—種即使 l制作業過程中亦能夠對—非揮發性記憶體實施资料 覆寫作業的電子控制裝置。 ” 【發明内容】 —為解決上述問題’根據中請專利範圍第旧之本發明提供 —種具一有—非揮發性記憶體和-揮發性記憶體的電子控制 ^置$非料性憶體與揮發性記憶财儲存用於控制 —元件之控财料。該電子控制裝置包括―控制器，該卢 ㈣使用儲存㈣發性記憶體内的資料來實施控制資料的 乂準’並在完成校準後將儲存於揮發性記憶體内的資料寫 入至非揮發性記憶體。 — 工根據申請專利範圍第2項之本發明提供申請專利範圍第i :之包子控制裝置’其中該控制器在校準開始時，將擬校 卞非揮發性C憶體内的資料儲存於揮發性記憶體中’·並使 用儲存於揮發性記憶體内的資料來校準控制資料。 根據申請專利範圍第3項之本發明提供申請專利範圍第五 200404304 項或第2項之電子控制裝置，其中該控制器進—步識別擬校 準非揮發性記憶體的一位址，並在校準開始時，賦予揮發 性記憶體相同於非揮發性記憶體之位址，並在校準過程^ 優先為揮發性記憶體實施資料處理。 工根據申請專利範圍第4項之本發明提供申請專利範圍第i 項至第3項中任一項之電子控制裝置，其進_步包括一用於 拴制非揮發性記憶體中資料的控制暫存器，其中該控制器 在权準％成時，將非揮發性記憶體之位址及已校準控制資 料寫入至孩控制暫存器，並利用寫入至該控制暫存器中的 位址和已校準控制資料來寫人至非揮發性記憶體。 根據中請專利範圍第5项之本發明提供申請專利範圍第* 項<電子控制裝置，其進一步包括一用於控制該控制暫存 咨使用榷限的權限暫存器，其中當寫入至揮發性記憶體時 私控制構件設定該權限暫存器’並在窝入作業完成後，清 除該權限暫存器。 項m清中專利範圍第6項之本發明提供申請專利範圍第1 /、至弟5頁中任一項j當不 %子控制裝置，其中該 個單元；控制資料儲转❹於|…^ ^有複數 體内；揮發性記_1# ft早7^非揮發性記憶 控制資料的儲存容量。 々 根據申請專利範圍第7項之 項至第6項中任-項之電计制申請專利範圍第1 且有至，丨、忐徊·+、夕 制裝置，其中非揮發性記憶體 〆、有至/兩個或多個儲存塊；针對每一储 業；當窝入儲存塊時，使用_ 貝’’’· 儲存塊控制該元件。 200404304 根據申請專利範圍第丨項所述之本發明，儲存於揮發性記 憶體中的資料用於實施控制資料的校準。當校準完成後， 將儲存於揮發性記憶體中的資料寫入至非揮發性^憶體。 因此，安裝於電子控制裝置中的揮發性記憶體可用於校準 储存有用於控制該元件之控制資料的非揮發性記憶體。在 錢情況下’無需使用-外部儲存幻牛（例如_除錯器）即可 貫施校準。藉由實施此一寫入作業，可在受控元件正在運 作的同時達成校準。 根據申請專利範圍第2項所述之本發明，當校準開始 擬校準非揮發性記憶體中的資料將儲存入揮發性記外中 ，並使用儲存於揮發性記憶體中的資料來校準控制資料。 因此，可使用預調整控制資料作為—起點來達成校準。藉 由將標準控制資料儲存入非揮發 — 非禪發己憶體中，僅需根據受 控兀件特性貫施微調，由此可達成有效校準。 根據申請專利範圍第3項所述之本發明，在校準開始時， 識別擬校準的非揮發性記憶體之位址。爾後，賦予揮發性 記憶體相同於該非揮發性記憶體之位址，且在校準過^中 ’優先為揮發性記憶體實施資料 , 园+ “十處理。料在記憶體配置 圖中，將揮發性記憶體之記悻髀 .^ ^ 匕^月且^域設足為交疊於擬校準 〜豆區域《上。因此，該電子控制裝置即使在校準作業 中亦可照樣使用一個位址來控制該元件。 根據申請專利範圍第4項所 ㈣^^ 本發明，#校準完成後， ::發性記憶眼之位址及已校準控制資料寫入至控 咨中。爾後，使用儲存於該控制暫存器中的位址及已校準 200404304 控制資料來執行-非揮發性 的資料菸 〜且窝入。揮發性記憶體中 中:科了藉由该控制暫存器可靠地窝入至非揮發性記憶體 ^據中請㈣_第5項所述之本發明，該電子 一有一用於控制該控制暫存 窝入恭…. “吏用權限的權限暫存器。當 馬入至揮發性記憶體時， 作業1接、1 將叹疋邊權限暫存器；而在寫入 業“後，孩榷限暫存器將被清除。因 > —寫入作業時對該控制暫存哭每，A、 了在貝她 利負存态貫施？己憶體管理。 «申請專利範圍第6項所述之本發明，揮發性記憶體具 说夠储存對應於擬校準單元的控制資料的儲 :此，揮發性記憶體错存容量可限制為校準所需容 此可減小該電子控制裝置之尺寸並降低其成本。 根據申請專利範圍第7項所诚 4 /、 焱明，非揮發性記憶體 :括土少兩或多個儲存塊，且針對每一儲存塊分別實施一 寫入作業。當寫入至儲存塊時， 一从 j使用另一儲存塊控制該 疋件。由此可在元件正在受垆车 4時覆寫非揮發性記憶體中的 控制讀n無需重新啟動受控元件或電 即可有效達成校準。 表置 【實施方式】 下文參照圖i至圖7詳細閣述本發明一具體實施例。在兮 具體實施例中’如圖i所示，假定使用—電子控制單： (E C U) i 〇來控制-受控目標i i (例如一汽車引擎）。亦即 則1〇安裝於汽車内之後，校準作為控制資料的控制參數 ，猎以控制構成該汽車的每一單元。 10 200404304 該 ECU 10 包括一 CPU ion ^ ☆ 1 、一作為非揮發性記憶體的快 閃EEPR0M 1 0 1及一作Λ揎菰认、r F局俾發性記憶體的校準RAM 1 02。該 ECU 1 0亦包括未圖示的_ B每扭 J時鐘楗組及一 A/D轉換器等等。 該CPU 100組態用於執杆锉左、人 奶4仃崎存於快閃eeprom 1 0 1、校準 RAM 102等中的各種程式。 f夬閃EEPROM 101包含關於由Ecu用於控制的控制指令 和I制參數的貝料。泫具體實施例中所用快閃EEpR〇M ^ 〇工 共具有64千位7C組（KB)的儲存容量。儲存區域由32 KB的儲 存塊（在記憶體配置圖中分別為，，塊〇 ”和，，塊1Π)組成。對於一 覆寫作業，逐塊實施一資料擦除和一寫入作業。對於每一 爻控單元，"塊0”包含相關於控制指令之資料，而"塊丨"則包 含相關於控制參數之資料。在該具體實施例中，假定在控 制受控目標11的過程中，”塊〇”中的一控制指令可導致覆寫 ’’塊1"中的控制參數。 k + RAM 102係一用於在校準過程中暫時儲存預定資料 的记fe體。對於該校準RAM 102，應使用一其儲存容量能 夠儲存對應於每一受控單元的控制參數的記憶體。該具體 實施例中的校準RAM 1〇2具有2 KB的儲存容量。 ECU 10進一步包括一輸入/輸出介面部分no。ecu 10之 母一部分皆藉由該輸入/輸出介面部分12〇連接至一使用者 介面部分12及一受控目標11。該使用者介面部分12由使用 者用於指定受控目標11並確認參數。 受控目標11為一元件，例如一引擎、變速箱和擬控制的 其b元件。ECU 10自安裝於受控目標11中的各傳感器接收 200404304 奢枓’並藉由輸入/輸出介面部分m將資料輸出至致器 等等。 1 00藉由k址匯 >瓦排連接至一位址解碼器1 1 Q。該 4止解碼咨110根據_纟自CPU 100的位址信號將一信號輸 出至其對應輸出端。在該具體實施例中，CPUi⑽及位址解 碼器110用作控制構件。 位址解碼器no包括一初始化暫存器丨丨卜該初始化暫存 器111包括：一用於儲存相關於一實施校準區域之位址的資 料的區域，及一用於儲存相關於校準RAM i 02之激活的資 料的區域（激活位元）0在該具體實施例中，當校準RAM102 激活時，激活位元中將輸入” 1 ”。 此外，ECU 10包括一超級使用者模式暫存器112作為一權 限暫存器，其用於控制該模式（在下文中稱作，，超級使用者 模式”）以針對快閃EEPr〇M 1〇1授予一覆寫權限。當設定為 超級使用者模式時，包含於超級使用者模式暫存器112中的 權限位元中將輸入” 1 ”。 ECU 10進一步包括一快閃控制暫存器U3作為一控制暫 存器，用於控制非揮發性記憶體中的資料。該快閃控制暫 存器113用於超級使用者模式中。該快閃控制暫存器113保 留擬寫入至快閃EEPROM 101的位址及已校準控制參數。 此外，CPU 100、校準RAM 102、快閃控制暫存器113及 輸入/輸出介面部分120分別連接至資料匯流排，從而藉由 資料匯流排發送和接收資料。 接下來，將參照圖2至圖7闡述ECU 10所實施作業中一用 12 200404304 於將儲存於快閃EEPROM 101中的資料重寫為適合於受控-目標11之資料之作業。 在ECU 10正在依據儲存於快閃EEPROM 101中的資料控 制受控目標11的同時，使用者可使用使用者介面部分12發 出一有關受控目標11之校準指令。該指令藉由輸入/輸出介 面部分120及資料匯流排傳送至CPU 100。 隨後，ECU 10進入校準模式，在該校準模式下開始圖2 所述之過程。首先，CPU 100確定快閃EEPROM 101上的一 _ 校準區域（S 1-1)。在彼種狀況下，CPU 100向初始化暫存器 111之激活位元輸入"1 ”，以激活校準RAM 1 02。此外，一實 施校準區域之位址儲存於初始化暫存器u丨中。 然後，將快閃EEPROM之校準區域中的資料複製至校準 RAM 1 02(S 1 -2)。此一作業參照圖4所示的一記憶體配置圖 500來闡述。在該記憶體配置圖5〇〇中設定有：一對應於校 準RAM 102的記憶體區域501 ; 一對應於快閃eePR0M 1〇1 之’’塊〇’’的記憶體區域502 ;及一對應於其”塊丨，，的記憶體區 _ 域503。在該具體實施例中，記憶體區域5〇3中的位置6〇〇〇 至67FF假定為一校準區域504。然後，在步驟（S1-2)中，將 权準區域504中的資料複製至對應於校準RAM i 〇2的記憶 體區域501。 然後，將校準RAM 102交叠於校準區域之上（sl-3)。此一 作業參照圖5所示的記憶體配置圖51()來闡釋。在該步驟中 ，在記憶體配置圖510上設定的校準RAM 1〇2之記憶體區域 501匹配到針對校準區域5〇4設定的位址。此意味著為記憶 13 200404304 體區域501與校準區域504賦予同一位址。 然後，根據受控目標丨丨之特性執行校準處理（si_4)。此一 作業參照圖3所示流程圖來閣釋。使用者可使用使用者介面 部分12發出一針對用於控制受控目標丨丨的參數資料等的修 改指令（S2-1)。在彼種狀況下，cpu 1〇〇將執行各種作業， 例如讀取或覆寫記憶體配置圖5 1 0上的資料。 右需處理叉疊校準RAM丨〇2的記憶體區域（當在步驟 (S2-2)中選擇”是”時），則依據校準ram 1〇2中的資料實施 處理（S2-3)。亦即，若在初始化暫存器ln之激活位元中設 定，τ’，則針對賦予快閃EEPR0M 101與校準RAM 1〇2相同 位址（在該具體實施例中為位置6〇〇〇至67FF)的記憶體區域 所實施的每一處理，亦會針對校準RAM 1〇2之記憶體區域 5 0 1貫施。 反之，若需處理未交疊校準RAM 102的區域（當為，，否，，時） ，則照常在？己憶體配置圖5 1 0上快閃EEPROM 1 0 1中的資料 上貝施處理（S2-4) 〇 然後’若具有任何新的資料處理指令（當在步驟（S2-5)中 選擇’’否”時），則重複步驟（S2-1)至（S2-4)來實施校準。反之 ，右找到一適用於受控目標11的合適參數值，則使用者可 使用使用者介面部分12發出一指令來結束校準。若發出一 用於結束扠準的指令（當在步驟（S2-5)中選擇，，是"時），則常 式將返回圖2所示的流程。 接下來’設定為超級使用者模式（S1_5)。具體而言，在超 、及使用者模式暫存器112之權限位元中輸入” 1 ”。在彼種狀 14 200404304 況下，儲存於校準RAM 102中的控制參數將寫入快閃· EEPROM 101中（S1-6)。亦即，如同圖6中記憶體配置圖52〇 所示，設定於記憶體配置圖52〇上的校準raM 102之記憶體 區域501中的資料將寫入至校準區域5〇4。具體而言，在超 級使用者模式中，可在記憶體配置圖上存取快閃控制暫存 斋113。然後，儲存於校準ram 102中的位址和資料寫入至 快閃控制暫存器113中。此外，根據儲存於快閃控制暫存器 11 3中的位址，將儲存於快閃控制暫存器丨丨3中的資料寫入 _ 至快閃EEPROM 101上的位址中。同時，ECU 1〇繼續依據 儲存於記憶體區域502中的資料來控制受控目標U。 當該程式結束時，清除超級使用者模式暫存器112之權限 位元，且退出超級使用者模式並返回正常模式。此外，初 始化暫存為111之設定發生改變（s 1-7)。此時，初始化暫存 器111之激活位元被清除，由此產生圖7所示的一記憶體配 置圖530。亦即校準ram 102之記憶體區域501被移除，且 在a己憶體配置圖530中生成已寫入校準ram 1 0 2之資料之 馨 校準區域531。然後，ECU 10使用快閃EEPR〇M 101中的覆 寫資料來控制受控目標11。隨後，快閃EEpR〇M之覆寫作 業結束。 根據前述之具體實施例，可獲得下列特點。在前述具體 貫施例中，ECU 10包括快閃控制暫存器1丨3，並在校準結束 時進入超級使用者模式。在該模式中，快閃控制暫存器η 3 變得可在記憶體配置圖上存取。然後，使用快閃控制暫存 器113將儲存於校準ram 102内的資料程式規劃入快閃 15 200404304 EEPROM 101。因此，即使在£(：11 1〇正在作業時，亦可擦 除或覆寫快閃EEPROM 101之一特定區域中的資料。按常規 ，在覆寫快閃EEPR0M 101之前，受控目標丨丨須停機且EC：lj 1 〇足控制將中斷。因此，當實施另一校準時，需重新啟動 ECU 10及受控目標n。在彼種情況下，啟動後，受控目標 11等需經過一段時間方可穩定。而根據該具體實施例所述 ’藉由在受控目標11仍在作業的同時實施校準，則可更快 完成校準任務。 在則述具體實施例中，可使用超級使用者模式在ECU 1 0 作業過程中實施校準。因此，即使在校準RAM 1〇2較小（例 如2 KB)時，亦可有效達成校準。藉由使用此一小容量校準 RAM 102 ’可縮小Ecu 1〇之尺寸。此外，由於ram相當昂 貝因此使用一小的校準RAM 102可容許降低ecu 1〇之成 本° 在前述具體實施例中，安裝於ECU 10中的校準RAM 102 用於覆寫快閃EEPROM 101中的資料。亦即ECU 1〇自身具 有一用於覆寫快閃EEPR〇M丨〇丨中資料的機制。其使得無需 將校準資料儲存至_外部儲存㈣（例如—除錯器）中。由此 可有效覆寫儲存於快閃]^1>11〇1^ 1〇1中的資料。 在則述具體實施例巾，在校準開始時，實施校準之區域 的-位址將儲存於初始化暫存器lu中。該位址可用於將快 閃EEPROM 1〇1中的資料複製至校準ram 1〇2，並在快閃 EEPROM 101《校準區域5〇4内設定校準RAM 1〇2之記憶體 區或50 1此思味著可根據校準區域來設定校準RAM ! 〇2之 16 200404304 設定區域。 應睁解，前述具體實施例可作如下修改。在前述具體實 施例中，田&式結束時，將清除超級使用者模式暫存器ιΐ2 之權限位TL ’且退出超級使用者模式以返回至正常模式。 同時，清除初始化暫存器lu之激活位元。反之，若連續實 犯另又拴目标1 1 < 4父準，邺可在初始化暫存器丨丨丨中設定 貝她-新;k準作業之區域之位址，同時使初始化暫存器 ill之激活位元維持為”P，由此可連續實施校準。 在則述具體貫施f列中，使用一具有2 KB儲存容量的校準 RAM 102，儘官其並非限定於此。其容量可涵蓋—單一校 準所需的記憶體區域。此外，可使用—具有更大儲存容量200404304 Description of the invention: [Technical field to which the invention belongs] The present invention relates to an electronic control device for controlling a component, and more specifically, to an electronic control device capable of overwriting control data. [Prior art] Control data, such as control programs and control parameters used to control a component, are stored in a non-volatile memory (ROM), thereby providing it even when the battery is disconnected and sometimes used Control data will not be erased. For example, τ, an electronic control device is used to control engines, transmissions, and other automotive components, and the generated control material is stored in a ROM in the electronic control device. After the electronic controls are installed in a car, the car manufacturer or dealer may wish to calibrate the control data based on the characteristics of a controlled component, such as an actual engine or transmission. Therefore, the control data is usually stored in a rewritable non-volatile memory (such as an EEPROM (Electrically Erasable Programmable Programming ROM) or a flash memory (Flash EEPROM)), so that Overwrite such control information. Flash EEPROMs are characterized by relatively simple internal circuits and low cost. The storage area of the flash EEPROM is divided into a plurality of storage blocks, so data can be erased and / or written for each storage block in an overwrite operation. For example, for a 64 KB flash EEPROM with two storage blocks each with a storage capacity of 32 kilobytes (KB), a data overwrite operation is implemented every 32 KB. However, for flash EEPR0M, when a data overwrite operation is performed, the data in the storage block cannot be read. 404304), flash; EEPR0M, and -Ram (random access memory phase-data overlay operation takes a long time. Therefore, ^ to perform calibration based on the characteristics of-controlled components (such as _ engine), The proposed material EEPR0M is usually temporarily stored in an external storage unit (... debugger). Then, after the engine is stopped, the data stored in the storage element of the Bu Shao is used to perform the flash-over EEP-overwrite operation. To perform multiple calibrations for a single flash EEP job, the above operations need to be repeated for the master technique, and these repeated operations are extremely time-consuming. The present invention is designed to solve the above problems, and an object thereof is to provide an electronic control device capable of performing a data overwriting operation on a non-volatile memory even during a manufacturing operation. [Contents of the invention]-In order to solve the above-mentioned problem, according to the invention of the oldest patent in the scope of the Chinese Patent Application, an electronic control of a non-volatile memory and a volatile memory is provided. And the volatile memory are used to control the control of the components. The electronic control device includes a controller, which uses the stored data in the memory to implement the control of the data and perform calibration. Then the data stored in the volatile memory is written to the non-volatile memory. — The worker provides a bun control device according to the scope of patent application i of the scope of patent application: 'The controller is being calibrated according to the invention of the scope of patent application item 2. At the beginning, the data in the non-volatile C memory to be calibrated is stored in the volatile memory 'and the data stored in the volatile memory is used to calibrate the control data. According to the third item of the scope of patent application The invention provides an electronic control device with a patent scope of 5,200,404,304 or 2, wherein the controller further identifies a bit address of the non-volatile memory to be calibrated, and starts the calibration At the same time, the address of the volatile memory is the same as that of the non-volatile memory, and the data processing is given priority to the volatile memory during the calibration process. The electronic control device according to any one of items 3 to 3, further comprising a control register for binding data in the non-volatile memory, wherein the controller will The address of the volatile memory and the calibrated control data are written to the child control register, and the address and the calibrated control data written to the control register are used to write the person to the non-volatile memory. According to the invention of claim 5, the invention provides a scope of application for a patent * item < an electronic control device, which further includes a permission register for controlling the control register, and when written to When the volatile memory is used, the private control component sets the permission register 'and clears the permission register after the nesting operation is completed. Item m Qingzhong Patent Scope Item 6 of the invention provides patent application scope No. 1 /, To page 5 Any one of them is not a sub-control device, in which the unit; the control data storage is transferred to | ... ^ ^ there is a plural body; volatile record _1 # ft 早 7 ^ non-volatile memory control data storage capacity 々Applies to the electric meter system according to any of the 7th item to the 6th item of the patent application scope. The patent application scope is 1 and there are, 丨, 忐, +, and evening devices, of which non-volatile memory. There are up to / two or more storage blocks; for each storage industry; when the storage blocks are nested, use _ shells to control the element. 200404304 According to item 丨 of the scope of patent application According to the invention, the data stored in the volatile memory is used to implement the calibration of the control data. After the calibration is completed, the data stored in the volatile memory is written to the non-volatile memory. Therefore, it is installed in the electronics The volatile memory in the control device can be used to calibrate the non-volatile memory that stores control data for controlling the component. In the case of money, calibration is performed without the use of external storage (such as _ debugger). By performing this writing operation, calibration can be achieved while the controlled component is operating. According to the invention described in item 2 of the scope of the patent application, when the calibration is started, the data in the non-volatile memory will be stored in the volatile memory, and the data stored in the volatile memory will be used to calibrate the control data. . Therefore, calibration can be achieved using pre-adjusted control data as a starting point. By storing the standard control data in a non-volatile-non-zen hair memory, you only need to fine-tune it consistently based on the characteristics of the controlled element, thereby achieving an effective calibration. According to the invention described in item 3 of the scope of the patent application, at the beginning of calibration, the address of the non-volatile memory to be calibrated is identified. After that, the volatile memory is given the same address as the non-volatile memory, and in the calibration process, the data of the volatile memory is preferentially implemented, and the "+" processing is performed. It is expected that the volatile memory will be volatile. The memory of sex memory. ^ ^ ^ ^ Month and ^ field is set to overlap on the to-be-calibrated ~ bean area ". Therefore, the electronic control device can still use an address to control even in the calibration operation According to the invention described in item 4 of the scope of the patent application, the invention ## After calibration is completed, :: the address of the memory eye and the calibrated control data are written to the controller. After that, use the stored in the control The address in the register and the 200404304 control data that has been calibrated to perform-non-volatile data smoke ~ and nested. In the volatile memory: the control register reliably nested into non-volatile by this control register Sexual memory ^ According to the invention described in item 5 above, the electronic one has a permission register for controlling the temporary storage of the control memory .... When the horse enters the volatile memory, assignment 1 and 1 will sigh the edge register; after writing to the industry, the child limit register will be cleared. Because> This control is stored temporarily. A. In the negative state of Bethali? Continuous memory management. «Applicable to the invention described in item 6 of the scope of patent application, volatile memory is said to be sufficient to store corresponding to the intended calibration. Storage of control data of the unit: As a result, the volatile memory's misstored capacity can be limited to the capacity required for calibration. This can reduce the size of the electronic control device and reduce its cost. Ming, non-volatile memory: include two or more storage blocks, and implement a write operation for each storage block. When writing to the storage block, one from j uses another storage block to control the This allows the control read in the non-volatile memory to be overwritten when the component is receiving the car 4. Calibration can be effectively achieved without restarting the controlled component or electricity. Table Setting [Embodiment] Refer to Figure i below A specific embodiment of the present invention is described in detail in Fig. 7. In the embodiment, 'as shown in FIG. I, it is assumed that an electronic control unit: (ECU) i 〇 is used to control-a controlled target ii (such as an automobile engine). That is, after 10 is installed in a car, it is calibrated as a control. The control parameters of the data are used to control each unit that constitutes the car. 10 200404304 The ECU 10 includes a CPU ion ^ ☆ 1, a flash EEPR0M 1 0 1 as a non-volatile memory, and r F RAM calibration RAM for local memory 102. The ECU 10 also includes an unillustrated _ B clock unit and an A / D converter, etc. The CPU 100 is configured for execution. Various files are stored in the flash file eeprom 1 0 1 and flash memory eeprom 1 0 1, calibration RAM 102, etc. f flash EEPROM 101 contains shell material for control instructions and I-parameters used by Ecu for control.快 The flash ERepROM used in the specific embodiment has a total storage capacity of 64 kilobytes of 7C group (KB). The storage area consists of 32 KB storage blocks (in the memory configuration diagram, respectively, block 0 " And, block 1Π). For an overwrite operation, a data erase and a write operation are performed block by block. For each control unit, " block 0 " contains data related to control instructions, and " block 丨 " contains data related to control parameters. In this specific embodiment, it is assumed that the control target 11 is controlled. During the process, a control instruction in "Block 0" may cause the control parameters in "Block 1" to be overwritten. K + RAM 102 is a memory for temporarily storing predetermined data during calibration. For this The calibration RAM 102 should use a memory having a storage capacity capable of storing control parameters corresponding to each controlled unit. The calibration RAM 102 in this embodiment has a storage capacity of 2 KB. The ECU 10 further includes an input The I / O interface part no.ecu 10 is connected to a user interface part 12 and a controlled target 11 through the I / O interface part 120. The user interface part 12 is used by the user to designate a receiver. Control target 11 and confirm the parameters. Control target 11 is a component, such as an engine, transmission, and its b component to be controlled. ECU 10 receives 200404304 from the sensors installed in controlled target 11 and The input / output interface part m outputs data to the actuator, etc. 1 00 is connected to a bit decoder 1 k by the k address sink> 1 watt. The 4 decoding decoder 110 is based on the CPU 100 The address signal outputs a signal to its corresponding output terminal. In this specific embodiment, the CPUi and the address decoder 110 are used as control components. The address decoder no includes an initialization register. The memory 111 includes an area for storing data related to an address of an implementation calibration area, and an area (activation bit) for storing data related to activation of the calibration RAM 102. In this specific implementation, For example, when the calibration RAM 102 is activated, "1" will be entered in the activation bit. In addition, the ECU 10 includes a super user mode register 112 as a permission register, which is used to control the mode (hereinafter referred to as Operation, super user mode ") to grant an overwrite permission for the flash EEPrOM 1101. When the super user mode is set, "1" will be entered in the permission bit included in the super user mode register 112. The ECU 10 further includes a flash control register U3 as a control register for controlling data in the non-volatile memory. The flash control register 113 is used in the super user mode. The flash control register 113 holds the address to be written to the flash EEPROM 101 and the calibrated control parameters. In addition, the CPU 100, the calibration RAM 102, the flash control register 113, and the input / output interface section 120 are connected to a data bus, respectively, so as to send and receive data through the data bus. Next, the operation performed by the ECU 10 in the operation performed by the ECU 10 will be described with reference to FIG. 2 to FIG. 7 to rewrite the data stored in the flash EEPROM 101 into data suitable for the controlled-target 11 data. While the ECU 10 is controlling the controlled target 11 based on the data stored in the flash EEPROM 101, the user can use the user interface section 12 to issue a calibration instruction regarding the controlled target 11. The instruction is transmitted to the CPU 100 through the input / output interface section 120 and the data bus. Subsequently, the ECU 10 enters a calibration mode, in which the process described in FIG. 2 is started. First, the CPU 100 determines a calibration area on the flash EEPROM 101 (S 1-1). In that case, the CPU 100 inputs " 1 " to the activation bit of the initialization register 111 to activate the calibration RAM 102. In addition, the address of an implementation calibration area is stored in the initialization register u. Then, the data in the calibration area of the flash EEPROM is copied to the calibration RAM 1 02 (S 1 -2). This operation is explained with reference to a memory configuration diagram 500 shown in FIG. 4. In this memory configuration diagram 5 〇〇 is set: a memory area 501 corresponding to the calibration RAM 102; a memory area 502 corresponding to the `` block 0 '' of the flash eePR0M 1101; and a corresponding block 501, Memory area_field 503. In this specific embodiment, positions 6,000 to 67FF in the memory area 503 are assumed to be a calibration area 504. Then, in step (S1-2), the data in the weighting area 504 is copied to the memory area 501 corresponding to the calibration RAM 102. Then, the calibration RAM 102 is overlapped over the calibration area (sl-3). This operation is explained with reference to the memory configuration diagram 51 () shown in FIG. 5. In this step, the memory area 501 of the calibration RAM 102 set on the memory map 510 matches the address set for the calibration area 504. This means that the memory 13 200404304 gives the same address to the body area 501 and the calibration area 504. Then, a calibration process (si_4) is performed according to the characteristics of the controlled target. This operation is explained with reference to the flowchart shown in FIG. 3. The user can use the user interface section 12 to issue a modification instruction (S2-1) for parameter data and the like for controlling the controlled target. In that case, the CPU 100 will perform various tasks, such as reading or overwriting the data on the memory configuration figure 5 10. The right needs to process the memory area of the cross-stack calibration RAM 丨 02 (when “Yes” is selected in step (S2-2)), the processing is performed according to the data in the calibration ram 102 (S2-3). That is, if τ ′ is set in the activation bit of the initialization register ln, the flash EEPR0M 101 is assigned the same address as the calibration RAM 10 (in this specific embodiment, the position is 6000 to 600). 67FF) each process carried out in the memory area will also be performed for the memory area 501 of the calibration RAM 102. Conversely, if it is necessary to process the area of the non-overlapping calibration RAM 102 (when ,, no ,, when), is it still there? Memories configuration Figure 5 1 Flash data on flash EEPROM 1 0 1 Bash processing (S2-4) 〇 Then 'if there are any new data processing instructions (when selected in step (S2-5)' ('No'), repeat steps (S2-1) to (S2-4) to perform calibration. Conversely, if a suitable parameter value for the controlled target 11 is found on the right, the user can use the user interface section 12 Issue a command to end the calibration. If a command is issued to end the cross calibration (when selected in step (S2-5), it is "), the routine will return to the flow shown in Figure 2. Next 'Set to super user mode (S1_5). Specifically, enter "1" in the permission bits of the super and user mode registers 112. In the case of the other state 14 200404304, it is stored in the calibration RAM 102. The control parameters in will be written into the flash · EEPROM 101 (S1-6). That is, as shown in the memory configuration diagram 52 in FIG. 6, the memory of the calibration raM 102 set in the memory configuration diagram 52. The data in the body area 501 will be written to the calibration area 504. Specifically, in the super user mode, The flash control register 113 can be accessed on the memory map. Then, the address and data stored in the calibration ram 102 are written to the flash control register 113. In addition, according to the storage in the flash control register 113 The address in the register 11 3 writes the data stored in the flash control register 丨 3 into the address on the flash EEPROM 101. At the same time, the ECU 10 continues to store the data in the memory according to The data in area 502 controls the controlled target U. When the program ends, clear the permission bits of the superuser mode register 112 and exit the superuser mode and return to normal mode. In addition, the initial temporary storage is 111 The setting is changed (s 1-7). At this time, the activation bit of the initialization register 111 is cleared, thereby generating a memory configuration diagram 530 shown in FIG. 7. That is, the memory area of the ram 102 is calibrated. 501 is removed, and a calibration area 531 of the data written in the calibration memory ram 1 0 2 is generated in a memory configuration map 530. Then, the ECU 10 uses the overwrite data in the flash EEPROM 101 to control Controlled target 11. Subsequently, the overwriting operation of the flash ERepROM is completed According to the foregoing specific embodiment, the following characteristics can be obtained. In the foregoing specific embodiment, the ECU 10 includes a flash control register 1 and 3, and enters the super user mode at the end of the calibration. In this mode, The flash control register η 3 becomes accessible on the memory map. Then, the flash control register 113 is used to program the data program stored in the calibration ram 102 into the flash 15 200404304 EEPROM 101. Therefore, the data in a specific area of the flash EEPROM 101 can be erased or overwritten even when £ (: 11 10 is in operation. Conventionally, before the flash EEPR0M 101 is overwritten, the controlled target 丨 丨Must stop and EC: lj 1 0 foot control will be interrupted. Therefore, when another calibration is performed, ECU 10 and controlled target n need to be restarted. In that case, controlled target 11 and so on need to go through a period after startup. Time can be stable. According to the specific embodiment, 'by performing the calibration while the controlled target 11 is still operating, the calibration task can be completed faster. In the specific embodiment described above, a super user can be used The mode is calibrated during the ECU 10 operation. Therefore, even when the calibration RAM 10 is small (for example, 2 KB), the calibration can be effectively achieved. By using this small capacity calibration RAM 102 ', Ecu 1 can be reduced In addition, the use of a small calibration RAM 102 may allow the cost of ecu 1 to be reduced because the ram is quite large. In the foregoing specific embodiment, the calibration RAM 102 installed in the ECU 10 is used to overwrite the flash memory. Data in EEPROM 101. Also That is, the ECU 10 has a mechanism for overwriting the data in the flash EEPROM 丨 〇 丨. It eliminates the need to store calibration data in _external storage㈣ (eg, debugger). This can effectively overwrite Write the data stored in the flash] ^ 1> 11〇1 ^ 1〇1. In the specific embodiment described above, at the beginning of the calibration, the address of the area where the calibration is performed will be stored in the initialization register lu. This address can be used to copy the data in the flash EEPROM 101 to the calibration ram 102, and set the memory area of the calibration RAM 10 or 50 1 in the flash EEPROM 101 "calibration area 504". This means that the calibration RAM can be set according to the calibration area! 〇2 of 16 200404304 setting area. It should be opened. The foregoing specific embodiment can be modified as follows. In the foregoing specific embodiment, the field & Supervisor mode register ΐ2's permission bit TL 'and exit the superuser mode to return to normal mode. At the same time, clear the activation bit of the initialization register lu. Conversely, if the continuous actual commits another target 1 1 < 4 fathers, you can initialize the register 丨 丨 丨Set the address of the Beta-New; k quasi-operation area, and maintain the activation bit of the initialization register ill to "P", so that calibration can be performed continuously. In the specific implementation of column f, use A calibration RAM 102 with a storage capacity of 2 KB, which is by no means limited to this. Its capacity can cover-the memory area required for a single calibration. In addition, it can be used-has a larger storage capacity
之校準RAM 102來同時對更多受控目標丨丨實施校準。The calibration RAM 102 performs calibration on more controlled targets simultaneously.
在前述具體實施例中，在控制受控目標11的作業過到 ，使用快閃EEPROM 101之”塊〇"的一控制指令來覆寫，，塊i 的控制參數，儘管其並非限定於此。可於一包括一需要赛 寫的快閃EEPROM 101的電子控制裝置中實施此作業。 在前述具體實施例中，快閃EEPR〇M 1〇1之校準區域中的 貝料在步驟S 1 -2中複製至校準ram 1 02。或者，若在該栌 準區域中無控制資料，可跳過該步驟。 在前述具體實施例中，受控目標u(例如一汽車引擎）由電 子控制裝置（ECU 10)控制，儘管其並非限定於此。關鍵在 於，該裝置可包括一快閃EEPROM 101，且可於一可執行自 身資料覆寫的電子控制裝置中實施。 如上文之詳述，根據本發明，即使在控制作業期間亦可 17 200404304 覆寫非揮發性記憶體之資料。 【圖式簡單說明】 圖1為一闡釋本發明一具體實施例之ECU(電子控制裝置） 之總體結構的示意圖； 圖 圖2為一用於解釋一快閃EEPR〇M之覆寫作業的流程圖； 圖3為另—用於解釋一快閃EEpR〇M之覆寫作業的流程 圖4為一記憶體配置圖之說明圖； 圖5為一記憶體配置圖之另一說明圖； 圖6為—記憶體配置圖之再一說明圖； 圖7為- 一 ？己憶體配置圖之又一說明圖 【圖式代表符號說明】 10 電子控制單元（ECU) 11 受控目標 12 使用者介面 100 CPU 101 快閃EEPROM 102 校準RAM 110 位址解碼器 111 初始化暫存器 112 超級使用者模式暫存器 113 快閃控制暫存器 120 I/O介面 位址匯流排 資料匯流排 開始 18 200404304 (Sl-l) (Sl-2) (Sl-3) (Sl-4) (Sl-5) (Sl-6) (Sl-7) (S2-1) (S2-2) (S2-3) (S2-4) (S2-5) 500 501 502 503 504 510 520 530 531 確定快閃EEPROM上的校準區域 將校準區域中的資料複製至校準RAM 將校準RAM交疊於校準區域之上 校準處理 設定超級使用者模式 使用快閃控制暫存器將校準RAM中的 資料程式規劃至快閃EEPROM中 改變初始化暫存器的設定 結束 校準處理 發出資料處理指令 處理交疊校準RAM之區域？ 根據校準RAM中的資料處理 根據快閃EEPROM中的資料處理 結束校準？ 返回 是 否 記憶體配置圖 校準RAM 快閃EEPROM(塊0) 快閃EEPROM(塊1) 校準區域 記憶體配置圖 記憶體配置圖 記憶體配置圖 校準區域 19In the foregoing specific embodiment, when the operation of controlling the controlled target 11 is over, a control instruction of the "block 0" of the flash EEPROM 101 is used to overwrite the control parameter of the block i, although it is not limited thereto . This operation can be implemented in an electronic control device including a flash EEPROM 101 that needs to be written. In the foregoing specific embodiment, the shell material in the calibration area of the flash EEPR0M 10 is in step S 1- 2 to the calibration ram 102. Or, if there is no control data in this standard area, you can skip this step. In the foregoing specific embodiment, the controlled target u (such as a car engine) is controlled by an electronic control device ( ECU 10) control, although it is not limited to this. The key point is that the device can include a flash EEPROM 101 and can be implemented in an electronic control device that can overwrite its own data. As detailed above, according to this The invention can overwrite the data of non-volatile memory even during the control operation. 17 200404304. [Schematic description] Figure 1 is a diagram illustrating the overall structure of an ECU (electronic control device) according to a specific embodiment of the present invention. Intent; Figure 2 is a flowchart for explaining the overwriting operation of a flash EEPROM; Figure 3 is another-a flowchart for explaining the overwriting operation of a flash ERPROM An explanatory diagram of the layout diagram; FIG. 5 is another explanatory diagram of a memory layout diagram; FIG. 6 is another explanatory diagram of a memory layout diagram; FIG. 7 is another explanatory diagram of a memory layout diagram [Illustrative Symbols] 10 Electronic Control Unit (ECU) 11 Controlled Target 12 User Interface 100 CPU 101 Flash EEPROM 102 Calibration RAM 110 Address Decoder 111 Initialization Register 112 Super User Mode Register 113 Flash Control Register 120 I / O Interface Address Bus Data Bus Start 18 200404304 (Sl-l) (Sl-2) (Sl-3) (Sl-4) (Sl-5) (Sl-6 ) (Sl-7) (S2-1) (S2-2) (S2-3) (S2-4) (S2-5) 500 501 502 503 504 510 520 530 531 Make sure the calibration area on the flash EEPROM will be calibrated Copy the data in the area to the calibration RAM. Overlap the calibration RAM on the calibration area. Calibration process setting. Super user mode. Use the flash control register to set the The data program is planned to the flash EEPROM. Change the setting of the initialization register. End Calibration process. Issue the data processing instruction. Process the area of the overlapping calibration RAM. According to the data in the calibration RAM. Back Yes No Memory Configuration Diagram Calibration RAM Flash EEPROM (Block 0) Flash EEPROM (Block 1) Calibration Area Memory Configuration Diagram Memory Configuration Diagram Memory Configuration Diagram Calibration Area 19