200302453 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡 單說明） [發明所屬之技術領域] 本發明是有關於一種使用薄膜電晶體作爲畫素驅動 切換元件之主動式矩陣顯不裝置’且特別是有關於一種具 有預充電路(precharge circuit)之主動式矩陣顯示裝置。 [先前技術] 近來，由於具有快速的反應速度、出色的顔色再現 性、低電力消耗、小尺寸的明亮點、高精細度等優點’藉 由薄膜電晶體驅動的主動式矩陣顯示裝置已被使用於許多 高附加價値的商品上，如筆記型電腦。 然而，主動式矩陣顯示裝置在優質產品與高附加價 値產品的應用上仍存在著許多問題。這些問題的其中之一 是有關於用以驅動液晶電容器（liquid crystal capacitor)的 畫素資料(pixel data)。換句話說，爲了驅動液晶電容器而 由源極驅動晶片（source driver)輸出的畫素資料與實際充入 液晶電容器的値會有差異。 爲了消除畫面閃爍以及避免液晶分子劣化，吾人將 畫素資料設計爲週期性改變極性(polarity)之交替電流以驅 動液晶電容器，因此畫素資料會與實際充入電容器的値有 差異。意即，爲了提供週期性的交替電流訊號，充入液晶 電容器中之影像訊號的極性改變，且相對極性之訊號充入 液晶電容器的時間會被延遲。 液晶電容器充電的時間被延遲的因素與導線阻値 10807pif.doc/008 6 200302453 (wiring resistance)以及液晶顯示裝置中連接成矩陣型態的 電容器有關。畢竟，畫素資料與實際充入液晶電容器的値 之間的差異對於顯示特性與影像品質有不好的影響。 因此，吾人必須提供薄膜電晶體足夠的閘極開啓時 間’此外，爲了使源極驅動晶片所提供的影像資料在傳送 至液晶電容器後不會失真，吾人必須開發掃描訊號線 (scanning signal lines)與資料訊號線（data signal lines)的材 料’以使其具有良好的導電特性。 此外，於源極驅動晶片內製作一個能夠預充特定等 級（regular level)電壓至液晶電容器中的預充電路，並驅動 此預充電路來補償上述影像訊號値差異的方法已被提出。 第1圖繪示爲習知具有預充電路之主動式矩陣顯示 裝置的電路圖。如第1圖所示，習知的主動式矩陣顯示裝 置具有多條列方向排列之閘極線（X)以及多條行方向排列 之資料線(Y)。液晶畫素（LC)係以矩陣方式排列於閘極線(X) 與資料線(Y)交會處。雖然第1圖中所繪示的主動式矩陣 顯示器具有液晶畫素（LC)，但可理解的是畫素亦可由其他 光電材料(electrooptics materials)構成。液晶畫素（LC)係藉 由薄膜電晶體(Tr)驅動。薄膜電晶體(Tr)的一個電極係連接 於對應之資料線（Y)，薄膜電晶體的另一個電極係連接於 對應之液晶畫素（LC)，而薄膜電晶體的閘極係連接於對應 之掃描線(X)。V掃描元件（1L，1R)係區分爲左邊與右邊且 與對應的每一條掃描線（X)連接，因此構成一垂直掃描電 路。V掃描元件（1L，1R)會根據垂直時間訊號（VCK)相繼 地掃描垂直起始脈衝（VST)，並在每一水平時間（horizontal 10807pif.doc/008 7 200302453 period)內選擇一列液晶畫素（LC)。換句話說’在對應之水 平轉換器（HSW，l〇a)的控制下’每一條資料線（Y)會與被 取樣的影像訊號（2)連接’並被提供一影像訊號。此外’另 裝設有一 Η掃描元件（4)以控制每一個水平轉換器的開啓 與關閉。即使第1圖中僅繪示一個Η掃描元件(4)，但其 亦可以是由許多Η掃描元件所構成。舉例來說’在960*760 畫素、長寬比爲5到4的情況下，單一列中的960個畫素 可藉由設置80個12位元的暫存器（shift registers)進行定 址（addressed)。意即，Η掃描元件(4)會與特定的時間訊號 (HCK)同步（synchronized)以傳送一 7jc平起始訊號（HST)， 並藉由輸出一取樣脈衝（sampling pulse)以開啓/關閉水平轉 換器(HSW)。Η掃描元件(4)與水平轉換器(HSW，10a)係構 成水平掃描電路，且對應的影像訊號（Vsig)會被提供至每 一條資料線(Y)。接著，影像訊號（Vsig)會藉由開啓的薄膜 電晶體（Tr)輸入至單一水平時間內所選定的一列液晶畫素 (LC)中。 此時，在水平空白時間（horizontal blank period)內， 預充元件（5)會提供一預充訊號水平空白時間，而在單一水 平時間內，當影像訊號（Vsig)未被提供的期間即爲水平空 白時間。當藉由預充控制訊號（PC，6)所控制的預充轉換 器(PWS)開啓或是關閉時，係採用線性方式（line method)同 時提供一預充電壓（Psig，7)於整列畫素（LC)上以提供預充 訊號。當使用如第1圖所繪示的線型態預充方式時，影像 訊號會藉由暫存器相繼地提供至資料線（Y)上，所以畫素 在左/右位置上的時間延遲（time delay)差異將會導致不同 10807pif.doc/008 8 200302453 的浅漏電流（leakage current)。因此，影像品質的均勻性會 惡化。 第2圖繪不爲習知藉由切換P掃插元件所構成的預 充電路以改善第1圖中影像品質的主動矩陣電路圖。請參 照第2圖，基本上，除了預充電路以外，第2圖之習知技 術與第1圖相同，與第1圖中相问的標號代表相同的功能 構件，因此省略其敘述。如第2圖所示，一P掃描元件(4b)、 一類比轉換器（l〇b)以及一預充訊號（Psig)係增設於每一條 資料線的末端，以進行每一個單元(cell)的預充。p掃描元 件（4b)係於相似的時間（similar time)以點型態（d〇t method) 的預充方式提供預充訊號(Psig)至Η掃描元件(4)中，有別 於第1圖中預充元件同時提供預充訊號至同一行之多個單 元的線型態預充方式，因此可以改善影像品質的均勻性。 舉例而言，爲了驅動960*760畫素、長寬比爲5到4的顯 示器，單一列中的960個畫素可能需要80個12位元的暫 存器進行定址。在此情況下，吾人可在提供一個資料電壓 給”i”暫存器之後，再提供一個預充電壓給”i + Ι”暫存器。 然而，習知在第2圖中的電路系統中必須另外增設 一個P掃描元件(4b)，如此將使得硬體更爲複雜。 [發明內容] 爲了解決上述問題，本發明的目的是在提供一種主 動式矩陣顯示裝置，其係將預充電路部份縮到最小以縮減 硬體的架構。 本發明的另一目的是提供一種主動式矩陣顯示裝 置，其將預充電路部份縮到最小的同時，亦可對影像品質 10807pif.doc/008 9 200302453 的均勻性有所改善。 爲達上述目的，本發明提供一種主動式矩陣顯示裝 置，包括：多條列方向排列之閘極線；多條行方向排列之 資料線；多個矩陣排列於閘極線與資料線交會處之畫素i 一個能夠在單一垂直時間內相繼地掃描每一條閘極線的垂 直掃描電路；多個能夠在單一水平時間內輸出切換控制訊 號以控制每一條資料線的Η-P掃描元件；以及多個能夠根 據Η-P掃描元件輸出之切換控制訊號以選擇性地切換一影 像訊號或是一預充訊號至每一條資料線的類比切換器。其 中，Η-P掃描元件在單一個水平時間內是相繼地被驅動， 且當Η-P掃描元件在此單一水平時間內被驅動時，會先提 供預充訊號而後才提供影像訊號。 [實施方式] 本發明將舉較佳實施例並配合所附圖式作更詳細的 說明如後。 第3圖繪示爲依照本發明一較佳實施例主動式矩陣 顯示裝置的電路圖。第3圖係說明將本發明應用在具有 960*760畫素之顯示器中的實施例。配置於同—列中的96〇 個垂直行（vertical columns)係以每十二個區分爲一組，且 分別由80個暫存器負責定址。主動式矩陣顯示裝置具有 多條列方向排列之閘極線（X)以及多條行方向排列之資料 線(Y)。液晶畫素（LC)係以矩陣方式排列於閘極線（χ)與資 料線（Υ)交會處。雖然第1圖中所繪示的主動式矩陣顯示 益具有液晶畫素（LC) ’但可理解的是，畫素亦可由其他光 電材料(electrooptics materials)構成。液晶畫素（LC)係藉由 10807pif.doc/008 10 200302453 薄膜電晶體（Tr)驅動。薄膜電晶體（Tr)的一個電極係連接於 對應之資料線（Y)，薄膜電晶體的另一個電極係連接於對 應之液晶畫素（LC)，而薄膜電晶體的閘極係連接於對應之 掃描線（X)。V掃描元件（1L，1R)係區分爲左邊與右邊且與 對應的每一條掃描線（X)連接，因此構成一垂直掃描電路。 V掃描元件（1L，1R)會根據垂直時間訊號（VCk)相繼地掃 描垂直起始脈衝（VST)，並在每一水平時間（horizontal period)內選擇同一列中的許多液晶單元（C)。換句話說， 每一條資料線（Y)會與被類比轉換器（AS1_AS12)所取樣的 影像訊號（2)連接，並被提供一影像訊號。此外，另裝設有 多個Η-P掃描元件以對同一列進行定址。Η-P掃描元件在 單一水平時間內會相繼地開啓，因此在空白時間（blanking period)內可使用相同的Η-P掃描元件進行預充的動作。設 置於Η-P掃描元件內的類比轉換器(AS1-AS12)會受到H-P 掃描元件的控制而相繼地開啓或關閉。意即，Η-P掃描元 件係與特定的時間訊號（HCK)同步（synchronized)，並藉由 水平起始訊號（HST)輸出的取樣脈衝（sampling pulse)來開 啓/關閉水平轉換器(AS)。Η-P掃描元件與水平轉換器(AS) 係構成水平掃描電路。對應的影像訊號（Vsig)會被提供至 每一條資料線(Y)。接著，影像訊號（Vsig)會藉由開啓狀態 的薄膜電晶體（Tr)輸入至單一水平時間內所選定的一列液 晶單元（C)中。 第4圖繪示爲依照本發明一較佳實施例第3圖中水 平掃描元件操作的電路圖。爲了針對第3圖之整體電路中 每一個單元的存取（accessing)方法進行說明，第4圖詳細 10807pif.doc/008 11 200302453 說明了一個H-P掃描元件與一水平掃描電路之間的關係。 本發明的第4圖中包括：一 H-p掃描元件能夠輸出控制訊 號以選擇性地控制輸入到每一條資料線中的影像訊號（Vsig) 或是預充訊號（Psig);多個能夠根據η-p掃描元件輸出之 控制訊號以選擇性地切換影像訊號（Vsig)或是預充訊號 (Psig)至每一條資料線的類比切換器（AS); 一個能夠相繼 地掃描每一條閘極線的垂直掃描電路；以及一個由開啓/ 關閉液晶層之電晶體（Tr)與電容器所構成的單元（cell unit) 〇 Η-P掃描元件（4)係由暫存器所構成，其係藉由輸出 類比轉換控制訊號（ASW1-ASWN)來提供一取樣影像訊號 (Vsigl-VsigN)至資料線(γ)上，以同步控制多個單元。H-P 掃描元件(4)除了提供影像訊號(Vsigi-VsigN)之外，亦提供 預充所需的控制訊號。 液晶畫素（LC)係藉由薄膜電晶體（Tr)驅動。薄膜電晶 體(Tr)的一個電極係連接於對應之資料線(Y)，薄膜電晶體 的另一^個電極係連接於對應之液晶畫素（LC)，而薄膜電晶 體的閘極係連接於對應之掃描線(X)。V掃描元件係與對 應的每一條掃描線(X)連接，因此構成一垂直掃描電路。V 掃描元件（1L)會根據垂直時間訊號（VCK)相繼地掃描垂直 起始脈衝（VST)，並在每一水平時間（horizontal period)內 選擇同一列中的N個液晶畫素(LC)。換句話說，每一條資 料線(Y)會與被類比轉換器(AS1-ASN)所取樣的影像訊號（2) 連接，並被提供一影像訊號。 設置於Η-P掃描元件內的類比轉換器(AS1-ASN)會受 10807pif.doc/008 12 200302453 到H-P掃描元件的控制而相繼地開啓或關閉。意即’ H-P 掃描元件係與特定的時間訊號（HCK)同步（synchronized) ’ 並藉由水平起始訊號（HST)輸出的取樣脈衝（sampling pulse) 來開啓/關閉水平轉換器（AS)。水平掃描電路係由Η-P掃 描元件與水平轉換器（AS)所構成，且對應的影像訊號（Vsig) 會被提供至每一條資料線（Y)。接著，影像訊號（Vsig)會藉 由開啓狀態的薄膜電晶體（Tr)輸入至單一水平時間內所選 定的一列液晶畫素（LC)中。 第5圖繪示爲第4圖之電路的操作時序圖。請參照 第5圖，當單一水平時間藉由一 HST訊號開始時，用以 輸入Η-P掃描元件之資料値(data value)的預充輸入步驟緊 跟著進行。之後，當一類比轉換開啓/關閉訊號（ASW)被輸 入時，一預充電壓（Psig)則被提供至多條行方向排列之資 料線（Y)上。當預充步驟完後，影像訊號的暫存器藉由一 輸入的預充控制訊號（PC)的啓始（activation)而輸入資料。 接著，影像訊號(Vsig)會藉由類比轉換開啓/關閉訊號(ASW) 而被提供至多條行方向排列之資料線（Y)上，因此每一個 單元會根據影像訊號（Vsig)而開啓或關閉。由此操作時序 圖可知，”單一水平時間”必須維持在大於Η-P掃描元件進 行預充時資料輸入的時間（tl)、預充電壓提供的時間（t3)、 Η-P掃描元件輸入影像訊號的時間（t2)，以及影像訊號提 供的時間（t4)四者之總和。 第6圖繪示爲依照本發明一較佳實施例類比切換器 的閘極層次電路圖。此類比切換器的閘極層次電路圖包 括：一用以輸入預充控制訊號（PC)與類比切換輸入訊號 10807pif.doc/008 13 200302453 (ASWi)的 AND 閘極（VAND1); — 能夠將 AND 閘極（VANDl) 輸出的訊號轉換爲控制訊號，並將一影像訊號（Vsigi)轉換 爲輸入訊號的影像訊號轉換電晶體（VTR); —將預充控制 訊號（PC)反向的反用換流器（INV1); —用以輸入反向預充 控制訊號（PC)與類比轉換輸入訊號（ASWi)的AND閘極 (PAND1); —肯g夠將AND闊f亟（PAND1)的輸出雷只號轉#爲 一控制訊號，並將一預充訊號轉換爲一輸入訊號的預充轉 換電晶體（PTR);以及一能夠將影像訊號轉換電晶體（VTR) 之輸出訊號與預充轉換電晶體（PTR)之輸出訊號反接的輸 出轉換電晶體（OTR)，此輸出轉換電晶體（OTR)可將類比轉 換輸入訊號（ASWi)轉換爲控制訊號，且可輸入反接後的影 像訊號轉換電晶體（VTR)之輸出訊號以及預充轉換電晶體 (PTR)之輸出訊號。輸出轉換電晶體（OTR)的輸出訊號係分 別連接到多條行方向排列之資料線（Yi)上。轉換電晶體 (VTR、PTR、OTR)係由一反用換流器（VIN ' PIN、OIN)、 控制訊號所控制的N通道電晶體(Nl、N2、ΝΑ)，以及分 別與Ν通道電晶體、源極、汲極連接，並藉由反用換流器 (VIN、PIN、ΟΙΝ)反向後之控制訊號所控制的Ρ通道電晶 體（PI、P2、PA)。 以下，將對第6圖的電路操作進行說明。當預充控 制訊號（PC)被啓始（activated)時，影像訊號轉換電晶體(VTR) 與輸出轉換電晶體（OTR)會與類比切換輸入訊號（ASWi)同 步開啓，而預充轉換電晶體（PTR)則維持在關閉的狀態， 故取樣影像訊號（Vsigi)會被傳送至多條行方向排列之資料 線（Yi)上。當預充控制訊號（PC)被啓始（activated)時，輸出 10807pif.doc/008 14 200302453 轉換電晶體（OTR)與預充轉換電晶體（PTR)會與類比切換輸 入訊號（AS Wi)同步開啓，而影像訊號轉換電晶體（VTR)則 維持在關閉的狀態，故預充訊號（Psigi)會被傳送至多條行 方向排列之資料線（Yi)上。因此，本實施例可藉由於類比 轉換器中增加多個電晶體的方式選擇性地篩選影像訊號以 及預充訊號。 根據上述之主動式矩陣顯示裝置及其驅動方法，本 發明可在提工預充訊號的问時’使用一^ Η-P掃描元件輸入 影像訊號。因此，相較於習知電路架構中使用另一個P掃 描元件進行預充，本實施例可以減少構件的數目，也因此 可以降低產品成本。 此外，本發明之主動式矩陣顯示裝置及其驅動方法 能夠解決當使用線型態預充方式時所導致的螢幕均勻性惡 化的問題。 因此，本發明所製造出的高品質主動式矩陣顯示裝 置可滿足螢幕的均勻性與生產率，除此之外，可以將新增 至習知主動式矩陣顯示裝置上的電路數量縮減到最小。 雖然本發明已以不同實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作些許之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 [圖式簡單說明] 第1圖繪示爲習知具有預充電路之主動式矩陣顯示 裝置的電路圖； 第2圖繪示爲習知藉由切換P掃描元件所構成的預 10807pif.doc/008 15 200302453 充電路以改善第1圖中影像品質的主動矩陣電路圖； 第3圖繪示爲依照本發明一較佳實施例主動式矩陣 顯示裝置的電路圖； 第4圖繪示爲依照本發明一較佳實施例第3圖中水 平掃描元件操作的電路圖； 第5圖繪示爲第4圖之電路的操作時序（timing)圖； 以及 第6圖繪示爲依照本發明一較佳實施例類比切換器 (analog switch)的閘極層次電路（gate level circuit)圖。 [圖式標示說明] 1L、1R : V掃描元件 2:影像訊號 4 : Η掃描元件 4b : Ρ掃描元件 5:預充元件 7:預充電壓 10a :水平轉換器 l〇b :類比轉換器 拾、申請專利範圍 1.一種主動式矩陣顯示裝置，包括： 複數個列方向排列之閘極線； 複數個行方向排列之資料線； 複數個矩陣排列於該些閘極線與唉些資料線交會處 之畫素； 16 10807pif.doc/008200302453 发明 Description of the invention (The description of the invention should state: the technical field to which the invention belongs, the prior art, the content, the embodiments, and the drawings are briefly explained. An active matrix display device of a prime-driven switching element 'and, in particular, relates to an active matrix display device having a precharge circuit. [Previous Technology] Recently, an active matrix display device driven by a thin film transistor has been used due to its advantages such as fast response speed, excellent color reproducibility, low power consumption, small size bright spots, and high fineness. On many high value-added products, such as laptops. However, there are still many problems in the application of active matrix display devices to high-quality products and high value-added products. One of these issues is the pixel data used to drive liquid crystal capacitors. In other words, the pixel data output by the source driver in order to drive the liquid crystal capacitor is different from the actual charge of the liquid crystal capacitor. In order to eliminate the flicker of the screen and avoid the degradation of the liquid crystal molecules, I designed the pixel data to periodically change the polarity of the alternating current to drive the liquid crystal capacitor, so the pixel data will be different from the actual charge of the capacitor. This means that in order to provide a periodic alternating current signal, the polarity of the image signal charged in the liquid crystal capacitor changes, and the time for charging the liquid crystal capacitor with a relatively polar signal is delayed. The factors that delay the charging time of liquid crystal capacitors are related to the wire resistance 10807pif.doc / 008 6 200302453 (wiring resistance) and capacitors connected in a matrix type in liquid crystal display devices. After all, the difference between the pixel data and the actual charge in the liquid crystal capacitor has a bad effect on the display characteristics and image quality. Therefore, we must provide a sufficient gate turn-on time of the thin film transistor. In addition, in order to prevent the image data provided by the source driver chip from being distorted after being transmitted to the liquid crystal capacitor, we must develop scanning signal lines and scanning signal lines. The material of data signal lines is to make it have good conductive properties. In addition, a method has been proposed in the source driver chip to precharge a regular level voltage into the liquid crystal capacitor and drive the precharge circuit to compensate for the above-mentioned difference in image signal. FIG. 1 is a circuit diagram of a conventional active matrix display device having a precharge circuit. As shown in FIG. 1, the conventional active matrix display device has a plurality of gate lines (X) arranged in a column direction and a plurality of data lines (Y) arranged in a row direction. Liquid crystal pixels (LC) are arranged in a matrix manner at the intersection of the gate line (X) and the data line (Y). Although the active matrix display shown in FIG. 1 has liquid crystal pixels (LC), it is understood that the pixels may also be composed of other electrooptics materials. Liquid crystal pixels (LC) are driven by thin film transistors (Tr). One electrode of the thin film transistor (Tr) is connected to the corresponding data line (Y), the other electrode of the thin film transistor is connected to the corresponding liquid crystal pixel (LC), and the gate of the thin film transistor is connected to the corresponding Scan line (X). The V scanning elements (1L, 1R) are divided into left and right sides and connected to each corresponding scanning line (X), thus forming a vertical scanning circuit. The V-scan element (1L, 1R) scans the vertical start pulse (VST) successively according to the vertical time signal (VCK), and selects a column of liquid crystal pixels in each horizontal time (horizontal 10807pif.doc / 008 7 200302453 period) (LC). In other words, 'under the control of the corresponding horizontal converter (HSW, 10a)', each data line (Y) will be connected to the sampled image signal (2) 'and provided with an image signal. In addition, there is an additional scan element (4) to control the turning on and off of each level shifter. Even if only one scan unit (4) is shown in Fig. 1, it may be composed of a plurality of scan units. For example, 'in the case of 960 * 760 pixels and an aspect ratio of 5 to 4, 960 pixels in a single column can be addressed by setting 80 12-bit shift registers ( addressed). That is, the scan element (4) is synchronized with a specific time signal (HCK) to transmit a 7jc flat start signal (HST), and outputs a sampling pulse to turn on / off the level. Converter (HSW). The scan element (4) and the horizontal converter (HSW, 10a) form a horizontal scanning circuit, and the corresponding image signal (Vsig) is provided to each data line (Y). Then, the image signal (Vsig) is input to a selected column of liquid crystal pixels (LC) through a turned-on thin film transistor (Tr) in a single horizontal time. At this time, during the horizontal blank period, the pre-charging element (5) will provide a horizontal blanking time for the pre-charge signal. In a single horizontal time, the period when the video signal (Vsig) is not provided is Horizontal blank time. When the pre-charge converter (PWS) controlled by the pre-charge control signal (PC, 6) is turned on or off, a linear method is used to simultaneously provide a pre-charge voltage (Psig, 7) on the entire line. (LC) to provide a pre-charge signal. When using the line type pre-charging method as shown in Figure 1, the image signal will be provided to the data line (Y) one after the other by a register, so the time delay of the pixel in the left / right position ( time delay) difference will lead to different shallow currents (10807pif.doc / 008 8 200302453). As a result, the uniformity of image quality is deteriorated. Fig. 2 is not a conventional active matrix circuit diagram for improving the image quality in Fig. 1 by switching a pre-charging circuit formed by switching P-swap components. Please refer to Fig. 2. Basically, except for the pre-charging circuit, the conventional technology of Fig. 2 is the same as that of Fig. 1. The same reference numerals as those in Fig. 1 represent the same functional components, so the description is omitted. As shown in Figure 2, a P-scan element (4b), an analog converter (10b), and a pre-charge signal (Psig) are added at the end of each data line to perform each cell. Pre-charge. The p-scan element (4b) provides a pre-charge signal (Psig) to the Η-scan element (4) at a similar time in a dot-type pre-charge method, which is different from the first time The pre-charging components in the figure provide a pre-charging method of line type pre-charging signals to multiple units in the same row, so the uniformity of image quality can be improved. For example, to drive a 960 * 760 pixel display with an aspect ratio of 5 to 4, 960 pixels in a single column may require 80 12-bit registers for addressing. In this case, we can provide a pre-charge voltage to the "i + Ι" register after providing a data voltage to the "i" register. However, it is known that an additional P-scan element (4b) must be added to the circuit system in Figure 2. This will make the hardware more complicated. [Summary of the Invention] In order to solve the above-mentioned problems, an object of the present invention is to provide an active matrix display device, which has a structure in which a pre-charging circuit portion is minimized to reduce hardware. Another object of the present invention is to provide an active matrix display device, which can reduce the pre-charging circuit part to a minimum, and can also improve the uniformity of the image quality 10807pif.doc / 008 9 200302453. To achieve the above object, the present invention provides an active matrix display device including: a plurality of gate lines arranged in a column direction; a plurality of data lines arranged in a row direction; and a plurality of matrices arranged at a intersection of the gate lines and the data lines. Pixel i A vertical scanning circuit capable of sequentially scanning each gate line in a single vertical time; multiple Η-P scanning elements capable of outputting a switching control signal to control each data line in a single horizontal time; and multiple An analog switcher that can selectively switch an image signal or a pre-charged signal to each data line according to the switching control signal output by the Η-P scanning element. Among them, the Η-P scanning element is successively driven in a single horizontal time, and when the Η-P scanning element is driven in this single horizontal time, a pre-charge signal is provided first and then an image signal is provided. [Embodiment] The present invention will be described in more detail with reference to the preferred embodiments and the accompanying drawings. FIG. 3 is a circuit diagram of an active matrix display device according to a preferred embodiment of the present invention. FIG. 3 illustrates an embodiment in which the present invention is applied to a display having 960 * 760 pixels. The 96 vertical columns arranged in the same column are divided into groups of twelve, and 80 registers are used for addressing. The active matrix display device has a plurality of gate lines (X) arranged in a column direction and a plurality of data lines (Y) arranged in a row direction. The liquid crystal pixels (LC) are arranged in a matrix manner at the intersection of the gate line (χ) and the data line (Υ). Although the active matrix display shown in Fig. 1 has liquid crystal pixels (LC) ', it can be understood that the pixels may also be composed of other electrooptics materials. Liquid crystal pixels (LC) are driven by 10807pif.doc / 008 10 200302453 thin film transistors (Tr). One electrode of the thin film transistor (Tr) is connected to the corresponding data line (Y), the other electrode of the thin film transistor is connected to the corresponding liquid crystal pixel (LC), and the gate of the thin film transistor is connected to the corresponding Scan line (X). The V scanning elements (1L, 1R) are divided into left and right sides and are connected to each scanning line (X) corresponding thereto, thus forming a vertical scanning circuit. The V scanning element (1L, 1R) sequentially scans the vertical start pulse (VST) according to the vertical time signal (VCk), and selects many liquid crystal cells (C) in the same column in each horizontal period (horizontal period). In other words, each data line (Y) is connected to the image signal (2) sampled by the analog converter (AS1_AS12) and is provided with an image signal. In addition, multiple Η-P scanning elements are installed to address the same column. The Η-P scanning elements are turned on one after the other in a single horizontal time, so the same Η-P scanning element can be used for pre-charging during the blanking period. The analog converters (AS1-AS12) set in the Η-P scanning element are controlled by the H-P scanning element to be turned on or off one after the other. In other words, the Η-P scanning element is synchronized with a specific time signal (HCK), and turns on / off the horizontal converter (AS) with a sampling pulse output by the horizontal start signal (HST). . The Η-P scanning element and the horizontal converter (AS) form a horizontal scanning circuit. The corresponding video signal (Vsig) is provided to each data line (Y). Then, the video signal (Vsig) is input to the selected liquid crystal unit (C) in a single horizontal time by the thin film transistor (Tr) in the on state. Fig. 4 is a circuit diagram showing the operation of the horizontal scanning element in Fig. 3 according to a preferred embodiment of the present invention. In order to explain the accessing method of each unit in the overall circuit of Fig. 3, Fig. 4 details 10807pif.doc / 008 11 200302453 to explain the relationship between an H-P scanning element and a horizontal scanning circuit. The fourth diagram of the present invention includes: an Hp scanning element can output a control signal to selectively control a video signal (Vsig) or a pre-charge signal (Psig) input to each data line; a plurality of Control signal output by the p-scan element to selectively switch the image signal (Vsig) or pre-charge signal (Psig) to each data line analog switch (AS); one can scan each gate line's vertical A scanning circuit; and a cell unit composed of a transistor (Tr) and a capacitor that turn on / off the liquid crystal layer. The Η-P scanning element (4) is composed of a register, which is analogized by output The control signals (ASW1-ASWN) are converted to provide a sampling image signal (Vsigl-VsigN) to the data line (γ) to control multiple units simultaneously. The H-P scanning element (4) provides not only the image signal (Vsigi-VsigN), but also the control signal required for pre-charging. Liquid crystal pixels (LC) are driven by thin film transistors (Tr). One electrode of the thin film transistor (Tr) is connected to the corresponding data line (Y), the other electrode of the thin film transistor is connected to the corresponding liquid crystal pixel (LC), and the gate of the thin film transistor is connected On the corresponding scan line (X). The V scanning element is connected to each corresponding scanning line (X), and thus constitutes a vertical scanning circuit. The V-scan element (1L) scans the vertical start pulse (VST) successively according to the vertical time signal (VCK), and selects N liquid crystal pixels (LC) in the same column in each horizontal period. In other words, each data line (Y) is connected to the image signal (2) sampled by the analog converter (AS1-ASN) and is provided with an image signal. The analog converters (AS1-ASN) set in the Η-P scanning element will be turned on or off successively under the control of 10807pif.doc / 008 12 200302453 to H-P scanning element. This means that the 'H-P scanning element is synchronized with a specific time signal (HCK)' and turns on / off the horizontal converter (AS) with a sampling pulse output by the horizontal start signal (HST). The horizontal scanning circuit is composed of a Η-P scanning element and a horizontal converter (AS), and the corresponding image signal (Vsig) is provided to each data line (Y). Then, the video signal (Vsig) is input to a selected column of liquid crystal pixels (LC) through a thin film transistor (Tr) in an on state in a single horizontal time. FIG. 5 is a timing diagram of the operation of the circuit of FIG. 4. Please refer to Fig. 5. When a single horizontal time is started by an HST signal, the pre-charge input step for inputting the data value of the Η-P scanning element follows. Then, when an analog conversion on / off signal (ASW) is input, a precharge voltage (Psig) is provided to a plurality of data lines (Y) arranged in the row direction. After the pre-charging step is completed, the register of the image signal is inputted with the activation of an input pre-charging control signal (PC). Then, the video signal (Vsig) is provided to the data lines (Y) arranged in multiple row directions by analog switch on / off signal (ASW), so each unit will be turned on or off according to the video signal (Vsig) . It can be seen from the operation timing diagram that the "single level time" must be maintained longer than the time (tl) for data input during pre-charging of the Η-P scanning element, the time provided by the pre-charging voltage (t3), and the input image of the Η-P scanning element. The sum of the signal time (t2) and the time provided by the video signal (t4). FIG. 6 is a gate-level circuit diagram of an analog switcher according to a preferred embodiment of the present invention. The gate-level circuit diagram of the analog switch includes: an AND gate (VAND1) for inputting the precharge control signal (PC) and an analog switch input signal 10807pif.doc / 008 13 200302453 (ASWi); — able to gate the AND gate The signal output from the VAND1 is converted into a control signal, and an image signal (Vsigi) is converted into an input signal. The image signal conversion transistor (VTR) is used to reverse the precharge control signal (PC). (INV1); —AND gate (PAND1) used to input reverse precharge control signal (PC) and analog conversion input signal (ASWi); —Ken g is enough to output the AND wide f No. transfer # is a control signal and a precharge conversion transistor (PTR) that converts a precharge signal into an input signal; and a output signal and precharge conversion transistor that can convert the image signal conversion transistor (VTR) The output conversion transistor (OTR) of the (PTR) output signal is reversely connected. This output conversion transistor (OTR) can convert the analog conversion input signal (ASWi) into a control signal, and can input the reversed image signal conversion transistor. Crystal (VTR) output signal and pre- Conversion transistor (PTR) of the output signal. The output signals of the output switching transistor (OTR) are respectively connected to a plurality of data lines (Yi) arranged in the row direction. The conversion transistor (VTR, PTR, OTR) is an N-channel transistor (Nl, N2, NA) controlled by a inverter (VIN 'PIN, OIN), a control signal, and an N-channel transistor. P-channel transistors (PI, P2, PA) controlled by the control signals after the inverters (VIN, PIN, ΙΝΝ) are reversed, connected to the source, the drain, and the drain. Hereinafter, the circuit operation of FIG. 6 will be described. When the precharge control signal (PC) is activated, the video signal conversion transistor (VTR) and output conversion transistor (OTR) are turned on simultaneously with the analog switch input signal (ASWi), and the precharge conversion transistor (PTR) is kept closed, so the sampled image signal (Vsigi) will be transmitted to the data lines (Yi) arranged in multiple row directions. When the pre-charge control signal (PC) is activated, the output 10807pif.doc / 008 14 200302453 switching transistor (OTR) and pre-charge switching transistor (PTR) will be synchronized with the analog switching input signal (AS Wi) It is on, and the image signal conversion transistor (VTR) is kept off, so the pre-charge signal (Psigi) will be transmitted to multiple data lines (Yi) arranged in the row direction. Therefore, in this embodiment, the image signal and the precharge signal can be selectively filtered by adding multiple transistors in the analog converter. According to the above-mentioned active matrix display device and its driving method, the present invention can input a video signal using a ^ Η-P scanning element when the pre-charge signal of the lift is asked. Therefore, compared with using another P-scan element for precharging in the conventional circuit architecture, this embodiment can reduce the number of components, and thus can reduce the product cost. In addition, the active matrix display device and the driving method thereof of the present invention can solve the problem of worsening the uniformity of the screen caused by the linear pre-charging method. Therefore, the high-quality active matrix display device manufactured by the present invention can meet the uniformity and productivity of the screen. In addition, the number of circuits added to the conventional active matrix display device can be reduced to a minimum. Although the present invention has been disclosed in different embodiments as above, it is not intended to limit the present invention. Any person skilled in the art can make some changes and decorations without departing from the spirit and scope of the present invention. The scope of protection shall be determined by the scope of the attached patent application. [Brief description of the diagram] Fig. 1 shows a circuit diagram of a conventional active matrix display device with a pre-charging circuit; Fig. 2 shows a pre-configuration of a conventional 10807pif.doc / 008 by switching a P-scan element. 15 200302453 Active matrix circuit diagram for charging circuit to improve the image quality in the first picture; FIG. 3 shows a circuit diagram of an active matrix display device according to a preferred embodiment of the present invention; FIG. 4 shows a comparative diagram according to the present invention. The preferred embodiment is a circuit diagram of the horizontal scanning element operation in FIG. 3; FIG. 5 is a timing diagram of the operation of the circuit in FIG. 4; and FIG. 6 is an analog switch in accordance with a preferred embodiment of the present invention. Gate level circuit diagram of the analog switch. [Illustration of diagrammatic symbols] 1L, 1R: V scanning element 2: image signal 4: Η scanning element 4b: P scanning element 5: pre-charging element 7: pre-charging voltage 10a: horizontal converter 10b: analog converter 1. Patent application scope 1. An active matrix display device comprising: a plurality of gate lines arranged in a column direction; a plurality of data lines arranged in a row direction; a plurality of matrices arranged at the intersection of the gate lines and the data lines Pixels at the office; 16 10807pif.doc / 008